[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
authorbugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Fri, 3 Apr 2020 11:00:13 +0000 (11:00 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Fri, 3 Apr 2020 11:00:15 +0000 (12:00 +0100)
a9/957a410dcf6e19dc1c07b1b485eb1721d111e2 [new file with mode: 0644]

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+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Fri, 03 Apr 2020 11:00:13 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: whitequark@whitequark.org
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: lkcl@lkcl.net
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+Message-ID: <bug-276-13-e9BbWsSrHS@http.bugs.libre-riscv.org/>
+In-Reply-To: <bug-276-13@http.bugs.libre-riscv.org/>
+References: <bug-276-13@http.bugs.libre-riscv.org/>
+X-Bugzilla-URL: http://bugs.libre-riscv.org/
+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
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