type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
+boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_panic=true
phys_addr_range_64=40
power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
+readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
+image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
threadPolicy=RoundRobin
tracer=system.cpu0.tracer
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
sequential_access=false
size=32768
system=system
+tag_latency=2
tags=system.cpu0.dcache.tags
tgts_per_mshr=8
write_buffers=16
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=2
[system.cpu0.dstage2_mmu]
type=ArmStage2MMU
[system.cpu0.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
-children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
+children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
eventq_index=0
-opClasses=system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25
+opClasses=system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses27
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
-opClass=FloatMult
+opClass=FloatMisc
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
-opClass=FloatDiv
+opClass=FloatMult
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
-opClass=FloatSqrt
+opClass=FloatMultAcc
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
-opClass=SimdAdd
+opClass=FloatDiv
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
-opClass=SimdAddAcc
+opClass=FloatSqrt
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
-opClass=SimdAlu
+opClass=SimdAdd
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
-opClass=SimdCmp
+opClass=SimdAddAcc
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
-opClass=SimdCvt
+opClass=SimdAlu
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
-opClass=SimdMisc
+opClass=SimdCmp
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
-opClass=SimdMult
+opClass=SimdCvt
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
-opClass=SimdMultAcc
+opClass=SimdMisc
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
-opClass=SimdShift
+opClass=SimdMult
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
-opClass=SimdShiftAcc
+opClass=SimdMultAcc
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
-opClass=SimdSqrt
+opClass=SimdShift
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatAdd
+opClass=SimdShiftAcc
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatAlu
+opClass=SimdSqrt
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatCmp
+opClass=SimdFloatAdd
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatCvt
+opClass=SimdFloatAlu
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatDiv
+opClass=SimdFloatCmp
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatMisc
+opClass=SimdFloatCvt
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatMult
+opClass=SimdFloatDiv
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatMultAcc
+opClass=SimdFloatMisc
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
+opClass=SimdFloatMult
+
+[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses26]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatMultAcc
+
+[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses27]
+type=MinorOpClass
+eventq_index=0
opClass=SimdFloatSqrt
[system.cpu0.executeFuncUnits.funcUnits4.timings]
[system.cpu0.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
-children=opClasses0 opClasses1
+children=opClasses0 opClasses1 opClasses2 opClasses3
eventq_index=0
-opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1
+opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses3
[system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=MemWrite
+[system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses2]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatMemRead
+
+[system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses3]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatMemWrite
+
[system.cpu0.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
sequential_access=false
size=32768
system=system
+tag_latency=1
tags=system.cpu0.icache.tags
tgts_per_mshr=8
write_buffers=8
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=1
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=1
[system.cpu0.interrupts]
type=ArmInterrupts
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
+data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
sequential_access=false
size=1048576
system=system
+tag_latency=12
tags=system.cpu0.l2cache.tags
tgts_per_mshr=8
write_buffers=8
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=12
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
+tag_latency=12
[system.cpu0.toL2Bus]
type=CoherentXBar
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
threadPolicy=RoundRobin
tracer=system.cpu1.tracer
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
sequential_access=false
size=32768
system=system
+tag_latency=2
tags=system.cpu1.dcache.tags
tgts_per_mshr=8
write_buffers=16
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=2
[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
[system.cpu1.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
-children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
+children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
eventq_index=0
-opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25
+opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses27
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
-opClass=FloatMult
+opClass=FloatMisc
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
-opClass=FloatDiv
+opClass=FloatMult
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
-opClass=FloatSqrt
+opClass=FloatMultAcc
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
-opClass=SimdAdd
+opClass=FloatDiv
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
-opClass=SimdAddAcc
+opClass=FloatSqrt
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
-opClass=SimdAlu
+opClass=SimdAdd
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
-opClass=SimdCmp
+opClass=SimdAddAcc
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
-opClass=SimdCvt
+opClass=SimdAlu
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
-opClass=SimdMisc
+opClass=SimdCmp
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
-opClass=SimdMult
+opClass=SimdCvt
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
-opClass=SimdMultAcc
+opClass=SimdMisc
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
-opClass=SimdShift
+opClass=SimdMult
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
-opClass=SimdShiftAcc
+opClass=SimdMultAcc
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
-opClass=SimdSqrt
+opClass=SimdShift
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatAdd
+opClass=SimdShiftAcc
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatAlu
+opClass=SimdSqrt
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatCmp
+opClass=SimdFloatAdd
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatCvt
+opClass=SimdFloatAlu
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatDiv
+opClass=SimdFloatCmp
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatMisc
+opClass=SimdFloatCvt
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatMult
+opClass=SimdFloatDiv
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatMultAcc
+opClass=SimdFloatMisc
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
+opClass=SimdFloatMult
+
+[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses26]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatMultAcc
+
+[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses27]
+type=MinorOpClass
+eventq_index=0
opClass=SimdFloatSqrt
[system.cpu1.executeFuncUnits.funcUnits4.timings]
[system.cpu1.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
-children=opClasses0 opClasses1
+children=opClasses0 opClasses1 opClasses2 opClasses3
eventq_index=0
-opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1
+opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses3
[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=MemWrite
+[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses2]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatMemRead
+
+[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses3]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatMemWrite
+
[system.cpu1.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
sequential_access=false
size=32768
system=system
+tag_latency=1
tags=system.cpu1.icache.tags
tgts_per_mshr=8
write_buffers=8
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=1
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=1
[system.cpu1.interrupts]
type=ArmInterrupts
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
+data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
sequential_access=false
size=1048576
system=system
+tag_latency=12
tags=system.cpu1.l2cache.tags
tgts_per_mshr=8
write_buffers=8
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=12
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
+tag_latency=12
[system.cpu1.toL2Bus]
type=CoherentXBar
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
+data_latency=50
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=50
is_read_only=false
max_miss_count=0
mshrs=20
sequential_access=false
size=1024
system=system
+tag_latency=50
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
assoc=8
block_size=64
clk_domain=system.clk_domain
+data_latency=50
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=50
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1024
+tag_latency=50
[system.l2c]
type=Cache
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
sequential_access=false
size=4194304
system=system
+tag_latency=20
tags=system.l2c.tags
tgts_per_mshr=12
write_buffers=8
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=4194304
+tag_latency=20
[system.membus]
type=CoherentXBar
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+info: Entering event queue @ 0. Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: instruction 'mcr bpiall' unimplemented
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:42:59
-gem5 executing on e108600-lin, pid 17317
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor-dual
+gem5 compiled Mar 29 2017 19:38:26
+gem5 started Mar 29 2017 19:38:42
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83600
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2848926718000 because m5_exit instruction encountered
+Exiting @ tick 2848623849000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.848599 # Number of seconds simulated
-sim_ticks 2848598682500 # Number of ticks simulated
-final_tick 2848598682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 262669 # Simulator instruction rate (inst/s)
-host_op_rate 318064 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5881753499 # Simulator tick rate (ticks/s)
-host_mem_usage 626168 # Number of bytes of host memory used
-host_seconds 484.31 # Real time elapsed on the host
-sim_insts 127213455 # Number of instructions simulated
-sim_ops 154041729 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker 9280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1663936 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 1359352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8597824 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 234560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 659412 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 325376 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12852044 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1663936 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 234560 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1898496 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8978368 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8995932 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 145 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 25999 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 21764 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 134341 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 3665 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 10324 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 5084 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 201358 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 140287 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 144678 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 3258 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 584124 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 477200 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 3018264 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 449 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 82342 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 231486 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 114223 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4511707 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 584124 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 82342 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 666467 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3151854 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6152 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3158020 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3151854 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 3258 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 584124 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 483352 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 3018264 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 449 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 82342 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 231500 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 114223 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7669728 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 201358 # Number of read requests accepted
-system.physmem.writeReqs 144678 # Number of write requests accepted
-system.physmem.readBursts 201358 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 144678 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 12877760 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9008896 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 12852044 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8995932 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 12337 # Per bank write bursts
-system.physmem.perBankRdBursts::1 12726 # Per bank write bursts
-system.physmem.perBankRdBursts::2 13547 # Per bank write bursts
-system.physmem.perBankRdBursts::3 13037 # Per bank write bursts
-system.physmem.perBankRdBursts::4 15119 # Per bank write bursts
-system.physmem.perBankRdBursts::5 12845 # Per bank write bursts
-system.physmem.perBankRdBursts::6 12657 # Per bank write bursts
-system.physmem.perBankRdBursts::7 13022 # Per bank write bursts
-system.physmem.perBankRdBursts::8 12280 # Per bank write bursts
-system.physmem.perBankRdBursts::9 12341 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11583 # Per bank write bursts
-system.physmem.perBankRdBursts::11 10739 # Per bank write bursts
-system.physmem.perBankRdBursts::12 12026 # Per bank write bursts
-system.physmem.perBankRdBursts::13 12946 # Per bank write bursts
-system.physmem.perBankRdBursts::14 12179 # Per bank write bursts
-system.physmem.perBankRdBursts::15 11831 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8873 # Per bank write bursts
-system.physmem.perBankWrBursts::1 9291 # Per bank write bursts
-system.physmem.perBankWrBursts::2 9856 # Per bank write bursts
-system.physmem.perBankWrBursts::3 9274 # Per bank write bursts
-system.physmem.perBankWrBursts::4 8405 # Per bank write bursts
-system.physmem.perBankWrBursts::5 8988 # Per bank write bursts
-system.physmem.perBankWrBursts::6 8961 # Per bank write bursts
-system.physmem.perBankWrBursts::7 9107 # Per bank write bursts
-system.physmem.perBankWrBursts::8 8695 # Per bank write bursts
-system.physmem.perBankWrBursts::9 8769 # Per bank write bursts
-system.physmem.perBankWrBursts::10 8272 # Per bank write bursts
-system.physmem.perBankWrBursts::11 7845 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8751 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8985 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8630 # Per bank write bursts
-system.physmem.perBankWrBursts::15 8062 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 74 # Number of times write queue was full causing retry
-system.physmem.totGap 2848598144000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 555 # Read request sizes (log2)
-system.physmem.readPktSize::3 28 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 200775 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 4391 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 140287 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 85113 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 63389 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 11790 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 9690 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 8148 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 6744 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 5598 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 4878 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 4009 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1035 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 281 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 239 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 165 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 134 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2537 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 3403 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4421 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5052 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6114 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6454 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 7065 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 7505 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 8553 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 8479 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 9706 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 10172 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 8910 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 8556 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 8923 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 9945 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 8410 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 8137 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 883 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 583 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 478 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 405 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 334 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 317 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 271 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 267 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 249 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 284 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 263 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 264 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 233 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 221 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 181 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 223 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 208 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 239 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 202 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 172 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 173 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 184 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 209 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 195 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 131 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 188 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 225 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 216 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 128 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 216 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 88566 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 247.121830 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 141.476955 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 302.598654 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 44693 50.46% 50.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 18724 21.14% 71.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6637 7.49% 79.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3795 4.28% 83.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2919 3.30% 86.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1572 1.77% 88.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 960 1.08% 89.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1024 1.16% 90.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8242 9.31% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 88566 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6985 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 28.806586 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 558.021687 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6983 99.97% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6985 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6985 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.152326 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.495944 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 14.110349 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5869 84.02% 84.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 441 6.31% 90.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 79 1.13% 91.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 44 0.63% 92.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 241 3.45% 95.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 25 0.36% 95.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 15 0.21% 96.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 10 0.14% 96.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 17 0.24% 96.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 8 0.11% 96.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 3 0.04% 96.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 7 0.10% 96.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 146 2.09% 98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 4 0.06% 98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 4 0.06% 98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 6 0.09% 99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 7 0.10% 99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 1 0.01% 99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 2 0.03% 99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 3 0.04% 99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 3 0.04% 99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 11 0.16% 99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 2 0.03% 99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 2 0.03% 99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 10 0.14% 99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 2 0.03% 99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 3 0.04% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 3 0.04% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 3 0.04% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 2 0.03% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 3 0.04% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 1 0.01% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183 2 0.03% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191 2 0.03% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 3 0.04% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6985 # Writes before turning the bus around for reads
-system.physmem.totQLat 9483410947 # Total ticks spent queuing
-system.physmem.totMemAccLat 13256192197 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1006075000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 47130.74 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 65880.74 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 4.52 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 4.51 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.16 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.06 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.98 # Average write queue length when enqueuing
-system.physmem.readRowHits 166670 # Number of row buffer hits during reads
-system.physmem.writeRowHits 86742 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.83 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 61.61 # Row buffer hit rate for writes
-system.physmem.avgGap 8232086.10 # Average gap between requests
-system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 334044900 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 177549075 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 751770600 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 379781100 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 5711234880.000001 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 5249821980 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 307614240 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 11585671230 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 8434613280 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 670304268120 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 703238620035 # Total energy per rank (pJ)
-system.physmem_0.averagePower 246.871777 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 2836104738853 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 545953693 # Time in different power states
-system.physmem_0.memoryStateTime::REF 2426690000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 2788907518000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 21965166332 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 9346009704 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 25407344771 # Time in different power states
-system.physmem_1.actEnergy 298323480 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 158558895 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 684904500 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 355006980 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 5713078800.000001 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 5198973990 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 317598720 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 10947475860 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 8696180160 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 670560217290 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 702932935245 # Total energy per rank (pJ)
-system.physmem_1.averagePower 246.764467 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 2836364452001 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 573854684 # Time in different power states
-system.physmem_1.memoryStateTime::REF 2428124000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 2789710596750 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 22646269258 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 9232187315 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 24007650493 # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 21387746 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 14055793 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 1067110 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 13655999 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 8982856 # Number of BTB hits
-system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 65.779560 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 3510572 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 218030 # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups 788067 # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits 592988 # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses 195079 # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted 105213 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks 69629 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 69629 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46094 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23535 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 69629 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 69629 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 69629 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 7649 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 12135.050333 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 10988.955041 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 11832.363963 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 7639 99.87% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 2 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 7649 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 338892000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 338892000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 338892000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 5959 77.91% 77.91% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1690 22.09% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 7649 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69629 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69629 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7649 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7649 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 77278 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.inst_hits 0 # ITB inst hits
-system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 17966885 # DTB read hits
-system.cpu0.dtb.read_misses 63028 # DTB read misses
-system.cpu0.dtb.write_hits 15039551 # DTB write hits
-system.cpu0.dtb.write_misses 6601 # DTB write misses
-system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3754 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1491 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 2059 # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 18029913 # DTB read accesses
-system.cpu0.dtb.write_accesses 15046152 # DTB write accesses
-system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 33006436 # DTB hits
-system.cpu0.dtb.misses 69629 # DTB misses
-system.cpu0.dtb.accesses 33076065 # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks 4318 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 4318 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1 325 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3993 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 4318 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 4318 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 4318 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 2683 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12304.137160 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11560.884208 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 4695.711947 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191 502 18.71% 18.71% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383 1984 73.95% 92.66% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575 147 5.48% 98.14% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767 31 1.16% 99.29% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-40959 18 0.67% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 2683 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 338263500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 338263500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 338263500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 2363 88.07% 88.07% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 320 11.93% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 2683 # Table walker page sizes translated
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4318 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4318 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2683 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2683 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 7001 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 39752533 # ITB inst hits
-system.cpu0.itb.inst_misses 4318 # ITB inst misses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2396 # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 7865 # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 39756851 # ITB inst accesses
-system.cpu0.itb.hits 39752533 # DTB hits
-system.cpu0.itb.misses 4318 # DTB misses
-system.cpu0.itb.accesses 39756851 # DTB accesses
-system.cpu0.numPwrStateTransitions 3708 # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples 1854 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean 1488611861.955232 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev 23946276211.601498 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows 1085 58.52% 58.52% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10 762 41.10% 99.62% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 499963838164 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total 1854 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON 88712290435 # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 2759886392065 # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles 177427128 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 82154396 # Number of instructions committed
-system.cpu0.committedOps 98918766 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 5358225 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 1854 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 5519798084 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.159679 # CPI: cycles per instruction
-system.cpu0.ipc 0.463032 # IPC: instructions per cycle
-system.cpu0.op_class_0::No_OpClass 2315 0.00% 0.00% # Class of committed instruction
-system.cpu0.op_class_0::IntAlu 65610842 66.33% 66.33% # Class of committed instruction
-system.cpu0.op_class_0::IntMult 94061 0.10% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::IntDiv 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::FloatAdd 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::FloatCmp 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::FloatCvt 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::FloatMult 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::FloatDiv 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::FloatMisc 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdAdd 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdAlu 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdCmp 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdCvt 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdMisc 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdMult 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdShift 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMisc 8175 0.01% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.43% # Class of committed instruction
-system.cpu0.op_class_0::MemRead 17407324 17.60% 84.03% # Class of committed instruction
-system.cpu0.op_class_0::MemWrite 15784753 15.96% 99.99% # Class of committed instruction
-system.cpu0.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction
-system.cpu0.op_class_0::FloatMemWrite 8588 0.01% 100.00% # Class of committed instruction
-system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.op_class_0::total 98918766 # Class of committed instruction
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed
-system.cpu0.tickCycles 124478065 # Number of cycles that the object actually ticked
-system.cpu0.idleCycles 52949063 # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements 756000 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 495.989536 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 31503611 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 756512 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 41.643240 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 356904000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.989536 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968730 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.968730 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 66089687 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 66089687 # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data 16428136 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 16428136 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 13890443 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 13890443 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 328324 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 328324 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374119 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 374119 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370195 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 370195 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 30318579 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 30318579 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 30646903 # number of overall hits
-system.cpu0.dcache.overall_hits::total 30646903 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 460755 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 460755 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 603639 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 603639 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141924 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 141924 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21489 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 21489 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20512 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 20512 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1064394 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1064394 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1206318 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1206318 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6676359500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 6676359500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11544866500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 11544866500 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336675500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 336675500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 485473000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 485473000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 539500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 539500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 18221226000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 18221226000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 18221226000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 18221226000 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 16888891 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 16888891 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 14494082 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 14494082 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470248 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 470248 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 395608 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 395608 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390707 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 390707 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 31382973 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 31382973 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 31853221 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 31853221 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027282 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.027282 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041647 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.041647 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301807 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301807 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054319 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054319 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052500 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052500 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033916 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.033916 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037871 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.037871 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14490.042430 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14490.042430 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19125.448323 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 19125.448323 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15667.341430 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15667.341430 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23667.755460 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23667.755460 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17118.873274 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 17118.873274 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15104.828080 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 15104.828080 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks 756000 # number of writebacks
-system.cpu0.dcache.writebacks::total 756000 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 45822 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 45822 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266133 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 266133 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14947 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14947 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 311955 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 311955 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 311955 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 311955 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 414933 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 414933 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337506 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 337506 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108299 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 108299 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6542 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6542 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20512 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 20512 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 752439 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 752439 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 860738 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 860738 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20603 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20603 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19302 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19302 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39905 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39905 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5470255000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5470255000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6299771000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6299771000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1751643500 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1751643500 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104376500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104376500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 464977000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 464977000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 523500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 523500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11770026000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 11770026000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13521669500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 13521669500 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4611679000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4611679000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4611679000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4611679000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024568 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024568 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023286 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023286 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230302 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230302 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016537 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016537 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052500 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052500 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023976 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.023976 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027022 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.027022 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13183.465764 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13183.465764 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18665.656314 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18665.656314 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16174.142882 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16174.142882 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15954.830327 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15954.830327 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22668.535491 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22668.535491 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15642.498595 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15642.498595 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15709.390662 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15709.390662 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223835.315245 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223835.315245 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115566.445308 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115566.445308 # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements 2036864 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.774783 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 37707013 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 2037376 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 18.507636 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 6575306000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774783 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999560 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999560 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 81526207 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 81526207 # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst 37707013 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 37707013 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 37707013 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 37707013 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 37707013 # number of overall hits
-system.cpu0.icache.overall_hits::total 37707013 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 2037394 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 2037394 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 2037394 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 2037394 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 2037394 # number of overall misses
-system.cpu0.icache.overall_misses::total 2037394 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20429568000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 20429568000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 20429568000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 20429568000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 20429568000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 20429568000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 39744407 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 39744407 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 39744407 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 39744407 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 39744407 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 39744407 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051262 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.051262 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051262 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.051262 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051262 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.051262 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10027.303506 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10027.303506 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10027.303506 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10027.303506 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10027.303506 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10027.303506 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks 2036864 # number of writebacks
-system.cpu0.icache.writebacks::total 2036864 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2037394 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 2037394 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 2037394 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 2037394 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 2037394 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 2037394 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total 3277 # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total 3277 # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19410871500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 19410871500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19410871500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 19410871500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19410871500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 19410871500 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 323882000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 323882000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 323882000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total 323882000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051262 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051262 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051262 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.051262 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051262 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.051262 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9527.303752 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9527.303752 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9527.303752 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 9527.303752 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9527.303752 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 9527.303752 # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98834.909979 # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98834.909979 # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927829 # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified 1927948 # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit 103 # number of redundant prefetches already in prefetch queue
-system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage 243748 # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements 297127 # number of replacements
-system.cpu0.l2cache.tags.tagsinuse 15638.814401 # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs 2702273 # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs 312734 # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs 8.640803 # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 14568.839087 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.655947 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.055478 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1008.263889 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks 0.889211 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003763 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000003 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.061540 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total 0.954517 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022 252 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15345 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 32 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 142 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1191 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7256 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5870 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 777 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.015381 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936584 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses 95152070 # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses 95152070 # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 82993 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5634 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total 88627 # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks 506169 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total 506169 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks 2242578 # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total 2242578 # number of WritebackClean hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data 235126 # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total 235126 # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1941946 # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total 1941946 # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 414577 # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total 414577 # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 82993 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5634 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst 1941946 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data 649703 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total 2680276 # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 82993 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5634 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst 1941946 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data 649703 # number of overall hits
-system.cpu0.l2cache.overall_hits::total 2680276 # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 792 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 89 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total 881 # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56686 # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total 56686 # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20512 # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total 20512 # number of SCUpgradeReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45703 # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total 45703 # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 95448 # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total 95448 # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 115192 # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total 115192 # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 792 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker 89 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst 95448 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data 160895 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total 257224 # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 792 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker 89 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst 95448 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data 160895 # number of overall misses
-system.cpu0.l2cache.overall_misses::total 257224 # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 39518000 # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2258000 # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total 41776000 # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 46480500 # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total 46480500 # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 11233000 # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 11233000 # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 499500 # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 499500 # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2934504499 # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total 2934504499 # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4610090000 # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4610090000 # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3801275499 # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3801275499 # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 39518000 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2258000 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4610090000 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data 6735779998 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total 11387645998 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 39518000 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2258000 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4610090000 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data 6735779998 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total 11387645998 # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 83785 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5723 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total 89508 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks 506169 # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total 506169 # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks 2242578 # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total 2242578 # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56686 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total 56686 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20512 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total 20512 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 280829 # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total 280829 # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 2037394 # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total 2037394 # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 529769 # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total 529769 # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 83785 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5723 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst 2037394 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data 810598 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total 2937500 # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 83785 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5723 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst 2037394 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data 810598 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total 2937500 # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009453 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015551 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total 0.009843 # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.162743 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total 0.162743 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.046848 # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.046848 # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.217438 # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.217438 # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009453 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015551 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.046848 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198489 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total 0.087566 # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009453 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015551 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.046848 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198489 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total 0.087566 # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 49896.464646 # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 25370.786517 # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 47418.842225 # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 819.964365 # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 819.964365 # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 547.630655 # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 547.630655 # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64208.137300 # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64208.137300 # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 48299.492918 # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 48299.492918 # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32999.474781 # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32999.474781 # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 49896.464646 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 25370.786517 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 48299.492918 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41864.445744 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 44271.319931 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 49896.464646 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 25370.786517 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 48299.492918 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41864.445744 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 44271.319931 # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked
-system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches 10950 # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks 237127 # number of writebacks
-system.cpu0.l2cache.writebacks::total 237127 # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3260 # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total 3260 # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 60 # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 60 # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 437 # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 437 # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 60 # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3697 # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total 3758 # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 60 # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3697 # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total 3758 # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 791 # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 89 # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total 880 # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 267610 # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total 267610 # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56686 # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56686 # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20512 # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20512 # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42443 # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total 42443 # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 95388 # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 95388 # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 114755 # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 114755 # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 791 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 89 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 95388 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data 157198 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total 253466 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 791 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 89 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 95388 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data 157198 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 267610 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total 521076 # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20603 # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23880 # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19302 # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19302 # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39905 # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 43182 # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 34749000 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1724000 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 36473000 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17027732697 # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17027732697 # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 983576499 # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 983576499 # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 310242000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 310242000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 403500 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 403500 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2182275999 # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2182275999 # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 4035832000 # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 4035832000 # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 3088712499 # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 3088712499 # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 34749000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1724000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 4035832000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5270988498 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total 9343293498 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 34749000 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1724000 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4035832000 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5270988498 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17027732697 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 26371026195 # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 297666000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4446739000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4744405000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 297666000 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4446739000 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4744405000 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009441 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015551 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009832 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.151135 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.151135 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046819 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046819 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.216613 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.216613 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009441 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015551 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046819 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.193928 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.086286 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009441 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015551 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046819 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.193928 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177388 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 41446.590909 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63628.910343 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63628.910343 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17351.312476 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17351.312476 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15124.902496 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15124.902496 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 51416.629338 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 51416.629338 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42309.640626 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42309.640626 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26915.711725 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26915.711725 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42309.640626 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33530.887785 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36862.117594 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42309.640626 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33530.887785 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63628.910343 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50608.790647 # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215829.684997 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198676.926298 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111433.128681 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109869.968969 # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests 5741859 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2893899 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44137 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 221175 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 217002 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4173 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq 125397 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 2741625 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 19302 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 19302 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 743607 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 2286693 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 110010 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 316910 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 86864 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42906 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 113874 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 31 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 299874 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 296474 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2037394 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 616815 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 3112 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 13 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6118205 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2712873 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14034 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 176949 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 9022061 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 260962176 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104517534 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22892 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 335140 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 365837742 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 939630 # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic 19388808 # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples 3896038 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.075284 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.267877 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 3606903 92.58% 92.58% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 284962 7.31% 99.89% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 4173 0.11% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 3896038 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 5733869996 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 115563972 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 3061282943 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1285797933 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 8314992 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 93182962 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 18647514 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 5782822 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 870887 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 9511803 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 3428026 # Number of BTB hits
-system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 36.039708 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 8548256 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 712976 # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups 3551521 # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits 3498978 # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses 52543 # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted 17984 # Number of mispredicted indirect branches.
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks 22971 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 22971 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19558 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3413 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 22971 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 22971 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 22971 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 1848 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 12803.300866 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 11525.814953 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 15800.491207 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 1844 99.78% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 3 0.16% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.05% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 1848 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples -1978443032 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 -1978443032 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total -1978443032 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 1308 70.78% 70.78% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 540 29.22% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 1848 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22971 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22971 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1848 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1848 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 24819 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.inst_hits 0 # ITB inst hits
-system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 10530339 # DTB read hits
-system.cpu1.dtb.read_misses 20830 # DTB read misses
-system.cpu1.dtb.write_hits 6472980 # DTB write hits
-system.cpu1.dtb.write_misses 2141 # DTB write misses
-system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1623 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 116 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 184 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 10551169 # DTB read accesses
-system.cpu1.dtb.write_accesses 6475121 # DTB write accesses
-system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 17003319 # DTB hits
-system.cpu1.dtb.misses 22971 # DTB misses
-system.cpu1.dtb.accesses 17026290 # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks 2051 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 2051 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1 145 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1906 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 2051 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 2051 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 2051 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 830 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12046.987952 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11480.071390 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 4509.628818 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191 126 15.18% 15.18% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287 555 66.87% 82.05% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383 85 10.24% 92.29% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479 14 1.69% 93.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575 22 2.65% 96.63% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671 18 2.17% 98.80% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767 6 0.72% 99.52% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 99.64% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.36% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 830 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples -1979056532 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 -1979056532 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total -1979056532 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 695 83.73% 83.73% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 135 16.27% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 830 # Table walker page sizes translated
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2051 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2051 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 830 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 830 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 2881 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 38623354 # ITB inst hits
-system.cpu1.itb.inst_misses 2051 # ITB inst misses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 830 # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1040 # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 38625405 # ITB inst accesses
-system.cpu1.itb.hits 38623354 # DTB hits
-system.cpu1.itb.misses 2051 # DTB misses
-system.cpu1.itb.accesses 38625405 # DTB accesses
-system.cpu1.numPwrStateTransitions 5477 # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples 2739 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean 1019571073.706097 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev 25827442882.959442 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows 1941 70.87% 70.87% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.99% 99.85% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 949980394548 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total 2739 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON 55993511619 # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 2792605170881 # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles 111990488 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 45059059 # Number of instructions committed
-system.cpu1.committedOps 55122963 # Number of ops (including micro ops) committed
-system.cpu1.discardedOps 4849343 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 2739 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 5584538446 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 2.485416 # CPI: cycles per instruction
-system.cpu1.ipc 0.402347 # IPC: instructions per cycle
-system.cpu1.op_class_0::No_OpClass 24 0.00% 0.00% # Class of committed instruction
-system.cpu1.op_class_0::IntAlu 38107074 69.13% 69.13% # Class of committed instruction
-system.cpu1.op_class_0::IntMult 43629 0.08% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::IntDiv 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::FloatAdd 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::FloatCmp 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::FloatCvt 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::FloatMult 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::FloatMultAcc 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::FloatDiv 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::FloatMisc 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdAdd 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdAlu 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdCmp 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdCvt 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdMisc 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdMult 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdShift 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMisc 3226 0.01% 69.22% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.22% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.22% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.22% # Class of committed instruction
-system.cpu1.op_class_0::MemRead 10387367 18.84% 88.06% # Class of committed instruction
-system.cpu1.op_class_0::MemWrite 6581643 11.94% 100.00% # Class of committed instruction
-system.cpu1.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.op_class_0::total 55122963 # Class of committed instruction
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed
-system.cpu1.tickCycles 90184958 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 21805530 # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements 157661 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 475.726390 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 16648746 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 158020 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 105.358474 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 91198641000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.726390 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.929153 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.929153 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 284 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 34039754 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 34039754 # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data 10204486 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 10204486 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 6223411 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 6223411 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 43300 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 43300 # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 71256 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 71256 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 62645 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 62645 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 16427897 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 16427897 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 16471197 # number of overall hits
-system.cpu1.dcache.overall_hits::total 16471197 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 127390 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 127390 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 122263 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 122263 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24165 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 24165 # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16525 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 16525 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23356 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 23356 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 249653 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 249653 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 273818 # number of overall misses
-system.cpu1.dcache.overall_misses::total 273818 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2191208500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 2191208500 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3801376500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 3801376500 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322530000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 322530000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 548226000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 548226000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 650000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 650000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 5992585000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 5992585000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 5992585000 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 5992585000 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 10331876 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 10331876 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 6345674 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 6345674 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67465 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 67465 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87781 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 87781 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 86001 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 86001 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 16677550 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 16677550 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 16745015 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 16745015 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.012330 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.012330 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.019267 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.019267 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.358186 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.358186 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188253 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188253 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.271578 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.271578 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014969 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.014969 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.016352 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.016352 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17200.788916 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 17200.788916 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31091.798009 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 31091.798009 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19517.700454 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19517.700454 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23472.598048 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23472.598048 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24003.657076 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 24003.657076 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21885.285116 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 21885.285116 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks 157661 # number of writebacks
-system.cpu1.dcache.writebacks::total 157661 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 4447 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 4447 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42267 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 42267 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11747 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11747 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 46714 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 46714 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 46714 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 46714 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 122943 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 122943 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79996 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 79996 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23657 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 23657 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4778 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4778 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23356 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 23356 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 202939 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 202939 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 226596 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 226596 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14406 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14406 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11728 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11728 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26134 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26134 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1987288500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1987288500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2305734500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2305734500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 418963500 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 418963500 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86008500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86008500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 524885000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 524885000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 635000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 635000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4293023000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 4293023000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4711986500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 4711986500 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2490253500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2490253500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2490253500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2490253500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.011899 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.011899 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012606 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012606 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.350656 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.350656 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054431 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054431 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.271578 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.271578 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.012168 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.012168 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.013532 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.013532 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16164.307850 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16164.307850 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28823.122406 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28823.122406 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17709.916727 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17709.916727 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18000.941817 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18000.941817 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22473.240281 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22473.240281 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21154.253249 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21154.253249 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20794.658776 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20794.658776 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172862.244898 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172862.244898 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95287.881687 # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95287.881687 # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements 872875 # number of replacements
-system.cpu1.icache.tags.tagsinuse 499.208474 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 37748872 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 873387 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 43.221243 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 72896771000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.208474 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975017 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.975017 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 78117905 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 78117905 # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst 37748872 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 37748872 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 37748872 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 37748872 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 37748872 # number of overall hits
-system.cpu1.icache.overall_hits::total 37748872 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 873387 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 873387 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 873387 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 873387 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 873387 # number of overall misses
-system.cpu1.icache.overall_misses::total 873387 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8011666500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 8011666500 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 8011666500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 8011666500 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 8011666500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 8011666500 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 38622259 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 38622259 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 38622259 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 38622259 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 38622259 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 38622259 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022614 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.022614 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022614 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.022614 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022614 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.022614 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9173.100241 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 9173.100241 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9173.100241 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 9173.100241 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9173.100241 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 9173.100241 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks 872875 # number of writebacks
-system.cpu1.icache.writebacks::total 872875 # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 873387 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 873387 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 873387 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 873387 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 873387 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 873387 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
-system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable
-system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
-system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7574973000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 7574973000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7574973000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 7574973000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7574973000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 7574973000 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11042500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 11042500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 11042500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 11042500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022614 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022614 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022614 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.022614 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022614 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.022614 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8673.100241 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8673.100241 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8673.100241 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 8673.100241 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8673.100241 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 8673.100241 # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000 # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 98593.750000 # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000 # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 98593.750000 # average overall mshr uncacheable latency
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued 118852 # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified 118852 # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
-system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage 49172 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements 37377 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 14753.834184 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 946442 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 52088 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 18.170058 # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14422.597482 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 42.225036 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.137350 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 287.874316 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks 0.880285 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002577 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000069 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.017570 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total 0.900503 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022 261 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14372 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 24 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 234 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 53 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1285 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2929 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10158 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.015930 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.877197 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses 35693220 # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses 35693220 # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 23446 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2580 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total 26026 # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks 95283 # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total 95283 # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks 916386 # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total 916386 # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18220 # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total 18220 # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 844850 # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total 844850 # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 81639 # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total 81639 # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 23446 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2580 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst 844850 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data 99859 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total 970735 # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 23446 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2580 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst 844850 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data 99859 # number of overall hits
-system.cpu1.l2cache.overall_hits::total 970735 # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 823 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 297 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total 1120 # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29230 # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total 29230 # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23356 # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total 23356 # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32546 # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total 32546 # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 28537 # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total 28537 # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69739 # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total 69739 # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 823 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker 297 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst 28537 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data 102285 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total 131942 # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 823 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker 297 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst 28537 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data 102285 # number of overall misses
-system.cpu1.l2cache.overall_misses::total 131942 # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 21253500 # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5882500 # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total 27136000 # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 7496000 # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total 7496000 # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 16835000 # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 16835000 # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 611000 # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 611000 # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1439672500 # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total 1439672500 # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1146878000 # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1146878000 # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1720708495 # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1720708495 # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 21253500 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5882500 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1146878000 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data 3160380995 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total 4334394995 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 21253500 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5882500 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1146878000 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data 3160380995 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total 4334394995 # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 24269 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2877 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total 27146 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks 95283 # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total 95283 # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks 916386 # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total 916386 # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29230 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total 29230 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23356 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total 23356 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50766 # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total 50766 # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 873387 # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total 873387 # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 151378 # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total 151378 # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 24269 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2877 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst 873387 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data 202144 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total 1102677 # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 24269 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2877 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst 873387 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data 202144 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total 1102677 # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.033912 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.103233 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total 0.041258 # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.641098 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total 0.641098 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.032674 # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.032674 # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.460694 # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.460694 # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.033912 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.103233 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.032674 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.506001 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total 0.119656 # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.033912 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.103233 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.032674 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.506001 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total 0.119656 # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25824.422843 # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19806.397306 # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24228.571429 # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 256.448854 # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 256.448854 # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 720.799794 # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 720.799794 # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44235.005838 # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44235.005838 # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40189.157935 # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40189.157935 # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 24673.547011 # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 24673.547011 # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25824.422843 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19806.397306 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40189.157935 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30897.795327 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 32850.760145 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25824.422843 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19806.397306 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40189.157935 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30897.795327 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 32850.760145 # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches 596 # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks 29159 # number of writebacks
-system.cpu1.l2cache.writebacks::total 29159 # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 174 # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total 174 # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 5 # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 44 # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 44 # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data 218 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data 218 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total 229 # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 820 # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 294 # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total 1114 # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 19637 # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total 19637 # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29230 # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29230 # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23356 # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23356 # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32372 # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total 32372 # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 28532 # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 28532 # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69695 # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69695 # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 820 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 294 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 28532 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102067 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total 131713 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 820 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 294 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 28532 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102067 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 19637 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total 151350 # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14406 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14518 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11728 # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11728 # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26134 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26246 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 16302000 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4074000 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 20376000 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 732946008 # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 732946008 # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 445433500 # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 445433500 # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 348598000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 348598000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 521000 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 521000 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1224744500 # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1224744500 # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 975419000 # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 975419000 # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1300674995 # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1300674995 # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 16302000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4074000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 975419000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2525419495 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total 3521214495 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 16302000 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4074000 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 975419000 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2525419495 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 732946008 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total 4254160503 # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10146500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2374983500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2385130000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10146500 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2374983500 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2385130000 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.033788 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.102190 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041037 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.637671 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.637671 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.032668 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.032668 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.460404 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.460404 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.033788 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.102190 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.032668 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.504922 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119448 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.033788 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.102190 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.032668 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.504922 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.137257 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18290.843806 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37324.744513 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37324.744513 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15238.915498 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15238.915498 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14925.415311 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14925.415311 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37833.451748 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37833.451748 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34186.842843 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34186.842843 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18662.386039 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18662.386039 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34186.842843 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24742.762058 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26733.993569 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34186.842843 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24742.762058 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37324.744513 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28108.097146 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164860.717756 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164287.780686 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90877.152369 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90875.943001 # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests 2165902 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1090398 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 115909 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 108045 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7864 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq 44859 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 1106447 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 11728 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 11728 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 126621 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 935252 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 26571 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 23763 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 71775 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41777 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 84685 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 31 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 58060 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 55427 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 873387 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263309 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 71 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2619873 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 793002 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6834 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50653 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 3470362 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 111767936 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25786238 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11508 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 97076 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 137662758 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 338759 # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic 4674348 # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples 1446654 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.103615 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.322104 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 1304623 90.18% 90.18% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 134167 9.27% 99.46% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 7864 0.54% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1446654 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 2144021494 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 78336814 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 1310300396 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 351676729 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 3959994 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 26397473 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 31009 # Transaction distribution
-system.iobus.trans_dist::ReadResp 31009 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59424 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59424 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2483988 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 48425501 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 110500 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 324500 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 12500 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 621000 # Layer occupancy (ticks)
-system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6370500 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 39055001 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 187730317 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 36449 # number of replacements
-system.iocache.tags.tagsinuse 14.472713 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 271902155000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 14.472713 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.904545 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.904545 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 328203 # Number of tag accesses
-system.iocache.tags.data_accesses 328203 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
-system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses
-system.iocache.demand_misses::total 36467 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide 36467 # number of overall misses
-system.iocache.overall_misses::total 36467 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 32482877 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 32482877 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 4347292440 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 4347292440 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 4379775317 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 4379775317 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 4379775317 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 4379775317 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 133674.390947 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 133674.390947 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120011.385822 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 120011.385822 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 120102.430060 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 120102.430060 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 120102.430060 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 120102.430060 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 3.500000 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 36206 # number of writebacks
-system.iocache.writebacks::total 36206 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 20332877 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 20332877 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2534226880 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 2534226880 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 2554559757 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 2554559757 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 2554559757 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 2554559757 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 83674.390947 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 83674.390947 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69959.885159 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69959.885159 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 70051.272575 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70051.272575 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 70051.272575 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70051.272575 # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements 143599 # number of replacements
-system.l2c.tags.tagsinuse 65154.346859 # Cycle average of tags in use
-system.l2c.tags.total_refs 605481 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 209069 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 2.896082 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 94462980000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 6720.710891 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 87.363500 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.029896 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 8711.779777 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 6725.180439 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34970.113845 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.660518 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 2224.966255 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 3446.409233 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2253.132505 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.102550 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001333 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.132931 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.102618 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533602 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000224 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.033950 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.052588 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034380 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.994176 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022 32778 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 32633 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3 5072 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4 27569 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 59 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 123 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 1691 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 30817 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022 0.500153 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023 0.000900 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.497940 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 6803015 # Number of tag accesses
-system.l2c.tags.data_accesses 6803015 # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks 266286 # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total 266286 # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data 43645 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 4461 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 48106 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 3017 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 2129 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 5146 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 4448 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 1231 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 5679 # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 477 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker 86 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst 72650 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data 65777 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 48761 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 80 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst 24965 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data 8445 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3652 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 224902 # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 477 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 86 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 72650 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 70225 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher 48761 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 80 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 24965 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 9676 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher 3652 # number of demand (read+write) hits
-system.l2c.demand_hits::total 230581 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 477 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 86 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 72650 # number of overall hits
-system.l2c.overall_hits::cpu0.data 70225 # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher 48761 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 80 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 9 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 24965 # number of overall hits
-system.l2c.overall_hits::cpu1.data 9676 # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher 3652 # number of overall hits
-system.l2c.overall_hits::total 230581 # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data 459 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 178 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 637 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 57 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 62 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 119 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 11423 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 8564 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 19987 # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 145 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst 22738 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data 9967 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134498 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 20 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst 3567 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data 1751 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5084 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total 177771 # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 145 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 22738 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 21390 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher 134498 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker 20 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 3567 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 10315 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher 5084 # number of demand (read+write) misses
-system.l2c.demand_misses::total 197758 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 145 # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 22738 # number of overall misses
-system.l2c.overall_misses::cpu0.data 21390 # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher 134498 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 20 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 3567 # number of overall misses
-system.l2c.overall_misses::cpu1.data 10315 # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher 5084 # number of overall misses
-system.l2c.overall_misses::total 197758 # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data 8555500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 760000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 9315500 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 567000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 122000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 689000 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 1593574000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 815318500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 2408892500 # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 22107500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 90000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2317227000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data 1217018500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16177990963 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 4552500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst 377306500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data 262293500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 655902831 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 21034489294 # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker 22107500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker 90000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 2317227000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 2810592500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16177990963 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker 4552500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 377306500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 1077612000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 655902831 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 23443381794 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker 22107500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker 90000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 2317227000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 2810592500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16177990963 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker 4552500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 377306500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 1077612000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 655902831 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 23443381794 # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks 266286 # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total 266286 # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 44104 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 4639 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 48743 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 3074 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 2191 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 5265 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 15871 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 9795 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 25666 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 622 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 87 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst 95388 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data 75744 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 183259 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 100 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 9 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst 28532 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data 10196 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8736 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total 402673 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 622 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 87 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 95388 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 91615 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher 183259 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 100 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 9 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 28532 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 19991 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8736 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 428339 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 622 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 87 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 95388 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 91615 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher 183259 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 100 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 9 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 28532 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 19991 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8736 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 428339 # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.010407 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.038370 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.013069 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018543 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.028298 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.022602 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.719740 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.874324 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.778735 # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.233119 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.011494 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.238374 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.131588 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.733923 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.200000 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.125018 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.171734 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.581960 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total 0.441477 # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.233119 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.011494 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.238374 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.233477 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.733923 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.200000 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.125018 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.515982 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.581960 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.461686 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.233119 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.011494 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.238374 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.233477 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.733923 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.200000 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.125018 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.515982 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.581960 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.461686 # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 18639.433551 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4269.662921 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 14624.018838 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9947.368421 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1967.741935 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 5789.915966 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139505.734045 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 95203.000934 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 120522.964927 # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 152465.517241 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90000 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 101909.886534 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 122104.795826 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 120284.249305 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 227625 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 105776.983459 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 149796.402056 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 129013.145358 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 118323.513363 # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 152465.517241 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 101909.886534 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 131397.498831 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 120284.249305 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 227625 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 105776.983459 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 104470.382937 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 129013.145358 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 118545.807472 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 152465.517241 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 101909.886534 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 131397.498831 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 120284.249305 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 227625 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 105776.983459 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 104470.382937 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 129013.145358 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 118545.807472 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks 104081 # number of writebacks
-system.l2c.writebacks::total 104081 # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 1 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 6 # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks 4309 # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total 4309 # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data 459 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 178 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 637 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 57 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 62 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 119 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 11423 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 8564 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 19987 # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 145 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22733 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9967 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134498 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 20 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3566 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1751 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5084 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total 177765 # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker 145 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 22733 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 21390 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134498 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker 20 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 3566 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 10315 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5084 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 197752 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker 145 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 22733 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 21390 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134498 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker 20 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 3566 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 10315 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5084 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 197752 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20603 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14403 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total 38395 # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19302 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11728 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total 31030 # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39905 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26131 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total 69425 # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 10236500 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3909500 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 14146000 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1509500 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1453000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 2962500 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1479344000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 729678500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 2209022500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 20657500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2089156001 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1117348500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14833007471 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 4352500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 341582500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 244783001 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 605061833 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total 19256029306 # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 20657500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 2089156001 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 2596692500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14833007471 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 4352500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 341582500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 974461501 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 605061833 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 21465051806 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 20657500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 2089156001 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 2596692500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14833007471 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 4352500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 341582500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 974461501 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 605061833 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 21465051806 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 228848500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4075847000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7794500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2115657500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 6428147500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 228848500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4075847000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7794500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2115657500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 6428147500 # number of overall MSHR uncacheable cycles
-system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
-system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.010407 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.038370 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.013069 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018543 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.028298 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.022602 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.719740 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.874324 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.778735 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.233119 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.238321 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.131588 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733923 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.200000 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.124982 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.171734 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581960 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.441462 # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.233119 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.238321 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.233477 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733923 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200000 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.124982 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.515982 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581960 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.461672 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.233119 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.238321 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.233477 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733923 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200000 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.124982 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.515982 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581960 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.461672 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22301.742919 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21963.483146 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22207.221350 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26482.456140 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23435.483871 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24894.957983 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129505.734045 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 85203.000934 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 110522.964927 # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 91899.705318 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 112104.795826 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 217625 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 95788.698822 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 139796.117076 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108322.950558 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 91899.705318 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121397.498831 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 217625 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 95788.698822 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94470.334561 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 108545.308295 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 91899.705318 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121397.498831 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 217625 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 95788.698822 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94470.334561 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 108545.308295 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197827.840606 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146890.057627 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167421.474150 # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102138.754542 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80963.510773 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 92591.249550 # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests 513996 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 285885 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 629 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 38395 # Transaction distribution
-system.membus.trans_dist::ReadResp 216403 # Transaction distribution
-system.membus.trans_dist::WriteReq 31030 # Transaction distribution
-system.membus.trans_dist::WriteResp 31030 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 140287 # Transaction distribution
-system.membus.trans_dist::CleanEvict 19048 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 61128 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 38691 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::ReadExReq 40497 # Transaction distribution
-system.membus.trans_dist::ReadExResp 19965 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 178008 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 4238 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14192 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 655043 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 777209 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 850140 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28384 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19529832 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 19722372 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 22040516 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 124379 # Total snoops (count)
-system.membus.snoopTraffic 36224 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 423974 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.011487 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.106558 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 419104 98.85% 98.85% # Request fanout histogram
-system.membus.snoop_fanout::1 4870 1.15% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 423974 # Request fanout histogram
-system.membus.reqLayer0.occupancy 95170998 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 12519499 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1006886251 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1152568025 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 6725047 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests 1101165 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 567136 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 209084 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 30878 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 29463 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 1415 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq 38398 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 558656 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 31030 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 31030 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 370367 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 149733 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 109212 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 43837 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 153049 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 31 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 51538 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 51538 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 520262 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 4298 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 3081 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1372035 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 353597 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1725632 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 39251474 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5647218 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 44898692 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 393768 # Total snoops (count)
-system.toL2Bus.snoopTraffic 15844428 # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples 942231 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.393753 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.491645 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 572640 60.77% 60.77% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 368176 39.07% 99.85% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 1415 0.15% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 942231 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 939495440 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 1962409 # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 733983819 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 257943151 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+sim_seconds 2.848624
+sim_ticks 2848623849000
+final_tick 2848623849000
+sim_freq 1000000000000
+host_inst_rate 254983
+host_op_rate 308756
+host_tick_rate 5710154970
+host_mem_usage 634664
+host_seconds 498.87
+sim_insts 127203067
+sim_ops 154028798
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.physmem.bytes_read::cpu0.dtb.walker 9536
+system.physmem.bytes_read::cpu0.itb.walker 64
+system.physmem.bytes_read::cpu0.inst 1667584
+system.physmem.bytes_read::cpu0.data 1358648
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 8591232
+system.physmem.bytes_read::cpu1.dtb.walker 1280
+system.physmem.bytes_read::cpu1.inst 234816
+system.physmem.bytes_read::cpu1.data 662164
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 335296
+system.physmem.bytes_read::realview.ide 960
+system.physmem.bytes_read::total 12861580
+system.physmem.bytes_inst_read::cpu0.inst 1667584
+system.physmem.bytes_inst_read::cpu1.inst 234816
+system.physmem.bytes_inst_read::total 1902400
+system.physmem.bytes_written::writebacks 8982016
+system.physmem.bytes_written::cpu0.data 17524
+system.physmem.bytes_written::cpu1.data 40
+system.physmem.bytes_written::total 8999580
+system.physmem.num_reads::cpu0.dtb.walker 149
+system.physmem.num_reads::cpu0.itb.walker 1
+system.physmem.num_reads::cpu0.inst 26056
+system.physmem.num_reads::cpu0.data 21753
+system.physmem.num_reads::cpu0.l2cache.prefetcher 134238
+system.physmem.num_reads::cpu1.dtb.walker 20
+system.physmem.num_reads::cpu1.inst 3669
+system.physmem.num_reads::cpu1.data 10367
+system.physmem.num_reads::cpu1.l2cache.prefetcher 5239
+system.physmem.num_reads::realview.ide 15
+system.physmem.num_reads::total 201507
+system.physmem.num_writes::writebacks 140344
+system.physmem.num_writes::cpu0.data 4381
+system.physmem.num_writes::cpu1.data 10
+system.physmem.num_writes::total 144735
+system.physmem.bw_read::cpu0.dtb.walker 3348
+system.physmem.bw_read::cpu0.itb.walker 22
+system.physmem.bw_read::cpu0.inst 585400
+system.physmem.bw_read::cpu0.data 476949
+system.physmem.bw_read::cpu0.l2cache.prefetcher 3015924
+system.physmem.bw_read::cpu1.dtb.walker 449
+system.physmem.bw_read::cpu1.inst 82431
+system.physmem.bw_read::cpu1.data 232450
+system.physmem.bw_read::cpu1.l2cache.prefetcher 117705
+system.physmem.bw_read::realview.ide 337
+system.physmem.bw_read::total 4515015
+system.physmem.bw_inst_read::cpu0.inst 585400
+system.physmem.bw_inst_read::cpu1.inst 82431
+system.physmem.bw_inst_read::total 667831
+system.physmem.bw_write::writebacks 3153107
+system.physmem.bw_write::cpu0.data 6152
+system.physmem.bw_write::cpu1.data 14
+system.physmem.bw_write::total 3159273
+system.physmem.bw_total::writebacks 3153107
+system.physmem.bw_total::cpu0.dtb.walker 3348
+system.physmem.bw_total::cpu0.itb.walker 22
+system.physmem.bw_total::cpu0.inst 585400
+system.physmem.bw_total::cpu0.data 483101
+system.physmem.bw_total::cpu0.l2cache.prefetcher 3015924
+system.physmem.bw_total::cpu1.dtb.walker 449
+system.physmem.bw_total::cpu1.inst 82431
+system.physmem.bw_total::cpu1.data 232465
+system.physmem.bw_total::cpu1.l2cache.prefetcher 117705
+system.physmem.bw_total::realview.ide 337
+system.physmem.bw_total::total 7674288
+system.physmem.readReqs 201507
+system.physmem.writeReqs 144735
+system.physmem.readBursts 201507
+system.physmem.writeBursts 144735
+system.physmem.bytesReadDRAM 12886784
+system.physmem.bytesReadWrQ 9664
+system.physmem.bytesWritten 9012160
+system.physmem.bytesReadSys 12861580
+system.physmem.bytesWrittenSys 8999580
+system.physmem.servicedByWrQ 151
+system.physmem.mergedWrBursts 3896
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 12371
+system.physmem.perBankRdBursts::1 12729
+system.physmem.perBankRdBursts::2 13637
+system.physmem.perBankRdBursts::3 13176
+system.physmem.perBankRdBursts::4 15206
+system.physmem.perBankRdBursts::5 12912
+system.physmem.perBankRdBursts::6 12737
+system.physmem.perBankRdBursts::7 12939
+system.physmem.perBankRdBursts::8 12121
+system.physmem.perBankRdBursts::9 12358
+system.physmem.perBankRdBursts::10 11582
+system.physmem.perBankRdBursts::11 10807
+system.physmem.perBankRdBursts::12 12020
+system.physmem.perBankRdBursts::13 12909
+system.physmem.perBankRdBursts::14 12059
+system.physmem.perBankRdBursts::15 11793
+system.physmem.perBankWrBursts::0 8805
+system.physmem.perBankWrBursts::1 9304
+system.physmem.perBankWrBursts::2 9936
+system.physmem.perBankWrBursts::3 9418
+system.physmem.perBankWrBursts::4 8548
+system.physmem.perBankWrBursts::5 9131
+system.physmem.perBankWrBursts::6 8974
+system.physmem.perBankWrBursts::7 9071
+system.physmem.perBankWrBursts::8 8560
+system.physmem.perBankWrBursts::9 8780
+system.physmem.perBankWrBursts::10 8271
+system.physmem.perBankWrBursts::11 7900
+system.physmem.perBankWrBursts::12 8752
+system.physmem.perBankWrBursts::13 8928
+system.physmem.perBankWrBursts::14 8529
+system.physmem.perBankWrBursts::15 7908
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 81
+system.physmem.totGap 2848623293000
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 555
+system.physmem.readPktSize::3 28
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 200924
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 4391
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 140344
+system.physmem.rdQLenPdf::0 85231
+system.physmem.rdQLenPdf::1 63458
+system.physmem.rdQLenPdf::2 11762
+system.physmem.rdQLenPdf::3 9672
+system.physmem.rdQLenPdf::4 8125
+system.physmem.rdQLenPdf::5 6741
+system.physmem.rdQLenPdf::6 5582
+system.physmem.rdQLenPdf::7 4883
+system.physmem.rdQLenPdf::8 4010
+system.physmem.rdQLenPdf::9 1041
+system.physmem.rdQLenPdf::10 301
+system.physmem.rdQLenPdf::11 244
+system.physmem.rdQLenPdf::12 163
+system.physmem.rdQLenPdf::13 133
+system.physmem.rdQLenPdf::14 4
+system.physmem.rdQLenPdf::15 2
+system.physmem.rdQLenPdf::16 1
+system.physmem.rdQLenPdf::17 1
+system.physmem.rdQLenPdf::18 1
+system.physmem.rdQLenPdf::19 1
+system.physmem.rdQLenPdf::20 0
+system.physmem.rdQLenPdf::21 0
+system.physmem.rdQLenPdf::22 0
+system.physmem.rdQLenPdf::23 0
+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
+system.physmem.rdQLenPdf::26 0
+system.physmem.rdQLenPdf::27 0
+system.physmem.rdQLenPdf::28 0
+system.physmem.rdQLenPdf::29 0
+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 1
+system.physmem.wrQLenPdf::1 1
+system.physmem.wrQLenPdf::2 1
+system.physmem.wrQLenPdf::3 1
+system.physmem.wrQLenPdf::4 1
+system.physmem.wrQLenPdf::5 1
+system.physmem.wrQLenPdf::6 1
+system.physmem.wrQLenPdf::7 1
+system.physmem.wrQLenPdf::8 1
+system.physmem.wrQLenPdf::9 1
+system.physmem.wrQLenPdf::10 1
+system.physmem.wrQLenPdf::11 1
+system.physmem.wrQLenPdf::12 1
+system.physmem.wrQLenPdf::13 1
+system.physmem.wrQLenPdf::14 1
+system.physmem.wrQLenPdf::15 2579
+system.physmem.wrQLenPdf::16 3466
+system.physmem.wrQLenPdf::17 4465
+system.physmem.wrQLenPdf::18 5100
+system.physmem.wrQLenPdf::19 6081
+system.physmem.wrQLenPdf::20 6495
+system.physmem.wrQLenPdf::21 7105
+system.physmem.wrQLenPdf::22 7482
+system.physmem.wrQLenPdf::23 8550
+system.physmem.wrQLenPdf::24 8454
+system.physmem.wrQLenPdf::25 9694
+system.physmem.wrQLenPdf::26 10241
+system.physmem.wrQLenPdf::27 8890
+system.physmem.wrQLenPdf::28 8481
+system.physmem.wrQLenPdf::29 8847
+system.physmem.wrQLenPdf::30 9999
+system.physmem.wrQLenPdf::31 8358
+system.physmem.wrQLenPdf::32 8021
+system.physmem.wrQLenPdf::33 878
+system.physmem.wrQLenPdf::34 529
+system.physmem.wrQLenPdf::35 472
+system.physmem.wrQLenPdf::36 388
+system.physmem.wrQLenPdf::37 315
+system.physmem.wrQLenPdf::38 296
+system.physmem.wrQLenPdf::39 291
+system.physmem.wrQLenPdf::40 294
+system.physmem.wrQLenPdf::41 261
+system.physmem.wrQLenPdf::42 323
+system.physmem.wrQLenPdf::43 287
+system.physmem.wrQLenPdf::44 247
+system.physmem.wrQLenPdf::45 264
+system.physmem.wrQLenPdf::46 292
+system.physmem.wrQLenPdf::47 229
+system.physmem.wrQLenPdf::48 187
+system.physmem.wrQLenPdf::49 201
+system.physmem.wrQLenPdf::50 190
+system.physmem.wrQLenPdf::51 167
+system.physmem.wrQLenPdf::52 232
+system.physmem.wrQLenPdf::53 203
+system.physmem.wrQLenPdf::54 172
+system.physmem.wrQLenPdf::55 242
+system.physmem.wrQLenPdf::56 262
+system.physmem.wrQLenPdf::57 203
+system.physmem.wrQLenPdf::58 150
+system.physmem.wrQLenPdf::59 219
+system.physmem.wrQLenPdf::60 213
+system.physmem.wrQLenPdf::61 193
+system.physmem.wrQLenPdf::62 95
+system.physmem.wrQLenPdf::63 221
+system.physmem.bytesPerActivate::samples 88702
+system.physmem.bytesPerActivate::mean 246.880025
+system.physmem.bytesPerActivate::gmean 141.304455
+system.physmem.bytesPerActivate::stdev 302.553851
+system.physmem.bytesPerActivate::0-127 44832 50.54% 50.54%
+system.physmem.bytesPerActivate::128-255 18757 21.15% 71.69%
+system.physmem.bytesPerActivate::256-383 6580 7.42% 79.11%
+system.physmem.bytesPerActivate::384-511 3817 4.30% 83.41%
+system.physmem.bytesPerActivate::512-639 2913 3.28% 86.69%
+system.physmem.bytesPerActivate::640-767 1571 1.77% 88.46%
+system.physmem.bytesPerActivate::768-895 958 1.08% 89.54%
+system.physmem.bytesPerActivate::896-1023 1010 1.14% 90.68%
+system.physmem.bytesPerActivate::1024-1151 8264 9.32% 100.00%
+system.physmem.bytesPerActivate::total 88702
+system.physmem.rdPerTurnAround::samples 6978
+system.physmem.rdPerTurnAround::mean 28.854256
+system.physmem.rdPerTurnAround::stdev 558.300170
+system.physmem.rdPerTurnAround::0-2047 6976 99.97% 99.97%
+system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99%
+system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00%
+system.physmem.rdPerTurnAround::total 6978
+system.physmem.wrPerTurnAround::samples 6978
+system.physmem.wrPerTurnAround::mean 20.179851
+system.physmem.wrPerTurnAround::gmean 18.509497
+system.physmem.wrPerTurnAround::stdev 14.198077
+system.physmem.wrPerTurnAround::16-19 5875 84.19% 84.19%
+system.physmem.wrPerTurnAround::20-23 429 6.15% 90.34%
+system.physmem.wrPerTurnAround::24-27 69 0.99% 91.33%
+system.physmem.wrPerTurnAround::28-31 52 0.75% 92.08%
+system.physmem.wrPerTurnAround::32-35 247 3.54% 95.61%
+system.physmem.wrPerTurnAround::36-39 18 0.26% 95.87%
+system.physmem.wrPerTurnAround::40-43 20 0.29% 96.16%
+system.physmem.wrPerTurnAround::44-47 11 0.16% 96.32%
+system.physmem.wrPerTurnAround::48-51 9 0.13% 96.45%
+system.physmem.wrPerTurnAround::52-55 5 0.07% 96.52%
+system.physmem.wrPerTurnAround::56-59 7 0.10% 96.62%
+system.physmem.wrPerTurnAround::60-63 12 0.17% 96.79%
+system.physmem.wrPerTurnAround::64-67 142 2.03% 98.82%
+system.physmem.wrPerTurnAround::68-71 6 0.09% 98.91%
+system.physmem.wrPerTurnAround::72-75 4 0.06% 98.97%
+system.physmem.wrPerTurnAround::76-79 6 0.09% 99.05%
+system.physmem.wrPerTurnAround::80-83 7 0.10% 99.15%
+system.physmem.wrPerTurnAround::84-87 2 0.03% 99.18%
+system.physmem.wrPerTurnAround::88-91 1 0.01% 99.20%
+system.physmem.wrPerTurnAround::96-99 3 0.04% 99.24%
+system.physmem.wrPerTurnAround::100-103 1 0.01% 99.25%
+system.physmem.wrPerTurnAround::104-107 1 0.01% 99.27%
+system.physmem.wrPerTurnAround::108-111 6 0.09% 99.36%
+system.physmem.wrPerTurnAround::112-115 2 0.03% 99.38%
+system.physmem.wrPerTurnAround::116-119 2 0.03% 99.41%
+system.physmem.wrPerTurnAround::120-123 1 0.01% 99.43%
+system.physmem.wrPerTurnAround::124-127 2 0.03% 99.46%
+system.physmem.wrPerTurnAround::128-131 12 0.17% 99.63%
+system.physmem.wrPerTurnAround::132-135 1 0.01% 99.64%
+system.physmem.wrPerTurnAround::136-139 2 0.03% 99.67%
+system.physmem.wrPerTurnAround::140-143 4 0.06% 99.73%
+system.physmem.wrPerTurnAround::144-147 1 0.01% 99.74%
+system.physmem.wrPerTurnAround::148-151 1 0.01% 99.76%
+system.physmem.wrPerTurnAround::152-155 1 0.01% 99.77%
+system.physmem.wrPerTurnAround::156-159 1 0.01% 99.79%
+system.physmem.wrPerTurnAround::160-163 1 0.01% 99.80%
+system.physmem.wrPerTurnAround::172-175 1 0.01% 99.81%
+system.physmem.wrPerTurnAround::176-179 4 0.06% 99.87%
+system.physmem.wrPerTurnAround::180-183 1 0.01% 99.89%
+system.physmem.wrPerTurnAround::188-191 3 0.04% 99.93%
+system.physmem.wrPerTurnAround::192-195 5 0.07% 100.00%
+system.physmem.wrPerTurnAround::total 6978
+system.physmem.totQLat 9469337826
+system.physmem.totMemAccLat 13244762826
+system.physmem.totBusLat 1006780000
+system.physmem.avgQLat 47027.84
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 65777.84
+system.physmem.avgRdBW 4.52
+system.physmem.avgWrBW 3.16
+system.physmem.avgRdBWSys 4.52
+system.physmem.avgWrBWSys 3.16
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 0.06
+system.physmem.busUtilRead 0.04
+system.physmem.busUtilWrite 0.02
+system.physmem.avgRdQLen 1.02
+system.physmem.avgWrQLen 23.84
+system.physmem.readRowHits 166772
+system.physmem.writeRowHits 86694
+system.physmem.readRowHitRate 82.82
+system.physmem.writeRowHitRate 61.56
+system.physmem.avgGap 8227260.97
+system.physmem.pageHitRate 74.07
+system.physmem_0.actEnergy 335508600
+system.physmem_0.preEnergy 178319460
+system.physmem_0.readEnergy 754747980
+system.physmem_0.writeEnergy 382036140
+system.physmem_0.refreshEnergy 5719839840.000001
+system.physmem_0.actBackEnergy 5271880410
+system.physmem_0.preBackEnergy 306187680
+system.physmem_0.actPowerDownEnergy 11707194090
+system.physmem_0.prePowerDownEnergy 8394624000
+system.physmem_0.selfRefreshEnergy 670253357385
+system.physmem_0.totalEnergy 703305764505
+system.physmem_0.averagePower 246.893167
+system.physmem_0.totalIdleTime 2836258686816
+system.physmem_0.memoryStateTime::IDLE 539863955
+system.physmem_0.memoryStateTime::REF 2430282000
+system.physmem_0.memoryStateTime::SREF 2788726076750
+system.physmem_0.memoryStateTime::PRE_PDN 21860979078
+system.physmem_0.memoryStateTime::ACT 9392787729
+system.physmem_0.memoryStateTime::ACT_PDN 25673859488
+system.physmem_1.actEnergy 297845100
+system.physmem_1.preEnergy 158304630
+system.physmem_1.readEnergy 682933860
+system.physmem_1.writeEnergy 353018160
+system.physmem_1.refreshEnergy 5672512560.000001
+system.physmem_1.actBackEnergy 5217863790
+system.physmem_1.preBackEnergy 312588960
+system.physmem_1.actPowerDownEnergy 10775465250
+system.physmem_1.prePowerDownEnergy 8663500800
+system.physmem_1.selfRefreshEnergy 670664327850
+system.physmem_1.totalEnergy 702800898300
+system.physmem_1.averagePower 246.715936
+system.physmem_1.totalIdleTime 2836361418343
+system.physmem_1.memoryStateTime::IDLE 561410191
+system.physmem_1.memoryStateTime::REF 2410880000
+system.physmem_1.memoryStateTime::SREF 2790169885500
+system.physmem_1.memoryStateTime::PRE_PDN 22561142782
+system.physmem_1.memoryStateTime::ACT 9290058466
+system.physmem_1.memoryStateTime::ACT_PDN 23630472061
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.nvmem.bytes_read::cpu0.inst 512
+system.realview.nvmem.bytes_read::cpu1.inst 832
+system.realview.nvmem.bytes_read::total 1344
+system.realview.nvmem.bytes_inst_read::cpu0.inst 512
+system.realview.nvmem.bytes_inst_read::cpu1.inst 832
+system.realview.nvmem.bytes_inst_read::total 1344
+system.realview.nvmem.num_reads::cpu0.inst 8
+system.realview.nvmem.num_reads::cpu1.inst 13
+system.realview.nvmem.num_reads::total 21
+system.realview.nvmem.bw_read::cpu0.inst 180
+system.realview.nvmem.bw_read::cpu1.inst 292
+system.realview.nvmem.bw_read::total 472
+system.realview.nvmem.bw_inst_read::cpu0.inst 180
+system.realview.nvmem.bw_inst_read::cpu1.inst 292
+system.realview.nvmem.bw_inst_read::total 472
+system.realview.nvmem.bw_total::cpu0.inst 180
+system.realview.nvmem.bw_total::cpu1.inst 292
+system.realview.nvmem.bw_total::total 472
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cf0.dma_read_full_pages 0
+system.cf0.dma_read_bytes 1024
+system.cf0.dma_read_txs 1
+system.cf0.dma_write_full_pages 540
+system.cf0.dma_write_bytes 2318336
+system.cf0.dma_write_txs 631
+system.cpu0.branchPred.lookups 21379739
+system.cpu0.branchPred.condPredicted 14048750
+system.cpu0.branchPred.condIncorrect 1066195
+system.cpu0.branchPred.BTBLookups 13664725
+system.cpu0.branchPred.BTBHits 8978756
+system.cpu0.branchPred.BTBCorrect 0
+system.cpu0.branchPred.BTBHitPct 65.707550
+system.cpu0.branchPred.usedRAS 3515588
+system.cpu0.branchPred.RASInCorrect 217948
+system.cpu0.branchPred.indirectLookups 787162
+system.cpu0.branchPred.indirectHits 592512
+system.cpu0.branchPred.indirectMisses 194650
+system.cpu0.branchPredindirectMispredicted 105179
+system.cpu_clk_domain.clock 500
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu0.dtb.walker.walks 69389
+system.cpu0.dtb.walker.walksShort 69389
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46163
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23226
+system.cpu0.dtb.walker.walkWaitTime::samples 69389
+system.cpu0.dtb.walker.walkWaitTime::0 69389 100.00% 100.00%
+system.cpu0.dtb.walker.walkWaitTime::total 69389
+system.cpu0.dtb.walker.walkCompletionTime::samples 7614
+system.cpu0.dtb.walker.walkCompletionTime::mean 12248.161282
+system.cpu0.dtb.walker.walkCompletionTime::gmean 11230.175404
+system.cpu0.dtb.walker.walkCompletionTime::stdev 9547.601051
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 7604 99.87% 99.87%
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.95%
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1 0.01% 99.96%
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 2 0.03% 99.99%
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00%
+system.cpu0.dtb.walker.walkCompletionTime::total 7614
+system.cpu0.dtb.walker.walksPending::samples 338892000
+system.cpu0.dtb.walker.walksPending::0 338892000 100.00% 100.00%
+system.cpu0.dtb.walker.walksPending::total 338892000
+system.cpu0.dtb.walker.walkPageSizes::4K 5921 77.76% 77.76%
+system.cpu0.dtb.walker.walkPageSizes::1M 1693 22.24% 100.00%
+system.cpu0.dtb.walker.walkPageSizes::total 7614
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69389
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69389
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7614
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7614
+system.cpu0.dtb.walker.walkRequestOrigin::total 77003
+system.cpu0.dtb.inst_hits 0
+system.cpu0.dtb.inst_misses 0
+system.cpu0.dtb.read_hits 17963765
+system.cpu0.dtb.read_misses 62780
+system.cpu0.dtb.write_hits 15037845
+system.cpu0.dtb.write_misses 6609
+system.cpu0.dtb.flush_tlb 66
+system.cpu0.dtb.flush_tlb_mva 917
+system.cpu0.dtb.flush_tlb_mva_asid 0
+system.cpu0.dtb.flush_tlb_asid 0
+system.cpu0.dtb.flush_entries 3754
+system.cpu0.dtb.align_faults 1496
+system.cpu0.dtb.prefetch_faults 2044
+system.cpu0.dtb.domain_faults 0
+system.cpu0.dtb.perms_faults 601
+system.cpu0.dtb.read_accesses 18026545
+system.cpu0.dtb.write_accesses 15044454
+system.cpu0.dtb.inst_accesses 0
+system.cpu0.dtb.hits 33001610
+system.cpu0.dtb.misses 69389
+system.cpu0.dtb.accesses 33070999
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu0.istage2_mmu.stage2_tlb.hits 0
+system.cpu0.istage2_mmu.stage2_tlb.misses 0
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu0.itb.walker.walks 4330
+system.cpu0.itb.walker.walksShort 4330
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1 325
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4005
+system.cpu0.itb.walker.walkWaitTime::samples 4330
+system.cpu0.itb.walker.walkWaitTime::0 4330 100.00% 100.00%
+system.cpu0.itb.walker.walkWaitTime::total 4330
+system.cpu0.itb.walker.walkCompletionTime::samples 2695
+system.cpu0.itb.walker.walkCompletionTime::mean 12512.059369
+system.cpu0.itb.walker.walkCompletionTime::gmean 11831.555276
+system.cpu0.itb.walker.walkCompletionTime::stdev 4578.031613
+system.cpu0.itb.walker.walkCompletionTime::0-8191 443 16.44% 16.44%
+system.cpu0.itb.walker.walkCompletionTime::8192-16383 2044 75.84% 92.28%
+system.cpu0.itb.walker.walkCompletionTime::16384-24575 157 5.83% 98.11%
+system.cpu0.itb.walker.walkCompletionTime::24576-32767 32 1.19% 99.29%
+system.cpu0.itb.walker.walkCompletionTime::32768-40959 18 0.67% 99.96%
+system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00%
+system.cpu0.itb.walker.walkCompletionTime::total 2695
+system.cpu0.itb.walker.walksPending::samples 338263500
+system.cpu0.itb.walker.walksPending::0 338263500 100.00% 100.00%
+system.cpu0.itb.walker.walksPending::total 338263500
+system.cpu0.itb.walker.walkPageSizes::4K 2375 88.13% 88.13%
+system.cpu0.itb.walker.walkPageSizes::1M 320 11.87% 100.00%
+system.cpu0.itb.walker.walkPageSizes::total 2695
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4330
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4330
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2695
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2695
+system.cpu0.itb.walker.walkRequestOrigin::total 7025
+system.cpu0.itb.inst_hits 39749039
+system.cpu0.itb.inst_misses 4330
+system.cpu0.itb.read_hits 0
+system.cpu0.itb.read_misses 0
+system.cpu0.itb.write_hits 0
+system.cpu0.itb.write_misses 0
+system.cpu0.itb.flush_tlb 66
+system.cpu0.itb.flush_tlb_mva 917
+system.cpu0.itb.flush_tlb_mva_asid 0
+system.cpu0.itb.flush_tlb_asid 0
+system.cpu0.itb.flush_entries 2403
+system.cpu0.itb.align_faults 0
+system.cpu0.itb.prefetch_faults 0
+system.cpu0.itb.domain_faults 0
+system.cpu0.itb.perms_faults 7919
+system.cpu0.itb.read_accesses 0
+system.cpu0.itb.write_accesses 0
+system.cpu0.itb.inst_accesses 39753369
+system.cpu0.itb.hits 39749039
+system.cpu0.itb.misses 4330
+system.cpu0.itb.accesses 39753369
+system.cpu0.numPwrStateTransitions 3708
+system.cpu0.pwrStateClkGateDist::samples 1854
+system.cpu0.pwrStateClkGateDist::mean 1488624916.645631
+system.cpu0.pwrStateClkGateDist::stdev 23946318823.517799
+system.cpu0.pwrStateClkGateDist::underflows 1085 58.52% 58.52%
+system.cpu0.pwrStateClkGateDist::1000-5e+10 762 41.10% 99.62%
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68%
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73%
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78%
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00%
+system.cpu0.pwrStateClkGateDist::min_value 501
+system.cpu0.pwrStateClkGateDist::max_value 499964387468
+system.cpu0.pwrStateClkGateDist::total 1854
+system.cpu0.pwrStateResidencyTicks::ON 88713253539
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2759910595461
+system.cpu0.numCycles 177429053
+system.cpu0.numWorkItemsStarted 0
+system.cpu0.numWorkItemsCompleted 0
+system.cpu0.committedInsts 82144744
+system.cpu0.committedOps 98906656
+system.cpu0.discardedOps 5353018
+system.cpu0.numFetchSuspends 1854
+system.cpu0.quiesceCycles 5519845971
+system.cpu0.cpi 2.159956
+system.cpu0.ipc 0.462972
+system.cpu0.op_class_0::No_OpClass 2315 0.00% 0.00%
+system.cpu0.op_class_0::IntAlu 65602827 66.33% 66.33%
+system.cpu0.op_class_0::IntMult 94044 0.10% 66.43%
+system.cpu0.op_class_0::IntDiv 0 0.00% 66.43%
+system.cpu0.op_class_0::FloatAdd 0 0.00% 66.43%
+system.cpu0.op_class_0::FloatCmp 0 0.00% 66.43%
+system.cpu0.op_class_0::FloatCvt 0 0.00% 66.43%
+system.cpu0.op_class_0::FloatMult 0 0.00% 66.43%
+system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.43%
+system.cpu0.op_class_0::FloatDiv 0 0.00% 66.43%
+system.cpu0.op_class_0::FloatMisc 0 0.00% 66.43%
+system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdAdd 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdAlu 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdCmp 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdCvt 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdMisc 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdMult 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdShift 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdFloatMisc 8167 0.01% 66.43%
+system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.43%
+system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.43%
+system.cpu0.op_class_0::MemRead 17404847 17.60% 84.03%
+system.cpu0.op_class_0::MemWrite 15783224 15.96% 99.99%
+system.cpu0.op_class_0::FloatMemRead 2708 0.00% 99.99%
+system.cpu0.op_class_0::FloatMemWrite 8524 0.01% 100.00%
+system.cpu0.op_class_0::IprAccess 0 0.00% 100.00%
+system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00%
+system.cpu0.op_class_0::total 98906656
+system.cpu0.kern.inst.arm 0
+system.cpu0.kern.inst.quiesce 1854
+system.cpu0.tickCycles 124456621
+system.cpu0.idleCycles 52972432
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu0.dcache.tags.replacements 756405
+system.cpu0.dcache.tags.tagsinuse 496.635860
+system.cpu0.dcache.tags.total_refs 31498556
+system.cpu0.dcache.tags.sampled_refs 756917
+system.cpu0.dcache.tags.avg_refs 41.614280
+system.cpu0.dcache.tags.warmup_cycle 356904000
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.635860
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969992
+system.cpu0.dcache.tags.occ_percent::total 0.969992
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 343
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 61
+system.cpu0.dcache.tags.occ_task_id_percent::1024 1
+system.cpu0.dcache.tags.tag_accesses 66081221
+system.cpu0.dcache.tags.data_accesses 66081221
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu0.dcache.ReadReq_hits::cpu0.data 16424804
+system.cpu0.dcache.ReadReq_hits::total 16424804
+system.cpu0.dcache.WriteReq_hits::cpu0.data 13888667
+system.cpu0.dcache.WriteReq_hits::total 13888667
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 328295
+system.cpu0.dcache.SoftPFReq_hits::total 328295
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374149
+system.cpu0.dcache.LoadLockedReq_hits::total 374149
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370236
+system.cpu0.dcache.StoreCondReq_hits::total 370236
+system.cpu0.dcache.demand_hits::cpu0.data 30313471
+system.cpu0.dcache.demand_hits::total 30313471
+system.cpu0.dcache.overall_hits::cpu0.data 30641766
+system.cpu0.dcache.overall_hits::total 30641766
+system.cpu0.dcache.ReadReq_misses::cpu0.data 461281
+system.cpu0.dcache.ReadReq_misses::total 461281
+system.cpu0.dcache.WriteReq_misses::cpu0.data 603910
+system.cpu0.dcache.WriteReq_misses::total 603910
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141881
+system.cpu0.dcache.SoftPFReq_misses::total 141881
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21430
+system.cpu0.dcache.LoadLockedReq_misses::total 21430
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20444
+system.cpu0.dcache.StoreCondReq_misses::total 20444
+system.cpu0.dcache.demand_misses::cpu0.data 1065191
+system.cpu0.dcache.demand_misses::total 1065191
+system.cpu0.dcache.overall_misses::cpu0.data 1207072
+system.cpu0.dcache.overall_misses::total 1207072
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6678483000
+system.cpu0.dcache.ReadReq_miss_latency::total 6678483000
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11547811000
+system.cpu0.dcache.WriteReq_miss_latency::total 11547811000
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336788000
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 336788000
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 483606000
+system.cpu0.dcache.StoreCondReq_miss_latency::total 483606000
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 634500
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total 634500
+system.cpu0.dcache.demand_miss_latency::cpu0.data 18226294000
+system.cpu0.dcache.demand_miss_latency::total 18226294000
+system.cpu0.dcache.overall_miss_latency::cpu0.data 18226294000
+system.cpu0.dcache.overall_miss_latency::total 18226294000
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 16886085
+system.cpu0.dcache.ReadReq_accesses::total 16886085
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 14492577
+system.cpu0.dcache.WriteReq_accesses::total 14492577
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470176
+system.cpu0.dcache.SoftPFReq_accesses::total 470176
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 395579
+system.cpu0.dcache.LoadLockedReq_accesses::total 395579
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390680
+system.cpu0.dcache.StoreCondReq_accesses::total 390680
+system.cpu0.dcache.demand_accesses::cpu0.data 31378662
+system.cpu0.dcache.demand_accesses::total 31378662
+system.cpu0.dcache.overall_accesses::cpu0.data 31848838
+system.cpu0.dcache.overall_accesses::total 31848838
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027317
+system.cpu0.dcache.ReadReq_miss_rate::total 0.027317
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041670
+system.cpu0.dcache.WriteReq_miss_rate::total 0.041670
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301761
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301761
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054174
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054174
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052329
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052329
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033946
+system.cpu0.dcache.demand_miss_rate::total 0.033946
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037900
+system.cpu0.dcache.overall_miss_rate::total 0.037900
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14478.122880
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14478.122880
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19121.741650
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 19121.741650
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15715.725618
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15715.725618
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23655.155547
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23655.155547
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17110.822378
+system.cpu0.dcache.demand_avg_miss_latency::total 17110.822378
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15099.591408
+system.cpu0.dcache.overall_avg_miss_latency::total 15099.591408
+system.cpu0.dcache.blocked_cycles::no_mshrs 0
+system.cpu0.dcache.blocked_cycles::no_targets 0
+system.cpu0.dcache.blocked::no_mshrs 0
+system.cpu0.dcache.blocked::no_targets 0
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan
+system.cpu0.dcache.writebacks::writebacks 756405
+system.cpu0.dcache.writebacks::total 756405
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 46004
+system.cpu0.dcache.ReadReq_mshr_hits::total 46004
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266244
+system.cpu0.dcache.WriteReq_mshr_hits::total 266244
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14893
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14893
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 312248
+system.cpu0.dcache.demand_mshr_hits::total 312248
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 312248
+system.cpu0.dcache.overall_mshr_hits::total 312248
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 415277
+system.cpu0.dcache.ReadReq_mshr_misses::total 415277
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337666
+system.cpu0.dcache.WriteReq_mshr_misses::total 337666
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108256
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 108256
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6537
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6537
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20444
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 20444
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 752943
+system.cpu0.dcache.demand_mshr_misses::total 752943
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 861199
+system.cpu0.dcache.overall_mshr_misses::total 861199
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20583
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20583
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19292
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19292
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39875
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39875
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5475832500
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5475832500
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6297373500
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6297373500
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1755672500
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1755672500
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104037500
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104037500
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 463180000
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 463180000
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 616500
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 616500
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11773206000
+system.cpu0.dcache.demand_mshr_miss_latency::total 11773206000
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13528878500
+system.cpu0.dcache.overall_mshr_miss_latency::total 13528878500
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4608535500
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4608535500
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4608535500
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4608535500
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024593
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024593
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023299
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023299
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230246
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230246
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016525
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016525
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052329
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052329
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023995
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.023995
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027040
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.027040
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13185.975867
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13185.975867
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18649.711549
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18649.711549
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16217.784696
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16217.784696
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15915.175157
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15915.175157
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22656.036001
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22656.036001
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15636.251350
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15636.251350
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15709.352310
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15709.352310
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223900.087451
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223900.087451
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115574.557994
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115574.557994
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu0.icache.tags.replacements 2037202
+system.cpu0.icache.tags.tagsinuse 511.775063
+system.cpu0.icache.tags.total_refs 37703101
+system.cpu0.icache.tags.sampled_refs 2037714
+system.cpu0.icache.tags.avg_refs 18.502646
+system.cpu0.icache.tags.warmup_cycle 6575306000
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.775063
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999561
+system.cpu0.icache.tags.occ_percent::total 0.999561
+system.cpu0.icache.tags.occ_task_id_blocks::1024 512
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 146
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 264
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 102
+system.cpu0.icache.tags.occ_task_id_percent::1024 1
+system.cpu0.icache.tags.tag_accesses 81519385
+system.cpu0.icache.tags.data_accesses 81519385
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu0.icache.ReadReq_hits::cpu0.inst 37703101
+system.cpu0.icache.ReadReq_hits::total 37703101
+system.cpu0.icache.demand_hits::cpu0.inst 37703101
+system.cpu0.icache.demand_hits::total 37703101
+system.cpu0.icache.overall_hits::cpu0.inst 37703101
+system.cpu0.icache.overall_hits::total 37703101
+system.cpu0.icache.ReadReq_misses::cpu0.inst 2037728
+system.cpu0.icache.ReadReq_misses::total 2037728
+system.cpu0.icache.demand_misses::cpu0.inst 2037728
+system.cpu0.icache.demand_misses::total 2037728
+system.cpu0.icache.overall_misses::cpu0.inst 2037728
+system.cpu0.icache.overall_misses::total 2037728
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20440936500
+system.cpu0.icache.ReadReq_miss_latency::total 20440936500
+system.cpu0.icache.demand_miss_latency::cpu0.inst 20440936500
+system.cpu0.icache.demand_miss_latency::total 20440936500
+system.cpu0.icache.overall_miss_latency::cpu0.inst 20440936500
+system.cpu0.icache.overall_miss_latency::total 20440936500
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 39740829
+system.cpu0.icache.ReadReq_accesses::total 39740829
+system.cpu0.icache.demand_accesses::cpu0.inst 39740829
+system.cpu0.icache.demand_accesses::total 39740829
+system.cpu0.icache.overall_accesses::cpu0.inst 39740829
+system.cpu0.icache.overall_accesses::total 39740829
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051275
+system.cpu0.icache.ReadReq_miss_rate::total 0.051275
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051275
+system.cpu0.icache.demand_miss_rate::total 0.051275
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051275
+system.cpu0.icache.overall_miss_rate::total 0.051275
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10031.238958
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10031.238958
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10031.238958
+system.cpu0.icache.demand_avg_miss_latency::total 10031.238958
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10031.238958
+system.cpu0.icache.overall_avg_miss_latency::total 10031.238958
+system.cpu0.icache.blocked_cycles::no_mshrs 0
+system.cpu0.icache.blocked_cycles::no_targets 0
+system.cpu0.icache.blocked::no_mshrs 0
+system.cpu0.icache.blocked::no_targets 0
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
+system.cpu0.icache.avg_blocked_cycles::no_targets nan
+system.cpu0.icache.writebacks::writebacks 2037202
+system.cpu0.icache.writebacks::total 2037202
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2037728
+system.cpu0.icache.ReadReq_mshr_misses::total 2037728
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 2037728
+system.cpu0.icache.demand_mshr_misses::total 2037728
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 2037728
+system.cpu0.icache.overall_mshr_misses::total 2037728
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3277
+system.cpu0.icache.ReadReq_mshr_uncacheable::total 3277
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3277
+system.cpu0.icache.overall_mshr_uncacheable_misses::total 3277
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19422073000
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 19422073000
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19422073000
+system.cpu0.icache.demand_mshr_miss_latency::total 19422073000
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19422073000
+system.cpu0.icache.overall_mshr_miss_latency::total 19422073000
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 323882000
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 323882000
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 323882000
+system.cpu0.icache.overall_mshr_uncacheable_latency::total 323882000
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051275
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051275
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051275
+system.cpu0.icache.demand_mshr_miss_rate::total 0.051275
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051275
+system.cpu0.icache.overall_mshr_miss_rate::total 0.051275
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9531.239204
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9531.239204
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9531.239204
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 9531.239204
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9531.239204
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 9531.239204
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98834.909979
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98834.909979
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927472
+system.cpu0.l2cache.prefetcher.pfIdentified 1927591
+system.cpu0.l2cache.prefetcher.pfBufferHit 103
+system.cpu0.l2cache.prefetcher.pfInCache 0
+system.cpu0.l2cache.prefetcher.pfRemovedFull 0
+system.cpu0.l2cache.prefetcher.pfSpanPage 244225
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu0.l2cache.tags.replacements 297417
+system.cpu0.l2cache.tags.tagsinuse 15628.878129
+system.cpu0.l2cache.tags.total_refs 2702548
+system.cpu0.l2cache.tags.sampled_refs 313030
+system.cpu0.l2cache.tags.avg_refs 8.633511
+system.cpu0.l2cache.tags.warmup_cycle 0
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14526.448544
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.513494
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.067121
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1037.848970
+system.cpu0.l2cache.tags.occ_percent::writebacks 0.886624
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003938
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063345
+system.cpu0.l2cache.tags.occ_percent::total 0.953911
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022 248
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15359
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 5
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 30
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 157
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 56
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 240
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1189
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7272
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5800
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 858
+system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.015137
+system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366
+system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.937439
+system.cpu0.l2cache.tags.tag_accesses 95173701
+system.cpu0.l2cache.tags.data_accesses 95173701
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 82675
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5812
+system.cpu0.l2cache.ReadReq_hits::total 88487
+system.cpu0.l2cache.WritebackDirty_hits::writebacks 506400
+system.cpu0.l2cache.WritebackDirty_hits::total 506400
+system.cpu0.l2cache.WritebackClean_hits::writebacks 2243097
+system.cpu0.l2cache.WritebackClean_hits::total 2243097
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data 235078
+system.cpu0.l2cache.ReadExReq_hits::total 235078
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1942100
+system.cpu0.l2cache.ReadCleanReq_hits::total 1942100
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 414660
+system.cpu0.l2cache.ReadSharedReq_hits::total 414660
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 82675
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5812
+system.cpu0.l2cache.demand_hits::cpu0.inst 1942100
+system.cpu0.l2cache.demand_hits::cpu0.data 649738
+system.cpu0.l2cache.demand_hits::total 2680325
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 82675
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5812
+system.cpu0.l2cache.overall_hits::cpu0.inst 1942100
+system.cpu0.l2cache.overall_hits::cpu0.data 649738
+system.cpu0.l2cache.overall_hits::total 2680325
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 788
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 88
+system.cpu0.l2cache.ReadReq_misses::total 876
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56733
+system.cpu0.l2cache.UpgradeReq_misses::total 56733
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20444
+system.cpu0.l2cache.SCUpgradeReq_misses::total 20444
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45864
+system.cpu0.l2cache.ReadExReq_misses::total 45864
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 95628
+system.cpu0.l2cache.ReadCleanReq_misses::total 95628
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 115406
+system.cpu0.l2cache.ReadSharedReq_misses::total 115406
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 788
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker 88
+system.cpu0.l2cache.demand_misses::cpu0.inst 95628
+system.cpu0.l2cache.demand_misses::cpu0.data 161270
+system.cpu0.l2cache.demand_misses::total 257774
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 788
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker 88
+system.cpu0.l2cache.overall_misses::cpu0.inst 95628
+system.cpu0.l2cache.overall_misses::cpu0.data 161270
+system.cpu0.l2cache.overall_misses::total 257774
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 38430500
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2144000
+system.cpu0.l2cache.ReadReq_miss_latency::total 40574500
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 46515500
+system.cpu0.l2cache.UpgradeReq_miss_latency::total 46515500
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 11588000
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 11588000
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 589500
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 589500
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2931053499
+system.cpu0.l2cache.ReadExReq_miss_latency::total 2931053499
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4619846000
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4619846000
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3809640999
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3809640999
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 38430500
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2144000
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4619846000
+system.cpu0.l2cache.demand_miss_latency::cpu0.data 6740694498
+system.cpu0.l2cache.demand_miss_latency::total 11401114998
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 38430500
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2144000
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4619846000
+system.cpu0.l2cache.overall_miss_latency::cpu0.data 6740694498
+system.cpu0.l2cache.overall_miss_latency::total 11401114998
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 83463
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5900
+system.cpu0.l2cache.ReadReq_accesses::total 89363
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks 506400
+system.cpu0.l2cache.WritebackDirty_accesses::total 506400
+system.cpu0.l2cache.WritebackClean_accesses::writebacks 2243097
+system.cpu0.l2cache.WritebackClean_accesses::total 2243097
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56733
+system.cpu0.l2cache.UpgradeReq_accesses::total 56733
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20444
+system.cpu0.l2cache.SCUpgradeReq_accesses::total 20444
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 280942
+system.cpu0.l2cache.ReadExReq_accesses::total 280942
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 2037728
+system.cpu0.l2cache.ReadCleanReq_accesses::total 2037728
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 530066
+system.cpu0.l2cache.ReadSharedReq_accesses::total 530066
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 83463
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5900
+system.cpu0.l2cache.demand_accesses::cpu0.inst 2037728
+system.cpu0.l2cache.demand_accesses::cpu0.data 811008
+system.cpu0.l2cache.demand_accesses::total 2938099
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 83463
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5900
+system.cpu0.l2cache.overall_accesses::cpu0.inst 2037728
+system.cpu0.l2cache.overall_accesses::cpu0.data 811008
+system.cpu0.l2cache.overall_accesses::total 2938099
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009441
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.014915
+system.cpu0.l2cache.ReadReq_miss_rate::total 0.009803
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1
+system.cpu0.l2cache.UpgradeReq_miss_rate::total 1
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.163251
+system.cpu0.l2cache.ReadExReq_miss_rate::total 0.163251
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.046929
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.046929
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.217720
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.217720
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009441
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.014915
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.046929
+system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198851
+system.cpu0.l2cache.demand_miss_rate::total 0.087735
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009441
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.014915
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.046929
+system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198851
+system.cpu0.l2cache.overall_miss_rate::total 0.087735
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 48769.670051
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24363.636364
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 46317.922374
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 819.901997
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 819.901997
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 566.816670
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 566.816670
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63907.498234
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63907.498234
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 48310.599406
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 48310.599406
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33010.770662
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33010.770662
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 48769.670051
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24363.636364
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 48310.599406
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41797.572382
+system.cpu0.l2cache.demand_avg_miss_latency::total 44229.111540
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 48769.670051
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24363.636364
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 48310.599406
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41797.572382
+system.cpu0.l2cache.overall_avg_miss_latency::total 44229.111540
+system.cpu0.l2cache.blocked_cycles::no_mshrs 3
+system.cpu0.l2cache.blocked_cycles::no_targets 0
+system.cpu0.l2cache.blocked::no_mshrs 1
+system.cpu0.l2cache.blocked::no_targets 0
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 3
+system.cpu0.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu0.l2cache.unused_prefetches 10997
+system.cpu0.l2cache.writebacks::writebacks 236911
+system.cpu0.l2cache.writebacks::total 236911
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1
+system.cpu0.l2cache.ReadReq_mshr_hits::total 2
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3224
+system.cpu0.l2cache.ReadExReq_mshr_hits::total 3224
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 63
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 63
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 416
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 416
+system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 63
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3640
+system.cpu0.l2cache.demand_mshr_hits::total 3705
+system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1
+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 63
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3640
+system.cpu0.l2cache.overall_mshr_hits::total 3705
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 787
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 87
+system.cpu0.l2cache.ReadReq_mshr_misses::total 874
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 267712
+system.cpu0.l2cache.HardPFReq_mshr_misses::total 267712
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56733
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56733
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20444
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20444
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42640
+system.cpu0.l2cache.ReadExReq_mshr_misses::total 42640
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 95565
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 95565
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 114990
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 114990
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 787
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 87
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 95565
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data 157630
+system.cpu0.l2cache.demand_mshr_misses::total 254069
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 787
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 87
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 95565
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data 157630
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 267712
+system.cpu0.l2cache.overall_mshr_misses::total 521781
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3277
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20583
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23860
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19292
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19292
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3277
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39875
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 43152
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 33685500
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1610000
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 35295500
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16994507487
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16994507487
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 984458499
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 984458499
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 308957999
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 308957999
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 481500
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 481500
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2181877499
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2181877499
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 4044466000
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 4044466000
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 3095831499
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 3095831499
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 33685500
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1610000
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 4044466000
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5277708998
+system.cpu0.l2cache.demand_mshr_miss_latency::total 9357470498
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 33685500
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1610000
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4044466000
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5277708998
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16994507487
+system.cpu0.l2cache.overall_mshr_miss_latency::total 26351977985
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 297666000
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4443759500
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4741425500
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 297666000
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4443759500
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4741425500
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009429
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014746
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009780
+system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf
+system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.151775
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.151775
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046898
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046898
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.216935
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.216935
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009429
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.014746
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046898
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.194363
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.086474
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009429
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.014746
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046898
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.194363
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177591
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42802.414231
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18505.747126
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40383.867277
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63480.559284
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63480.559284
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17352.484427
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17352.484427
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15112.404569
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15112.404569
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 51169.734967
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 51169.734967
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42321.624026
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42321.624026
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26922.615001
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26922.615001
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42802.414231
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18505.747126
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42321.624026
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33481.627850
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36830.429915
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42802.414231
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18505.747126
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42321.624026
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33481.627850
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63480.559284
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50503.904866
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215894.646067
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198718.587594
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111442.244514
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109877.305803
+system.cpu0.toL2Bus.snoop_filter.tot_requests 5743921
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2895216
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44126
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 221019
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 216830
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4189
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu0.toL2Bus.trans_dist::ReadReq 124852
+system.cpu0.toL2Bus.trans_dist::ReadResp 2741615
+system.cpu0.toL2Bus.trans_dist::WriteReq 19292
+system.cpu0.toL2Bus.trans_dist::WriteResp 19292
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 743621
+system.cpu0.toL2Bus.trans_dist::WritebackClean 2287205
+system.cpu0.toL2Bus.trans_dist::CleanEvict 110575
+system.cpu0.toL2Bus.trans_dist::HardPFReq 317039
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 86991
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42833
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 113881
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 31
+system.cpu0.toL2Bus.trans_dist::ReadExReq 299988
+system.cpu0.toL2Bus.trans_dist::ReadExResp 296595
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2037728
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 617206
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 3167
+system.cpu0.toL2Bus.trans_dist::InvalidateResp 12
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6119211
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2713935
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14235
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 176078
+system.cpu0.toL2Bus.pkt_count::total 9023459
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 261005184
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104563972
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23600
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 333852
+system.cpu0.toL2Bus.pkt_size::total 365926608
+system.cpu0.toL2Bus.snoops 939889
+system.cpu0.toL2Bus.snoopTraffic 19367640
+system.cpu0.toL2Bus.snoop_fanout::samples 3896905
+system.cpu0.toL2Bus.snoop_fanout::mean 0.075382
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.268048
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu0.toL2Bus.snoop_fanout::0 3607336 92.57% 92.57%
+system.cpu0.toL2Bus.snoop_fanout::1 285380 7.32% 99.89%
+system.cpu0.toL2Bus.snoop_fanout::2 4189 0.11% 100.00%
+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu0.toL2Bus.snoop_fanout::min_value 0
+system.cpu0.toL2Bus.snoop_fanout::max_value 2
+system.cpu0.toL2Bus.snoop_fanout::total 3896905
+system.cpu0.toL2Bus.reqLayer0.occupancy 5735062996
+system.cpu0.toL2Bus.reqLayer0.utilization 0.2
+system.cpu0.toL2Bus.snoopLayer0.occupancy 115443960
+system.cpu0.toL2Bus.snoopLayer0.utilization 0.0
+system.cpu0.toL2Bus.respLayer0.occupancy 3061810390
+system.cpu0.toL2Bus.respLayer0.utilization 0.1
+system.cpu0.toL2Bus.respLayer1.occupancy 1286359474
+system.cpu0.toL2Bus.respLayer1.utilization 0.0
+system.cpu0.toL2Bus.respLayer2.occupancy 8343483
+system.cpu0.toL2Bus.respLayer2.utilization 0.0
+system.cpu0.toL2Bus.respLayer3.occupancy 92635958
+system.cpu0.toL2Bus.respLayer3.utilization 0.0
+system.cpu1.branchPred.lookups 18642416
+system.cpu1.branchPred.condPredicted 5780300
+system.cpu1.branchPred.condIncorrect 870028
+system.cpu1.branchPred.BTBLookups 9493986
+system.cpu1.branchPred.BTBHits 3424862
+system.cpu1.branchPred.BTBCorrect 0
+system.cpu1.branchPred.BTBHitPct 36.074016
+system.cpu1.branchPred.usedRAS 8548372
+system.cpu1.branchPred.RASInCorrect 713031
+system.cpu1.branchPred.indirectLookups 3551810
+system.cpu1.branchPred.indirectHits 3499174
+system.cpu1.branchPred.indirectMisses 52636
+system.cpu1.branchPredindirectMispredicted 18015
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu1.dtb.walker.walks 23296
+system.cpu1.dtb.walker.walksShort 23296
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19754
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3542
+system.cpu1.dtb.walker.walkWaitTime::samples 23296
+system.cpu1.dtb.walker.walkWaitTime::0 23296 100.00% 100.00%
+system.cpu1.dtb.walker.walkWaitTime::total 23296
+system.cpu1.dtb.walker.walkCompletionTime::samples 1833
+system.cpu1.dtb.walker.walkCompletionTime::mean 12785.870158
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11578.247782
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15610.872723
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 1830 99.84% 99.84%
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2 0.11% 99.95%
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.05% 100.00%
+system.cpu1.dtb.walker.walkCompletionTime::total 1833
+system.cpu1.dtb.walker.walksPending::samples -1978443032
+system.cpu1.dtb.walker.walksPending::0 -1978443032 100.00% 100.00%
+system.cpu1.dtb.walker.walksPending::total -1978443032
+system.cpu1.dtb.walker.walkPageSizes::4K 1317 71.85% 71.85%
+system.cpu1.dtb.walker.walkPageSizes::1M 516 28.15% 100.00%
+system.cpu1.dtb.walker.walkPageSizes::total 1833
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 23296
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 23296
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1833
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1833
+system.cpu1.dtb.walker.walkRequestOrigin::total 25129
+system.cpu1.dtb.inst_hits 0
+system.cpu1.dtb.inst_misses 0
+system.cpu1.dtb.read_hits 10529198
+system.cpu1.dtb.read_misses 21069
+system.cpu1.dtb.write_hits 6472938
+system.cpu1.dtb.write_misses 2227
+system.cpu1.dtb.flush_tlb 66
+system.cpu1.dtb.flush_tlb_mva 917
+system.cpu1.dtb.flush_tlb_mva_asid 0
+system.cpu1.dtb.flush_tlb_asid 0
+system.cpu1.dtb.flush_entries 1638
+system.cpu1.dtb.align_faults 128
+system.cpu1.dtb.prefetch_faults 280
+system.cpu1.dtb.domain_faults 0
+system.cpu1.dtb.perms_faults 174
+system.cpu1.dtb.read_accesses 10550267
+system.cpu1.dtb.write_accesses 6475165
+system.cpu1.dtb.inst_accesses 0
+system.cpu1.dtb.hits 17002136
+system.cpu1.dtb.misses 23296
+system.cpu1.dtb.accesses 17025432
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu1.istage2_mmu.stage2_tlb.hits 0
+system.cpu1.istage2_mmu.stage2_tlb.misses 0
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu1.itb.walker.walks 2043
+system.cpu1.itb.walker.walksShort 2043
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1 145
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1898
+system.cpu1.itb.walker.walkWaitTime::samples 2043
+system.cpu1.itb.walker.walkWaitTime::0 2043 100.00% 100.00%
+system.cpu1.itb.walker.walkWaitTime::total 2043
+system.cpu1.itb.walker.walkCompletionTime::samples 839
+system.cpu1.itb.walker.walkCompletionTime::mean 11990.464839
+system.cpu1.itb.walker.walkCompletionTime::gmean 11429.168642
+system.cpu1.itb.walker.walkCompletionTime::stdev 4526.562247
+system.cpu1.itb.walker.walkCompletionTime::4096-8191 132 15.73% 15.73%
+system.cpu1.itb.walker.walkCompletionTime::8192-12287 566 67.46% 83.19%
+system.cpu1.itb.walker.walkCompletionTime::12288-16383 80 9.54% 92.73%
+system.cpu1.itb.walker.walkCompletionTime::16384-20479 15 1.79% 94.52%
+system.cpu1.itb.walker.walkCompletionTime::20480-24575 16 1.91% 96.42%
+system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 2.50% 98.93%
+system.cpu1.itb.walker.walkCompletionTime::28672-32767 4 0.48% 99.40%
+system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 99.52%
+system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.48% 100.00%
+system.cpu1.itb.walker.walkCompletionTime::total 839
+system.cpu1.itb.walker.walksPending::samples -1979056532
+system.cpu1.itb.walker.walksPending::0 -1979056532 100.00% 100.00%
+system.cpu1.itb.walker.walksPending::total -1979056532
+system.cpu1.itb.walker.walkPageSizes::4K 704 83.91% 83.91%
+system.cpu1.itb.walker.walkPageSizes::1M 135 16.09% 100.00%
+system.cpu1.itb.walker.walkPageSizes::total 839
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2043
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2043
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 839
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 839
+system.cpu1.itb.walker.walkRequestOrigin::total 2882
+system.cpu1.itb.inst_hits 38615960
+system.cpu1.itb.inst_misses 2043
+system.cpu1.itb.read_hits 0
+system.cpu1.itb.read_misses 0
+system.cpu1.itb.write_hits 0
+system.cpu1.itb.write_misses 0
+system.cpu1.itb.flush_tlb 66
+system.cpu1.itb.flush_tlb_mva 917
+system.cpu1.itb.flush_tlb_mva_asid 0
+system.cpu1.itb.flush_tlb_asid 0
+system.cpu1.itb.flush_entries 839
+system.cpu1.itb.align_faults 0
+system.cpu1.itb.prefetch_faults 0
+system.cpu1.itb.domain_faults 0
+system.cpu1.itb.perms_faults 1023
+system.cpu1.itb.read_accesses 0
+system.cpu1.itb.write_accesses 0
+system.cpu1.itb.inst_accesses 38618003
+system.cpu1.itb.hits 38615960
+system.cpu1.itb.misses 2043
+system.cpu1.itb.accesses 38618003
+system.cpu1.numPwrStateTransitions 5477
+system.cpu1.pwrStateClkGateDist::samples 2739
+system.cpu1.pwrStateClkGateDist::mean 1019579687.534502
+system.cpu1.pwrStateClkGateDist::stdev 25827377354.972477
+system.cpu1.pwrStateClkGateDist::underflows 1941 70.87% 70.87%
+system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.99% 99.85%
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89%
+system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93%
+system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96%
+system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00%
+system.cpu1.pwrStateClkGateDist::min_value 501
+system.cpu1.pwrStateClkGateDist::max_value 949980339048
+system.cpu1.pwrStateClkGateDist::total 2739
+system.cpu1.pwrStateResidencyTicks::ON 55995084843
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 2792628764157
+system.cpu1.numCycles 111993643
+system.cpu1.numWorkItemsStarted 0
+system.cpu1.numWorkItemsCompleted 0
+system.cpu1.committedInsts 45058323
+system.cpu1.committedOps 55122142
+system.cpu1.discardedOps 4846390
+system.cpu1.numFetchSuspends 2739
+system.cpu1.quiesceCycles 5584580714
+system.cpu1.cpi 2.485526
+system.cpu1.ipc 0.402329
+system.cpu1.op_class_0::No_OpClass 24 0.00% 0.00%
+system.cpu1.op_class_0::IntAlu 38106633 69.13% 69.13%
+system.cpu1.op_class_0::IntMult 43626 0.08% 69.21%
+system.cpu1.op_class_0::IntDiv 0 0.00% 69.21%
+system.cpu1.op_class_0::FloatAdd 0 0.00% 69.21%
+system.cpu1.op_class_0::FloatCmp 0 0.00% 69.21%
+system.cpu1.op_class_0::FloatCvt 0 0.00% 69.21%
+system.cpu1.op_class_0::FloatMult 0 0.00% 69.21%
+system.cpu1.op_class_0::FloatMultAcc 0 0.00% 69.21%
+system.cpu1.op_class_0::FloatDiv 0 0.00% 69.21%
+system.cpu1.op_class_0::FloatMisc 0 0.00% 69.21%
+system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdAdd 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdAlu 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdCmp 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdCvt 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdMisc 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdMult 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdShift 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.21%
+system.cpu1.op_class_0::SimdFloatMisc 3226 0.01% 69.22%
+system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.22%
+system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.22%
+system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.22%
+system.cpu1.op_class_0::MemRead 10387182 18.84% 88.06%
+system.cpu1.op_class_0::MemWrite 6581451 11.94% 100.00%
+system.cpu1.op_class_0::FloatMemRead 0 0.00% 100.00%
+system.cpu1.op_class_0::FloatMemWrite 0 0.00% 100.00%
+system.cpu1.op_class_0::IprAccess 0 0.00% 100.00%
+system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00%
+system.cpu1.op_class_0::total 55122142
+system.cpu1.kern.inst.arm 0
+system.cpu1.kern.inst.quiesce 2739
+system.cpu1.tickCycles 90175152
+system.cpu1.idleCycles 21818491
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu1.dcache.tags.replacements 157331
+system.cpu1.dcache.tags.tagsinuse 476.847164
+system.cpu1.dcache.tags.total_refs 16649796
+system.cpu1.dcache.tags.sampled_refs 157683
+system.cpu1.dcache.tags.avg_refs 105.590305
+system.cpu1.dcache.tags.warmup_cycle 91198641000
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 476.847164
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.931342
+system.cpu1.dcache.tags.occ_percent::total 0.931342
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 352
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 281
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 71
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500
+system.cpu1.dcache.tags.tag_accesses 34038904
+system.cpu1.dcache.tags.data_accesses 34038904
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu1.dcache.ReadReq_hits::cpu1.data 10204478
+system.cpu1.dcache.ReadReq_hits::total 10204478
+system.cpu1.dcache.WriteReq_hits::cpu1.data 6223179
+system.cpu1.dcache.WriteReq_hits::total 6223179
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 43363
+system.cpu1.dcache.SoftPFReq_hits::total 43363
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 71238
+system.cpu1.dcache.LoadLockedReq_hits::total 71238
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 62639
+system.cpu1.dcache.StoreCondReq_hits::total 62639
+system.cpu1.dcache.demand_hits::cpu1.data 16427657
+system.cpu1.dcache.demand_hits::total 16427657
+system.cpu1.dcache.overall_hits::cpu1.data 16471020
+system.cpu1.dcache.overall_hits::total 16471020
+system.cpu1.dcache.ReadReq_misses::cpu1.data 127297
+system.cpu1.dcache.ReadReq_misses::total 127297
+system.cpu1.dcache.WriteReq_misses::cpu1.data 122320
+system.cpu1.dcache.WriteReq_misses::total 122320
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24104
+system.cpu1.dcache.SoftPFReq_misses::total 24104
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16534
+system.cpu1.dcache.LoadLockedReq_misses::total 16534
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23351
+system.cpu1.dcache.StoreCondReq_misses::total 23351
+system.cpu1.dcache.demand_misses::cpu1.data 249617
+system.cpu1.dcache.demand_misses::total 249617
+system.cpu1.dcache.overall_misses::cpu1.data 273721
+system.cpu1.dcache.overall_misses::total 273721
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2189061000
+system.cpu1.dcache.ReadReq_miss_latency::total 2189061000
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3812195000
+system.cpu1.dcache.WriteReq_miss_latency::total 3812195000
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322706000
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 322706000
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 548331500
+system.cpu1.dcache.StoreCondReq_miss_latency::total 548331500
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 559500
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 559500
+system.cpu1.dcache.demand_miss_latency::cpu1.data 6001256000
+system.cpu1.dcache.demand_miss_latency::total 6001256000
+system.cpu1.dcache.overall_miss_latency::cpu1.data 6001256000
+system.cpu1.dcache.overall_miss_latency::total 6001256000
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 10331775
+system.cpu1.dcache.ReadReq_accesses::total 10331775
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 6345499
+system.cpu1.dcache.WriteReq_accesses::total 6345499
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67467
+system.cpu1.dcache.SoftPFReq_accesses::total 67467
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87772
+system.cpu1.dcache.LoadLockedReq_accesses::total 87772
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85990
+system.cpu1.dcache.StoreCondReq_accesses::total 85990
+system.cpu1.dcache.demand_accesses::cpu1.data 16677274
+system.cpu1.dcache.demand_accesses::total 16677274
+system.cpu1.dcache.overall_accesses::cpu1.data 16744741
+system.cpu1.dcache.overall_accesses::total 16744741
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.012321
+system.cpu1.dcache.ReadReq_miss_rate::total 0.012321
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.019277
+system.cpu1.dcache.WriteReq_miss_rate::total 0.019277
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.357271
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.357271
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188374
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188374
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.271555
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.271555
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014967
+system.cpu1.dcache.demand_miss_rate::total 0.014967
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.016347
+system.cpu1.dcache.overall_miss_rate::total 0.016347
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17196.485385
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 17196.485385
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31165.753761
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 31165.753761
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19517.721060
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19517.721060
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23482.142092
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23482.142092
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24041.856124
+system.cpu1.dcache.demand_avg_miss_latency::total 24041.856124
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21924.718966
+system.cpu1.dcache.overall_avg_miss_latency::total 21924.718966
+system.cpu1.dcache.blocked_cycles::no_mshrs 0
+system.cpu1.dcache.blocked_cycles::no_targets 0
+system.cpu1.dcache.blocked::no_mshrs 0
+system.cpu1.dcache.blocked::no_targets 0
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan
+system.cpu1.dcache.writebacks::writebacks 157331
+system.cpu1.dcache.writebacks::total 157331
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 4468
+system.cpu1.dcache.ReadReq_mshr_hits::total 4468
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42295
+system.cpu1.dcache.WriteReq_mshr_hits::total 42295
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11754
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11754
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 46763
+system.cpu1.dcache.demand_mshr_hits::total 46763
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 46763
+system.cpu1.dcache.overall_mshr_hits::total 46763
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 122829
+system.cpu1.dcache.ReadReq_mshr_misses::total 122829
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 80025
+system.cpu1.dcache.WriteReq_mshr_misses::total 80025
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23596
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 23596
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4780
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4780
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23351
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 23351
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 202854
+system.cpu1.dcache.demand_mshr_misses::total 202854
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 226450
+system.cpu1.dcache.overall_mshr_misses::total 226450
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14406
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14406
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11728
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11728
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26134
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26134
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1984683000
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1984683000
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2311631500
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2311631500
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 417855500
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 417855500
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86123500
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86123500
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 524993500
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 524993500
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 546500
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 546500
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4296314500
+system.cpu1.dcache.demand_mshr_miss_latency::total 4296314500
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4714170000
+system.cpu1.dcache.overall_mshr_miss_latency::total 4714170000
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2490233000
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2490233000
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2490233000
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2490233000
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.011888
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.011888
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012611
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012611
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.349741
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.349741
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054459
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054459
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.271555
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.271555
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.012163
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.012163
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.013524
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.013524
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16158.097843
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16158.097843
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28886.366760
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28886.366760
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17708.743007
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17708.743007
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18017.468619
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18017.468619
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22482.698814
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22482.698814
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21179.343272
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21179.343272
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20817.708103
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20817.708103
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172860.821880
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172860.821880
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95287.097268
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95287.097268
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu1.icache.tags.replacements 872942
+system.cpu1.icache.tags.tagsinuse 499.208587
+system.cpu1.icache.tags.total_refs 37741446
+system.cpu1.icache.tags.sampled_refs 873454
+system.cpu1.icache.tags.avg_refs 43.209426
+system.cpu1.icache.tags.warmup_cycle 72896771000
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.208587
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975017
+system.cpu1.icache.tags.occ_percent::total 0.975017
+system.cpu1.icache.tags.occ_task_id_blocks::1024 512
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 464
+system.cpu1.icache.tags.age_task_id_blocks_1024::3 47
+system.cpu1.icache.tags.age_task_id_blocks_1024::4 1
+system.cpu1.icache.tags.occ_task_id_percent::1024 1
+system.cpu1.icache.tags.tag_accesses 78103254
+system.cpu1.icache.tags.data_accesses 78103254
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu1.icache.ReadReq_hits::cpu1.inst 37741446
+system.cpu1.icache.ReadReq_hits::total 37741446
+system.cpu1.icache.demand_hits::cpu1.inst 37741446
+system.cpu1.icache.demand_hits::total 37741446
+system.cpu1.icache.overall_hits::cpu1.inst 37741446
+system.cpu1.icache.overall_hits::total 37741446
+system.cpu1.icache.ReadReq_misses::cpu1.inst 873454
+system.cpu1.icache.ReadReq_misses::total 873454
+system.cpu1.icache.demand_misses::cpu1.inst 873454
+system.cpu1.icache.demand_misses::total 873454
+system.cpu1.icache.overall_misses::cpu1.inst 873454
+system.cpu1.icache.overall_misses::total 873454
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8016929000
+system.cpu1.icache.ReadReq_miss_latency::total 8016929000
+system.cpu1.icache.demand_miss_latency::cpu1.inst 8016929000
+system.cpu1.icache.demand_miss_latency::total 8016929000
+system.cpu1.icache.overall_miss_latency::cpu1.inst 8016929000
+system.cpu1.icache.overall_miss_latency::total 8016929000
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 38614900
+system.cpu1.icache.ReadReq_accesses::total 38614900
+system.cpu1.icache.demand_accesses::cpu1.inst 38614900
+system.cpu1.icache.demand_accesses::total 38614900
+system.cpu1.icache.overall_accesses::cpu1.inst 38614900
+system.cpu1.icache.overall_accesses::total 38614900
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022620
+system.cpu1.icache.ReadReq_miss_rate::total 0.022620
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022620
+system.cpu1.icache.demand_miss_rate::total 0.022620
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022620
+system.cpu1.icache.overall_miss_rate::total 0.022620
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9178.421531
+system.cpu1.icache.ReadReq_avg_miss_latency::total 9178.421531
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9178.421531
+system.cpu1.icache.demand_avg_miss_latency::total 9178.421531
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9178.421531
+system.cpu1.icache.overall_avg_miss_latency::total 9178.421531
+system.cpu1.icache.blocked_cycles::no_mshrs 0
+system.cpu1.icache.blocked_cycles::no_targets 0
+system.cpu1.icache.blocked::no_mshrs 0
+system.cpu1.icache.blocked::no_targets 0
+system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
+system.cpu1.icache.avg_blocked_cycles::no_targets nan
+system.cpu1.icache.writebacks::writebacks 872942
+system.cpu1.icache.writebacks::total 872942
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 873454
+system.cpu1.icache.ReadReq_mshr_misses::total 873454
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 873454
+system.cpu1.icache.demand_mshr_misses::total 873454
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 873454
+system.cpu1.icache.overall_mshr_misses::total 873454
+system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112
+system.cpu1.icache.ReadReq_mshr_uncacheable::total 112
+system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112
+system.cpu1.icache.overall_mshr_uncacheable_misses::total 112
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7580202000
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 7580202000
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7580202000
+system.cpu1.icache.demand_mshr_miss_latency::total 7580202000
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7580202000
+system.cpu1.icache.overall_mshr_miss_latency::total 7580202000
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11042500
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 11042500
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 11042500
+system.cpu1.icache.overall_mshr_uncacheable_latency::total 11042500
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022620
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022620
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022620
+system.cpu1.icache.demand_mshr_miss_rate::total 0.022620
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022620
+system.cpu1.icache.overall_mshr_miss_rate::total 0.022620
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8678.421531
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8678.421531
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8678.421531
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 8678.421531
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8678.421531
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 8678.421531
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 98593.750000
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 98593.750000
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu1.l2cache.prefetcher.num_hwpf_issued 118133
+system.cpu1.l2cache.prefetcher.pfIdentified 118165
+system.cpu1.l2cache.prefetcher.pfBufferHit 27
+system.cpu1.l2cache.prefetcher.pfInCache 0
+system.cpu1.l2cache.prefetcher.pfRemovedFull 0
+system.cpu1.l2cache.prefetcher.pfSpanPage 48899
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu1.l2cache.tags.replacements 37449
+system.cpu1.l2cache.tags.tagsinuse 14754.261242
+system.cpu1.l2cache.tags.total_refs 949403
+system.cpu1.l2cache.tags.sampled_refs 52157
+system.cpu1.l2cache.tags.avg_refs 18.202792
+system.cpu1.l2cache.tags.warmup_cycle 0
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14416.237404
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.337553
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.132408
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 298.553878
+system.cpu1.l2cache.tags.occ_percent::writebacks 0.879897
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002340
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000069
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.018222
+system.cpu1.l2cache.tags.occ_percent::total 0.900529
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022 263
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023 80
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14365
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 22
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 239
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 58
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1288
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2922
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10155
+system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.016052
+system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004883
+system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.876770
+system.cpu1.l2cache.tags.tag_accesses 35693448
+system.cpu1.l2cache.tags.data_accesses 35693448
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 23875
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2548
+system.cpu1.l2cache.ReadReq_hits::total 26423
+system.cpu1.l2cache.WritebackDirty_hits::writebacks 95204
+system.cpu1.l2cache.WritebackDirty_hits::total 95204
+system.cpu1.l2cache.WritebackClean_hits::writebacks 916199
+system.cpu1.l2cache.WritebackClean_hits::total 916199
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18135
+system.cpu1.l2cache.ReadExReq_hits::total 18135
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 844876
+system.cpu1.l2cache.ReadCleanReq_hits::total 844876
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 81478
+system.cpu1.l2cache.ReadSharedReq_hits::total 81478
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 23875
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2548
+system.cpu1.l2cache.demand_hits::cpu1.inst 844876
+system.cpu1.l2cache.demand_hits::cpu1.data 99613
+system.cpu1.l2cache.demand_hits::total 970912
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 23875
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2548
+system.cpu1.l2cache.overall_hits::cpu1.inst 844876
+system.cpu1.l2cache.overall_hits::cpu1.data 99613
+system.cpu1.l2cache.overall_hits::total 970912
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 800
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 289
+system.cpu1.l2cache.ReadReq_misses::total 1089
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29346
+system.cpu1.l2cache.UpgradeReq_misses::total 29346
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23351
+system.cpu1.l2cache.SCUpgradeReq_misses::total 23351
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32545
+system.cpu1.l2cache.ReadExReq_misses::total 32545
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 28578
+system.cpu1.l2cache.ReadCleanReq_misses::total 28578
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69726
+system.cpu1.l2cache.ReadSharedReq_misses::total 69726
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 800
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker 289
+system.cpu1.l2cache.demand_misses::cpu1.inst 28578
+system.cpu1.l2cache.demand_misses::cpu1.data 102271
+system.cpu1.l2cache.demand_misses::total 131938
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 800
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker 289
+system.cpu1.l2cache.overall_misses::cpu1.inst 28578
+system.cpu1.l2cache.overall_misses::cpu1.data 102271
+system.cpu1.l2cache.overall_misses::total 131938
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 20317000
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5721500
+system.cpu1.l2cache.ReadReq_miss_latency::total 26038500
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 7548500
+system.cpu1.l2cache.UpgradeReq_miss_latency::total 7548500
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 16857000
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 16857000
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 525500
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 525500
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1443665500
+system.cpu1.l2cache.ReadExReq_miss_latency::total 1443665500
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1151971000
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1151971000
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1718484993
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1718484993
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 20317000
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5721500
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1151971000
+system.cpu1.l2cache.demand_miss_latency::cpu1.data 3162150493
+system.cpu1.l2cache.demand_miss_latency::total 4340159993
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 20317000
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5721500
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1151971000
+system.cpu1.l2cache.overall_miss_latency::cpu1.data 3162150493
+system.cpu1.l2cache.overall_miss_latency::total 4340159993
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 24675
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2837
+system.cpu1.l2cache.ReadReq_accesses::total 27512
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks 95204
+system.cpu1.l2cache.WritebackDirty_accesses::total 95204
+system.cpu1.l2cache.WritebackClean_accesses::writebacks 916199
+system.cpu1.l2cache.WritebackClean_accesses::total 916199
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29346
+system.cpu1.l2cache.UpgradeReq_accesses::total 29346
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23351
+system.cpu1.l2cache.SCUpgradeReq_accesses::total 23351
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50680
+system.cpu1.l2cache.ReadExReq_accesses::total 50680
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 873454
+system.cpu1.l2cache.ReadCleanReq_accesses::total 873454
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 151204
+system.cpu1.l2cache.ReadSharedReq_accesses::total 151204
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 24675
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2837
+system.cpu1.l2cache.demand_accesses::cpu1.inst 873454
+system.cpu1.l2cache.demand_accesses::cpu1.data 201884
+system.cpu1.l2cache.demand_accesses::total 1102850
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 24675
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2837
+system.cpu1.l2cache.overall_accesses::cpu1.inst 873454
+system.cpu1.l2cache.overall_accesses::cpu1.data 201884
+system.cpu1.l2cache.overall_accesses::total 1102850
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.032421
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.101868
+system.cpu1.l2cache.ReadReq_miss_rate::total 0.039583
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1
+system.cpu1.l2cache.UpgradeReq_miss_rate::total 1
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.642167
+system.cpu1.l2cache.ReadExReq_miss_rate::total 0.642167
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.032718
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.032718
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.461139
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.461139
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.032421
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.101868
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.032718
+system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.506583
+system.cpu1.l2cache.demand_miss_rate::total 0.119634
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.032421
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.101868
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.032718
+system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.506583
+system.cpu1.l2cache.overall_miss_rate::total 0.119634
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25396.250000
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19797.577855
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23910.468320
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 257.224153
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 257.224153
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 721.896279
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 721.896279
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44359.056691
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44359.056691
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40309.713766
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40309.713766
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 24646.258110
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 24646.258110
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25396.250000
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19797.577855
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40309.713766
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30919.327014
+system.cpu1.l2cache.demand_avg_miss_latency::total 32895.450841
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25396.250000
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19797.577855
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40309.713766
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30919.327014
+system.cpu1.l2cache.overall_avg_miss_latency::total 32895.450841
+system.cpu1.l2cache.blocked_cycles::no_mshrs 0
+system.cpu1.l2cache.blocked_cycles::no_targets 0
+system.cpu1.l2cache.blocked::no_mshrs 0
+system.cpu1.l2cache.blocked::no_targets 0
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu1.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu1.l2cache.unused_prefetches 608
+system.cpu1.l2cache.writebacks::writebacks 29316
+system.cpu1.l2cache.writebacks::total 29316
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3
+system.cpu1.l2cache.ReadReq_mshr_hits::total 3
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 183
+system.cpu1.l2cache.ReadExReq_mshr_hits::total 183
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 42
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 42
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 9
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data 225
+system.cpu1.l2cache.demand_mshr_hits::total 237
+system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 9
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data 225
+system.cpu1.l2cache.overall_mshr_hits::total 237
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 800
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 286
+system.cpu1.l2cache.ReadReq_mshr_misses::total 1086
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 19599
+system.cpu1.l2cache.HardPFReq_mshr_misses::total 19599
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29346
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29346
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23351
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23351
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32362
+system.cpu1.l2cache.ReadExReq_mshr_misses::total 32362
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 28569
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 28569
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69684
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69684
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 800
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 286
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 28569
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102046
+system.cpu1.l2cache.demand_mshr_misses::total 131701
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 800
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 286
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 28569
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102046
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 19599
+system.cpu1.l2cache.overall_mshr_misses::total 151300
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14406
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14518
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11728
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11728
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26134
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26246
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 15517000
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3959500
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 19476500
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 753093878
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 753093878
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 447116000
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 447116000
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 348719500
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 348719500
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 447500
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 447500
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1228645000
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1228645000
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 980270500
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 980270500
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1298411493
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1298411493
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 15517000
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3959500
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 980270500
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2527056493
+system.cpu1.l2cache.demand_mshr_miss_latency::total 3526803493
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 15517000
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3959500
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 980270500
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2527056493
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 753093878
+system.cpu1.l2cache.overall_mshr_miss_latency::total 4279897371
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10146500
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2374963000
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2385109500
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10146500
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2374963000
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2385109500
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.032421
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.100811
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.039474
+system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf
+system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.638556
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.638556
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.032708
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.032708
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.460861
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.460861
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.032421
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.100811
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.032708
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.505468
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119419
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.032421
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.100811
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.032708
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.505468
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.137190
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19396.250000
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13844.405594
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17934.162063
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38425.117506
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38425.117506
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15236.011722
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15236.011722
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14933.814398
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14933.814398
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37965.669613
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37965.669613
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34312.384053
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34312.384053
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18632.849621
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18632.849621
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19396.250000
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13844.405594
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34312.384053
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24763.895626
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26778.866470
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19396.250000
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13844.405594
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34312.384053
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24763.895626
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38425.117506
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28287.490886
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164859.294738
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164286.368646
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90876.367950
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90875.161929
+system.cpu1.toL2Bus.snoop_filter.tot_requests 2165698
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1090387
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18868
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 115904
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 107947
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7957
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.cpu1.toL2Bus.trans_dist::ReadReq 45297
+system.cpu1.toL2Bus.trans_dist::ReadResp 1106851
+system.cpu1.toL2Bus.trans_dist::WriteReq 11728
+system.cpu1.toL2Bus.trans_dist::WriteResp 11728
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 126681
+system.cpu1.toL2Bus.trans_dist::WritebackClean 935068
+system.cpu1.toL2Bus.trans_dist::CleanEvict 26505
+system.cpu1.toL2Bus.trans_dist::HardPFReq 23783
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 72033
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41786
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 84874
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 18
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 31
+system.cpu1.toL2Bus.trans_dist::ReadExReq 57990
+system.cpu1.toL2Bus.trans_dist::ReadExResp 55336
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 873454
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263190
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 83
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2620074
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 792520
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6778
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51513
+system.cpu1.toL2Bus.pkt_count::total 3470885
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 111776512
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25752830
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11348
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 98700
+system.cpu1.toL2Bus.pkt_size::total 137639390
+system.cpu1.toL2Bus.snoops 339311
+system.cpu1.toL2Bus.snoopTraffic 4688012
+system.cpu1.toL2Bus.snoop_fanout::samples 1447344
+system.cpu1.toL2Bus.snoop_fanout::mean 0.103724
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.322430
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu1.toL2Bus.snoop_fanout::0 1305176 90.18% 90.18%
+system.cpu1.toL2Bus.snoop_fanout::1 134211 9.27% 99.45%
+system.cpu1.toL2Bus.snoop_fanout::2 7957 0.55% 100.00%
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu1.toL2Bus.snoop_fanout::min_value 0
+system.cpu1.toL2Bus.snoop_fanout::max_value 2
+system.cpu1.toL2Bus.snoop_fanout::total 1447344
+system.cpu1.toL2Bus.reqLayer0.occupancy 2143805992
+system.cpu1.toL2Bus.reqLayer0.utilization 0.1
+system.cpu1.toL2Bus.snoopLayer0.occupancy 78479642
+system.cpu1.toL2Bus.snoopLayer0.utilization 0.0
+system.cpu1.toL2Bus.respLayer0.occupancy 1310404888
+system.cpu1.toL2Bus.respLayer0.utilization 0.0
+system.cpu1.toL2Bus.respLayer1.occupancy 351319768
+system.cpu1.toL2Bus.respLayer1.utilization 0.0
+system.cpu1.toL2Bus.respLayer2.occupancy 3943495
+system.cpu1.toL2Bus.respLayer2.utilization 0.0
+system.cpu1.toL2Bus.respLayer3.occupancy 26851972
+system.cpu1.toL2Bus.respLayer3.utilization 0.0
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.iobus.trans_dist::ReadReq 31007
+system.iobus.trans_dist::ReadResp 31007
+system.iobus.trans_dist::WriteReq 59424
+system.iobus.trans_dist::WriteResp 59424
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268
+system.iobus.pkt_count_system.bridge.master::total 107912
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72950
+system.iobus.pkt_count_system.realview.ide.dma::total 72950
+system.iobus.pkt_count::total 180862
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536
+system.iobus.pkt_size_system.bridge.master::total 162802
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321240
+system.iobus.pkt_size_system.realview.ide.dma::total 2321240
+system.iobus.pkt_size::total 2484042
+system.iobus.reqLayer0.occupancy 48434001
+system.iobus.reqLayer0.utilization 0.0
+system.iobus.reqLayer1.occupancy 110500
+system.iobus.reqLayer1.utilization 0.0
+system.iobus.reqLayer2.occupancy 324500
+system.iobus.reqLayer2.utilization 0.0
+system.iobus.reqLayer3.occupancy 28500
+system.iobus.reqLayer3.utilization 0.0
+system.iobus.reqLayer4.occupancy 12500
+system.iobus.reqLayer4.utilization 0.0
+system.iobus.reqLayer7.occupancy 85500
+system.iobus.reqLayer7.utilization 0.0
+system.iobus.reqLayer8.occupancy 602500
+system.iobus.reqLayer8.utilization 0.0
+system.iobus.reqLayer10.occupancy 19500
+system.iobus.reqLayer10.utilization 0.0
+system.iobus.reqLayer13.occupancy 11000
+system.iobus.reqLayer13.utilization 0.0
+system.iobus.reqLayer14.occupancy 8500
+system.iobus.reqLayer14.utilization 0.0
+system.iobus.reqLayer15.occupancy 8500
+system.iobus.reqLayer15.utilization 0.0
+system.iobus.reqLayer16.occupancy 47500
+system.iobus.reqLayer16.utilization 0.0
+system.iobus.reqLayer17.occupancy 9500
+system.iobus.reqLayer17.utilization 0.0
+system.iobus.reqLayer18.occupancy 8000
+system.iobus.reqLayer18.utilization 0.0
+system.iobus.reqLayer19.occupancy 2500
+system.iobus.reqLayer19.utilization 0.0
+system.iobus.reqLayer20.occupancy 9000
+system.iobus.reqLayer20.utilization 0.0
+system.iobus.reqLayer21.occupancy 8500
+system.iobus.reqLayer21.utilization 0.0
+system.iobus.reqLayer23.occupancy 6368000
+system.iobus.reqLayer23.utilization 0.0
+system.iobus.reqLayer24.occupancy 39055001
+system.iobus.reqLayer24.utilization 0.0
+system.iobus.reqLayer25.occupancy 187796294
+system.iobus.reqLayer25.utilization 0.0
+system.iobus.respLayer0.occupancy 84712000
+system.iobus.respLayer0.utilization 0.0
+system.iobus.respLayer3.occupancy 36774000
+system.iobus.respLayer3.utilization 0.0
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.iocache.tags.replacements 36457
+system.iocache.tags.tagsinuse 14.472725
+system.iocache.tags.total_refs 0
+system.iocache.tags.sampled_refs 36473
+system.iocache.tags.avg_refs 0
+system.iocache.tags.warmup_cycle 271902155000
+system.iocache.tags.occ_blocks::realview.ide 14.472725
+system.iocache.tags.occ_percent::realview.ide 0.904545
+system.iocache.tags.occ_percent::total 0.904545
+system.iocache.tags.occ_task_id_blocks::1023 16
+system.iocache.tags.age_task_id_blocks_1023::3 16
+system.iocache.tags.occ_task_id_percent::1023 1
+system.iocache.tags.tag_accesses 328275
+system.iocache.tags.data_accesses 328275
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.iocache.ReadReq_misses::realview.ide 251
+system.iocache.ReadReq_misses::total 251
+system.iocache.WriteLineReq_misses::realview.ide 36224
+system.iocache.WriteLineReq_misses::total 36224
+system.iocache.demand_misses::realview.ide 36475
+system.iocache.demand_misses::total 36475
+system.iocache.overall_misses::realview.ide 36475
+system.iocache.overall_misses::total 36475
+system.iocache.ReadReq_miss_latency::realview.ide 33525875
+system.iocache.ReadReq_miss_latency::total 33525875
+system.iocache.WriteLineReq_miss_latency::realview.ide 4369037419
+system.iocache.WriteLineReq_miss_latency::total 4369037419
+system.iocache.demand_miss_latency::realview.ide 4402563294
+system.iocache.demand_miss_latency::total 4402563294
+system.iocache.overall_miss_latency::realview.ide 4402563294
+system.iocache.overall_miss_latency::total 4402563294
+system.iocache.ReadReq_accesses::realview.ide 251
+system.iocache.ReadReq_accesses::total 251
+system.iocache.WriteLineReq_accesses::realview.ide 36224
+system.iocache.WriteLineReq_accesses::total 36224
+system.iocache.demand_accesses::realview.ide 36475
+system.iocache.demand_accesses::total 36475
+system.iocache.overall_accesses::realview.ide 36475
+system.iocache.overall_accesses::total 36475
+system.iocache.ReadReq_miss_rate::realview.ide 1
+system.iocache.ReadReq_miss_rate::total 1
+system.iocache.WriteLineReq_miss_rate::realview.ide 1
+system.iocache.WriteLineReq_miss_rate::total 1
+system.iocache.demand_miss_rate::realview.ide 1
+system.iocache.demand_miss_rate::total 1
+system.iocache.overall_miss_rate::realview.ide 1
+system.iocache.overall_miss_rate::total 1
+system.iocache.ReadReq_avg_miss_latency::realview.ide 133569.223108
+system.iocache.ReadReq_avg_miss_latency::total 133569.223108
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120611.677866
+system.iocache.WriteLineReq_avg_miss_latency::total 120611.677866
+system.iocache.demand_avg_miss_latency::realview.ide 120700.844249
+system.iocache.demand_avg_miss_latency::total 120700.844249
+system.iocache.overall_avg_miss_latency::realview.ide 120700.844249
+system.iocache.overall_avg_miss_latency::total 120700.844249
+system.iocache.blocked_cycles::no_mshrs 498
+system.iocache.blocked_cycles::no_targets 0
+system.iocache.blocked::no_mshrs 4
+system.iocache.blocked::no_targets 0
+system.iocache.avg_blocked_cycles::no_mshrs 124.500000
+system.iocache.avg_blocked_cycles::no_targets nan
+system.iocache.writebacks::writebacks 36206
+system.iocache.writebacks::total 36206
+system.iocache.ReadReq_mshr_misses::realview.ide 251
+system.iocache.ReadReq_mshr_misses::total 251
+system.iocache.WriteLineReq_mshr_misses::realview.ide 36224
+system.iocache.WriteLineReq_mshr_misses::total 36224
+system.iocache.demand_mshr_misses::realview.ide 36475
+system.iocache.demand_mshr_misses::total 36475
+system.iocache.overall_mshr_misses::realview.ide 36475
+system.iocache.overall_mshr_misses::total 36475
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 20975875
+system.iocache.ReadReq_mshr_miss_latency::total 20975875
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2555943544
+system.iocache.WriteLineReq_mshr_miss_latency::total 2555943544
+system.iocache.demand_mshr_miss_latency::realview.ide 2576919419
+system.iocache.demand_mshr_miss_latency::total 2576919419
+system.iocache.overall_mshr_miss_latency::realview.ide 2576919419
+system.iocache.overall_mshr_miss_latency::total 2576919419
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1
+system.iocache.ReadReq_mshr_miss_rate::total 1
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1
+system.iocache.WriteLineReq_mshr_miss_rate::total 1
+system.iocache.demand_mshr_miss_rate::realview.ide 1
+system.iocache.demand_mshr_miss_rate::total 1
+system.iocache.overall_mshr_miss_rate::realview.ide 1
+system.iocache.overall_mshr_miss_rate::total 1
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 83569.223108
+system.iocache.ReadReq_avg_mshr_miss_latency::total 83569.223108
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70559.395539
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70559.395539
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 70648.921700
+system.iocache.demand_avg_mshr_miss_latency::total 70648.921700
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 70648.921700
+system.iocache.overall_avg_mshr_miss_latency::total 70648.921700
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.l2c.tags.replacements 143741
+system.l2c.tags.tagsinuse 65154.311033
+system.l2c.tags.total_refs 605938
+system.l2c.tags.sampled_refs 209220
+system.l2c.tags.avg_refs 2.896176
+system.l2c.tags.warmup_cycle 94462980000
+system.l2c.tags.occ_blocks::writebacks 6696.148123
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 85.662080
+system.l2c.tags.occ_blocks::cpu0.itb.walker 0.029895
+system.l2c.tags.occ_blocks::cpu0.inst 8724.046305
+system.l2c.tags.occ_blocks::cpu0.data 6708.264318
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34991.261911
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.950937
+system.l2c.tags.occ_blocks::cpu1.inst 2215.206936
+system.l2c.tags.occ_blocks::cpu1.data 3461.157373
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2257.583155
+system.l2c.tags.occ_percent::writebacks 0.102175
+system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001307
+system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000
+system.l2c.tags.occ_percent::cpu0.inst 0.133118
+system.l2c.tags.occ_percent::cpu0.data 0.102360
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533924
+system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000228
+system.l2c.tags.occ_percent::cpu1.inst 0.033801
+system.l2c.tags.occ_percent::cpu1.data 0.052813
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034448
+system.l2c.tags.occ_percent::total 0.994176
+system.l2c.tags.occ_task_id_blocks::1022 32741
+system.l2c.tags.occ_task_id_blocks::1023 70
+system.l2c.tags.occ_task_id_blocks::1024 32668
+system.l2c.tags.age_task_id_blocks_1022::2 135
+system.l2c.tags.age_task_id_blocks_1022::3 5068
+system.l2c.tags.age_task_id_blocks_1022::4 27538
+system.l2c.tags.age_task_id_blocks_1023::3 1
+system.l2c.tags.age_task_id_blocks_1023::4 69
+system.l2c.tags.age_task_id_blocks_1024::0 4
+system.l2c.tags.age_task_id_blocks_1024::1 1
+system.l2c.tags.age_task_id_blocks_1024::2 118
+system.l2c.tags.age_task_id_blocks_1024::3 1804
+system.l2c.tags.age_task_id_blocks_1024::4 30741
+system.l2c.tags.occ_task_id_percent::1022 0.499588
+system.l2c.tags.occ_task_id_percent::1023 0.001068
+system.l2c.tags.occ_task_id_percent::1024 0.498474
+system.l2c.tags.tag_accesses 6808442
+system.l2c.tags.data_accesses 6808442
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.l2c.WritebackDirty_hits::writebacks 266227
+system.l2c.WritebackDirty_hits::total 266227
+system.l2c.UpgradeReq_hits::cpu0.data 43718
+system.l2c.UpgradeReq_hits::cpu1.data 4453
+system.l2c.UpgradeReq_hits::total 48171
+system.l2c.SCUpgradeReq_hits::cpu0.data 2952
+system.l2c.SCUpgradeReq_hits::cpu1.data 2121
+system.l2c.SCUpgradeReq_hits::total 5073
+system.l2c.ReadExReq_hits::cpu0.data 4385
+system.l2c.ReadExReq_hits::cpu1.data 1232
+system.l2c.ReadExReq_hits::total 5617
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 478
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker 82
+system.l2c.ReadSharedReq_hits::cpu0.inst 72769
+system.l2c.ReadSharedReq_hits::cpu0.data 66048
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 48713
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 82
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker 9
+system.l2c.ReadSharedReq_hits::cpu1.inst 24997
+system.l2c.ReadSharedReq_hits::cpu1.data 8438
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3692
+system.l2c.ReadSharedReq_hits::total 225308
+system.l2c.demand_hits::cpu0.dtb.walker 478
+system.l2c.demand_hits::cpu0.itb.walker 82
+system.l2c.demand_hits::cpu0.inst 72769
+system.l2c.demand_hits::cpu0.data 70433
+system.l2c.demand_hits::cpu0.l2cache.prefetcher 48713
+system.l2c.demand_hits::cpu1.dtb.walker 82
+system.l2c.demand_hits::cpu1.itb.walker 9
+system.l2c.demand_hits::cpu1.inst 24997
+system.l2c.demand_hits::cpu1.data 9670
+system.l2c.demand_hits::cpu1.l2cache.prefetcher 3692
+system.l2c.demand_hits::total 230925
+system.l2c.overall_hits::cpu0.dtb.walker 478
+system.l2c.overall_hits::cpu0.itb.walker 82
+system.l2c.overall_hits::cpu0.inst 72769
+system.l2c.overall_hits::cpu0.data 70433
+system.l2c.overall_hits::cpu0.l2cache.prefetcher 48713
+system.l2c.overall_hits::cpu1.dtb.walker 82
+system.l2c.overall_hits::cpu1.itb.walker 9
+system.l2c.overall_hits::cpu1.inst 24997
+system.l2c.overall_hits::cpu1.data 9670
+system.l2c.overall_hits::cpu1.l2cache.prefetcher 3692
+system.l2c.overall_hits::total 230925
+system.l2c.UpgradeReq_misses::cpu0.data 467
+system.l2c.UpgradeReq_misses::cpu1.data 174
+system.l2c.UpgradeReq_misses::total 641
+system.l2c.SCUpgradeReq_misses::cpu0.data 50
+system.l2c.SCUpgradeReq_misses::cpu1.data 72
+system.l2c.SCUpgradeReq_misses::total 122
+system.l2c.ReadExReq_misses::cpu0.data 11403
+system.l2c.ReadExReq_misses::cpu1.data 8599
+system.l2c.ReadExReq_misses::total 20002
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 149
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1
+system.l2c.ReadSharedReq_misses::cpu0.inst 22795
+system.l2c.ReadSharedReq_misses::cpu0.data 9975
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134395
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 20
+system.l2c.ReadSharedReq_misses::cpu1.inst 3572
+system.l2c.ReadSharedReq_misses::cpu1.data 1758
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5239
+system.l2c.ReadSharedReq_misses::total 177904
+system.l2c.demand_misses::cpu0.dtb.walker 149
+system.l2c.demand_misses::cpu0.itb.walker 1
+system.l2c.demand_misses::cpu0.inst 22795
+system.l2c.demand_misses::cpu0.data 21378
+system.l2c.demand_misses::cpu0.l2cache.prefetcher 134395
+system.l2c.demand_misses::cpu1.dtb.walker 20
+system.l2c.demand_misses::cpu1.inst 3572
+system.l2c.demand_misses::cpu1.data 10357
+system.l2c.demand_misses::cpu1.l2cache.prefetcher 5239
+system.l2c.demand_misses::total 197906
+system.l2c.overall_misses::cpu0.dtb.walker 149
+system.l2c.overall_misses::cpu0.itb.walker 1
+system.l2c.overall_misses::cpu0.inst 22795
+system.l2c.overall_misses::cpu0.data 21378
+system.l2c.overall_misses::cpu0.l2cache.prefetcher 134395
+system.l2c.overall_misses::cpu1.dtb.walker 20
+system.l2c.overall_misses::cpu1.inst 3572
+system.l2c.overall_misses::cpu1.data 10357
+system.l2c.overall_misses::cpu1.l2cache.prefetcher 5239
+system.l2c.overall_misses::total 197906
+system.l2c.UpgradeReq_miss_latency::cpu0.data 8660500
+system.l2c.UpgradeReq_miss_latency::cpu1.data 789500
+system.l2c.UpgradeReq_miss_latency::total 9450000
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data 536500
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data 199000
+system.l2c.SCUpgradeReq_miss_latency::total 735500
+system.l2c.ReadExReq_miss_latency::cpu0.data 1591551500
+system.l2c.ReadExReq_miss_latency::cpu1.data 819698500
+system.l2c.ReadExReq_miss_latency::total 2411250000
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 21194000
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 90000
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2323515000
+system.l2c.ReadSharedReq_miss_latency::cpu0.data 1219999500
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16143455282
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 4023000
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst 381119000
+system.l2c.ReadSharedReq_miss_latency::cpu1.data 259897000
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 675104910
+system.l2c.ReadSharedReq_miss_latency::total 21028397692
+system.l2c.demand_miss_latency::cpu0.dtb.walker 21194000
+system.l2c.demand_miss_latency::cpu0.itb.walker 90000
+system.l2c.demand_miss_latency::cpu0.inst 2323515000
+system.l2c.demand_miss_latency::cpu0.data 2811551000
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16143455282
+system.l2c.demand_miss_latency::cpu1.dtb.walker 4023000
+system.l2c.demand_miss_latency::cpu1.inst 381119000
+system.l2c.demand_miss_latency::cpu1.data 1079595500
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 675104910
+system.l2c.demand_miss_latency::total 23439647692
+system.l2c.overall_miss_latency::cpu0.dtb.walker 21194000
+system.l2c.overall_miss_latency::cpu0.itb.walker 90000
+system.l2c.overall_miss_latency::cpu0.inst 2323515000
+system.l2c.overall_miss_latency::cpu0.data 2811551000
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16143455282
+system.l2c.overall_miss_latency::cpu1.dtb.walker 4023000
+system.l2c.overall_miss_latency::cpu1.inst 381119000
+system.l2c.overall_miss_latency::cpu1.data 1079595500
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 675104910
+system.l2c.overall_miss_latency::total 23439647692
+system.l2c.WritebackDirty_accesses::writebacks 266227
+system.l2c.WritebackDirty_accesses::total 266227
+system.l2c.UpgradeReq_accesses::cpu0.data 44185
+system.l2c.UpgradeReq_accesses::cpu1.data 4627
+system.l2c.UpgradeReq_accesses::total 48812
+system.l2c.SCUpgradeReq_accesses::cpu0.data 3002
+system.l2c.SCUpgradeReq_accesses::cpu1.data 2193
+system.l2c.SCUpgradeReq_accesses::total 5195
+system.l2c.ReadExReq_accesses::cpu0.data 15788
+system.l2c.ReadExReq_accesses::cpu1.data 9831
+system.l2c.ReadExReq_accesses::total 25619
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 627
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 83
+system.l2c.ReadSharedReq_accesses::cpu0.inst 95564
+system.l2c.ReadSharedReq_accesses::cpu0.data 76023
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 183108
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 102
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 9
+system.l2c.ReadSharedReq_accesses::cpu1.inst 28569
+system.l2c.ReadSharedReq_accesses::cpu1.data 10196
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8931
+system.l2c.ReadSharedReq_accesses::total 403212
+system.l2c.demand_accesses::cpu0.dtb.walker 627
+system.l2c.demand_accesses::cpu0.itb.walker 83
+system.l2c.demand_accesses::cpu0.inst 95564
+system.l2c.demand_accesses::cpu0.data 91811
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher 183108
+system.l2c.demand_accesses::cpu1.dtb.walker 102
+system.l2c.demand_accesses::cpu1.itb.walker 9
+system.l2c.demand_accesses::cpu1.inst 28569
+system.l2c.demand_accesses::cpu1.data 20027
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8931
+system.l2c.demand_accesses::total 428831
+system.l2c.overall_accesses::cpu0.dtb.walker 627
+system.l2c.overall_accesses::cpu0.itb.walker 83
+system.l2c.overall_accesses::cpu0.inst 95564
+system.l2c.overall_accesses::cpu0.data 91811
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher 183108
+system.l2c.overall_accesses::cpu1.dtb.walker 102
+system.l2c.overall_accesses::cpu1.itb.walker 9
+system.l2c.overall_accesses::cpu1.inst 28569
+system.l2c.overall_accesses::cpu1.data 20027
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8931
+system.l2c.overall_accesses::total 428831
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.010569
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.037605
+system.l2c.UpgradeReq_miss_rate::total 0.013132
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.016656
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.032832
+system.l2c.SCUpgradeReq_miss_rate::total 0.023484
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.722257
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.874682
+system.l2c.ReadExReq_miss_rate::total 0.780749
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.237640
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.012048
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.238531
+system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.131210
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.733966
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.196078
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.125031
+system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.172421
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.586608
+system.l2c.ReadSharedReq_miss_rate::total 0.441217
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.237640
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.012048
+system.l2c.demand_miss_rate::cpu0.inst 0.238531
+system.l2c.demand_miss_rate::cpu0.data 0.232848
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.733966
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.196078
+system.l2c.demand_miss_rate::cpu1.inst 0.125031
+system.l2c.demand_miss_rate::cpu1.data 0.517152
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.586608
+system.l2c.demand_miss_rate::total 0.461501
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.237640
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.012048
+system.l2c.overall_miss_rate::cpu0.inst 0.238531
+system.l2c.overall_miss_rate::cpu0.data 0.232848
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.733966
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.196078
+system.l2c.overall_miss_rate::cpu1.inst 0.125031
+system.l2c.overall_miss_rate::cpu1.data 0.517152
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.586608
+system.l2c.overall_miss_rate::total 0.461501
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 18544.967880
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4537.356322
+system.l2c.UpgradeReq_avg_miss_latency::total 14742.589704
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 10730
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2763.888889
+system.l2c.SCUpgradeReq_avg_miss_latency::total 6028.688525
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139573.050952
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 95324.863356
+system.l2c.ReadExReq_avg_miss_latency::total 120550.444956
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 142241.610738
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90000
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 101930.905900
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 122305.714286
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 120119.463388
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 201150
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 106696.248600
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 147836.746303
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 128861.406757
+system.l2c.ReadSharedReq_avg_miss_latency::total 118200.814439
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 142241.610738
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90000
+system.l2c.demand_avg_miss_latency::cpu0.inst 101930.905900
+system.l2c.demand_avg_miss_latency::cpu0.data 131516.091309
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 120119.463388
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 201150
+system.l2c.demand_avg_miss_latency::cpu1.inst 106696.248600
+system.l2c.demand_avg_miss_latency::cpu1.data 104238.244665
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 128861.406757
+system.l2c.demand_avg_miss_latency::total 118438.287328
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 142241.610738
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90000
+system.l2c.overall_avg_miss_latency::cpu0.inst 101930.905900
+system.l2c.overall_avg_miss_latency::cpu0.data 131516.091309
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 120119.463388
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 201150
+system.l2c.overall_avg_miss_latency::cpu1.inst 106696.248600
+system.l2c.overall_avg_miss_latency::cpu1.data 104238.244665
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 128861.406757
+system.l2c.overall_avg_miss_latency::total 118438.287328
+system.l2c.blocked_cycles::no_mshrs 546
+system.l2c.blocked_cycles::no_targets 0
+system.l2c.blocked::no_mshrs 2
+system.l2c.blocked::no_targets 0
+system.l2c.avg_blocked_cycles::no_mshrs 273
+system.l2c.avg_blocked_cycles::no_targets nan
+system.l2c.writebacks::writebacks 104138
+system.l2c.writebacks::total 104138
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 2
+system.l2c.ReadSharedReq_mshr_hits::total 7
+system.l2c.demand_mshr_hits::cpu0.inst 5
+system.l2c.demand_mshr_hits::cpu1.inst 2
+system.l2c.demand_mshr_hits::total 7
+system.l2c.overall_mshr_hits::cpu0.inst 5
+system.l2c.overall_mshr_hits::cpu1.inst 2
+system.l2c.overall_mshr_hits::total 7
+system.l2c.CleanEvict_mshr_misses::writebacks 4255
+system.l2c.CleanEvict_mshr_misses::total 4255
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 467
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 174
+system.l2c.UpgradeReq_mshr_misses::total 641
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 50
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 72
+system.l2c.SCUpgradeReq_mshr_misses::total 122
+system.l2c.ReadExReq_mshr_misses::cpu0.data 11403
+system.l2c.ReadExReq_mshr_misses::cpu1.data 8599
+system.l2c.ReadExReq_mshr_misses::total 20002
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 149
+system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22790
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9975
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134395
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 20
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3570
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1758
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5239
+system.l2c.ReadSharedReq_mshr_misses::total 177897
+system.l2c.demand_mshr_misses::cpu0.dtb.walker 149
+system.l2c.demand_mshr_misses::cpu0.itb.walker 1
+system.l2c.demand_mshr_misses::cpu0.inst 22790
+system.l2c.demand_mshr_misses::cpu0.data 21378
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134395
+system.l2c.demand_mshr_misses::cpu1.dtb.walker 20
+system.l2c.demand_mshr_misses::cpu1.inst 3570
+system.l2c.demand_mshr_misses::cpu1.data 10357
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5239
+system.l2c.demand_mshr_misses::total 197899
+system.l2c.overall_mshr_misses::cpu0.dtb.walker 149
+system.l2c.overall_mshr_misses::cpu0.itb.walker 1
+system.l2c.overall_mshr_misses::cpu0.inst 22790
+system.l2c.overall_mshr_misses::cpu0.data 21378
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134395
+system.l2c.overall_mshr_misses::cpu1.dtb.walker 20
+system.l2c.overall_mshr_misses::cpu1.inst 3570
+system.l2c.overall_mshr_misses::cpu1.data 10357
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5239
+system.l2c.overall_mshr_misses::total 197899
+system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3277
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20583
+system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14403
+system.l2c.ReadReq_mshr_uncacheable::total 38375
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19292
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11728
+system.l2c.WriteReq_mshr_uncacheable::total 31020
+system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3277
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39875
+system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26131
+system.l2c.overall_mshr_uncacheable_misses::total 69395
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 10374500
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3853500
+system.l2c.UpgradeReq_mshr_miss_latency::total 14228000
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1334000
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1691000
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 3025000
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1477521500
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 733708500
+system.l2c.ReadExReq_mshr_miss_latency::total 2211230000
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 19704000
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 80000
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2094874500
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1120249500
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14799502289
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 3823000
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 345333500
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 242316501
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 622713912
+system.l2c.ReadSharedReq_mshr_miss_latency::total 19248597202
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 19704000
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000
+system.l2c.demand_mshr_miss_latency::cpu0.inst 2094874500
+system.l2c.demand_mshr_miss_latency::cpu0.data 2597771000
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14799502289
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 3823000
+system.l2c.demand_mshr_miss_latency::cpu1.inst 345333500
+system.l2c.demand_mshr_miss_latency::cpu1.data 976025001
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 622713912
+system.l2c.demand_mshr_miss_latency::total 21459827202
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 19704000
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000
+system.l2c.overall_mshr_miss_latency::cpu0.inst 2094874500
+system.l2c.overall_mshr_miss_latency::cpu0.data 2597771000
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14799502289
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 3823000
+system.l2c.overall_mshr_miss_latency::cpu1.inst 345333500
+system.l2c.overall_mshr_miss_latency::cpu1.data 976025001
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 622713912
+system.l2c.overall_mshr_miss_latency::total 21459827202
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 228848500
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4073216000
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7794500
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2115640500
+system.l2c.ReadReq_mshr_uncacheable_latency::total 6425499500
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 228848500
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4073216000
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7794500
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2115640500
+system.l2c.overall_mshr_uncacheable_latency::total 6425499500
+system.l2c.CleanEvict_mshr_miss_rate::writebacks inf
+system.l2c.CleanEvict_mshr_miss_rate::total inf
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.010569
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.037605
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.013132
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.016656
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.032832
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.023484
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.722257
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.874682
+system.l2c.ReadExReq_mshr_miss_rate::total 0.780749
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.237640
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.012048
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.238479
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.131210
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733966
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.196078
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.124961
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.172421
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.586608
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.441200
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.237640
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012048
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.238479
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.232848
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733966
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.196078
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.124961
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.517152
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.586608
+system.l2c.demand_mshr_miss_rate::total 0.461485
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.237640
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012048
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.238479
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.232848
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733966
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.196078
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.124961
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.517152
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.586608
+system.l2c.overall_mshr_miss_rate::total 0.461485
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22215.203426
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22146.551724
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22196.567863
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26680
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23486.111111
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24795.081967
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129573.050952
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 85324.863356
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 110550.444956
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132241.610738
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 91920.776656
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 112305.714286
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110119.441118
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 191150
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 96732.072829
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 137836.462457
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 118861.216263
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108200.797102
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132241.610738
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 91920.776656
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121516.091309
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110119.441118
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 191150
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 96732.072829
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94238.196485
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 118861.216263
+system.l2c.demand_avg_mshr_miss_latency::total 108438.280143
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132241.610738
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 91920.776656
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121516.091309
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110119.441118
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 191150
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 96732.072829
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94238.196485
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 118861.216263
+system.l2c.overall_avg_mshr_miss_latency::total 108438.280143
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197892.241170
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146888.877317
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167439.726384
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102149.617555
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80962.860204
+system.l2c.overall_avg_mshr_uncacheable_latency::total 92593.119101
+system.membus.snoop_filter.tot_requests 514509
+system.membus.snoop_filter.hit_single_requests 286339
+system.membus.snoop_filter.hit_multi_requests 635
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.membus.trans_dist::ReadReq 38375
+system.membus.trans_dist::ReadResp 216523
+system.membus.trans_dist::WriteReq 31020
+system.membus.trans_dist::WriteResp 31020
+system.membus.trans_dist::WritebackDirty 140344
+system.membus.trans_dist::CleanEvict 19042
+system.membus.trans_dist::UpgradeReq 61413
+system.membus.trans_dist::SCUpgradeReq 38691
+system.membus.trans_dist::UpgradeResp 2
+system.membus.trans_dist::ReadExReq 40527
+system.membus.trans_dist::ReadExResp 19982
+system.membus.trans_dist::ReadSharedReq 178148
+system.membus.trans_dist::InvalidateReq 36224
+system.membus.trans_dist::InvalidateResp 4303
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14152
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 655682
+system.membus.pkt_count_system.l2c.mem_side::total 777788
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72947
+system.membus.pkt_count_system.iocache.mem_side::total 72947
+system.membus.pkt_count::total 850735
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162802
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28304
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19543016
+system.membus.pkt_size_system.l2c.mem_side::total 19735466
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144
+system.membus.pkt_size_system.iocache.mem_side::total 2318144
+system.membus.pkt_size::total 22053610
+system.membus.snoops 124745
+system.membus.snoopTraffic 36736
+system.membus.snoop_fanout::samples 424399
+system.membus.snoop_fanout::mean 0.011640
+system.membus.snoop_fanout::stdev 0.107259
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 419459 98.84% 98.84%
+system.membus.snoop_fanout::1 4940 1.16% 100.00%
+system.membus.snoop_fanout::2 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 1
+system.membus.snoop_fanout::total 424399
+system.membus.reqLayer0.occupancy 95155498
+system.membus.reqLayer0.utilization 0.0
+system.membus.reqLayer1.occupancy 23328
+system.membus.reqLayer1.utilization 0.0
+system.membus.reqLayer2.occupancy 12482999
+system.membus.reqLayer2.utilization 0.0
+system.membus.reqLayer5.occupancy 1007290019
+system.membus.reqLayer5.utilization 0.0
+system.membus.respLayer2.occupancy 1153319410
+system.membus.respLayer2.utilization 0.0
+system.membus.respLayer3.occupancy 6842240
+system.membus.respLayer3.utilization 0.0
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.dcc.osc_cpu.clock 16667
+system.realview.dcc.osc_ddr.clock 25000
+system.realview.dcc.osc_hsbm.clock 25000
+system.realview.dcc.osc_pxl.clock 42105
+system.realview.dcc.osc_smb.clock 20000
+system.realview.dcc.osc_sys.clock 16667
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.ethernet.descDMAReads 0
+system.realview.ethernet.descDMAWrites 0
+system.realview.ethernet.descDmaReadBytes 0
+system.realview.ethernet.descDmaWriteBytes 0
+system.realview.ethernet.postedSwi 0
+system.realview.ethernet.coalescedSwi nan
+system.realview.ethernet.totalSwi 0
+system.realview.ethernet.postedRxIdle 0
+system.realview.ethernet.coalescedRxIdle nan
+system.realview.ethernet.totalRxIdle 0
+system.realview.ethernet.postedRxOk 0
+system.realview.ethernet.coalescedRxOk nan
+system.realview.ethernet.totalRxOk 0
+system.realview.ethernet.postedRxDesc 0
+system.realview.ethernet.coalescedRxDesc nan
+system.realview.ethernet.totalRxDesc 0
+system.realview.ethernet.postedTxOk 0
+system.realview.ethernet.coalescedTxOk nan
+system.realview.ethernet.totalTxOk 0
+system.realview.ethernet.postedTxIdle 0
+system.realview.ethernet.coalescedTxIdle nan
+system.realview.ethernet.totalTxIdle 0
+system.realview.ethernet.postedTxDesc 0
+system.realview.ethernet.coalescedTxDesc nan
+system.realview.ethernet.totalTxDesc 0
+system.realview.ethernet.postedRxOrn 0
+system.realview.ethernet.coalescedRxOrn nan
+system.realview.ethernet.totalRxOrn 0
+system.realview.ethernet.coalescedTotal nan
+system.realview.ethernet.postedInterrupts 0
+system.realview.ethernet.droppedPackets 0
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.mcc.osc_clcd.clock 42105
+system.realview.mcc.osc_mcc.clock 20000
+system.realview.mcc.osc_peripheral.clock 41667
+system.realview.mcc.osc_system_bus.clock 41667
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.toL2Bus.snoop_filter.tot_requests 1102536
+system.toL2Bus.snoop_filter.hit_single_requests 568062
+system.toL2Bus.snoop_filter.hit_multi_requests 209231
+system.toL2Bus.snoop_filter.tot_snoops 30967
+system.toL2Bus.snoop_filter.hit_single_snoops 29546
+system.toL2Bus.snoop_filter.hit_multi_snoops 1421
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848623849000
+system.toL2Bus.trans_dist::ReadReq 38378
+system.toL2Bus.trans_dist::ReadResp 559335
+system.toL2Bus.trans_dist::WriteReq 31020
+system.toL2Bus.trans_dist::WriteResp 31020
+system.toL2Bus.trans_dist::WritebackDirty 370365
+system.toL2Bus.trans_dist::CleanEvict 150278
+system.toL2Bus.trans_dist::UpgradeReq 109564
+system.toL2Bus.trans_dist::SCUpgradeReq 43764
+system.toL2Bus.trans_dist::UpgradeResp 153328
+system.toL2Bus.trans_dist::SCUpgradeFailReq 31
+system.toL2Bus.trans_dist::UpgradeFailResp 31
+system.toL2Bus.trans_dist::ReadExReq 51537
+system.toL2Bus.trans_dist::ReadExResp 51537
+system.toL2Bus.trans_dist::ReadSharedReq 520961
+system.toL2Bus.trans_dist::InvalidateReq 4360
+system.toL2Bus.trans_dist::InvalidateResp 3146
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1373233
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 354273
+system.toL2Bus.pkt_count::total 1727506
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 39252280
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5674546
+system.toL2Bus.pkt_size::total 44926826
+system.toL2Bus.snoops 394531
+system.toL2Bus.snoopTraffic 15861260
+system.toL2Bus.snoop_fanout::samples 943382
+system.toL2Bus.snoop_fanout::mean 0.393790
+system.toL2Bus.snoop_fanout::stdev 0.491663
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.toL2Bus.snoop_fanout::0 573309 60.77% 60.77%
+system.toL2Bus.snoop_fanout::1 368652 39.08% 99.85%
+system.toL2Bus.snoop_fanout::2 1421 0.15% 100.00%
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.toL2Bus.snoop_fanout::min_value 0
+system.toL2Bus.snoop_fanout::max_value 2
+system.toL2Bus.snoop_fanout::total 943382
+system.toL2Bus.reqLayer0.occupancy 940189543
+system.toL2Bus.reqLayer0.utilization 0.0
+system.toL2Bus.snoopLayer0.occupancy 1999903
+system.toL2Bus.snoopLayer0.utilization 0.0
+system.toL2Bus.respLayer0.occupancy 734750712
+system.toL2Bus.respLayer0.utilization 0.0
+system.toL2Bus.respLayer1.occupancy 258376523
+system.toL2Bus.respLayer1.utilization 0.0
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
+boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_panic=true
phys_addr_range_64=40
power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
+readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
+image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
sequential_access=false
size=32768
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
-children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
+children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
+opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
-opClass=FloatMult
+opClass=FloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
-opClass=FloatDiv
+opClass=FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
-opClass=FloatSqrt
+opClass=FloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
-opClass=SimdAdd
+opClass=FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
-opClass=SimdAddAcc
+opClass=FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
-opClass=SimdAlu
+opClass=SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
-opClass=SimdCmp
+opClass=SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
-opClass=SimdCvt
+opClass=SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
-opClass=SimdMisc
+opClass=SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
-opClass=SimdMult
+opClass=SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
-opClass=SimdMultAcc
+opClass=SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
-opClass=SimdShift
+opClass=SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
-opClass=SimdShiftAcc
+opClass=SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
-opClass=SimdSqrt
+opClass=SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatAdd
+opClass=SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatAlu
+opClass=SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatCmp
+opClass=SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatCvt
+opClass=SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatDiv
+opClass=SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatMisc
+opClass=SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatMult
+opClass=SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
-opClass=SimdFloatMultAcc
+opClass=SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
+opClass=SimdFloatMult
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26]
+type=MinorOpClass
+eventq_index=0
+opClass=SimdFloatMultAcc
+
+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27]
+type=MinorOpClass
+eventq_index=0
opClass=SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
-children=opClasses0 opClasses1
+children=opClasses0 opClasses1 opClasses2 opClasses3
eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
+opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=MemWrite
+[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatMemRead
+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatMemWrite
+
[system.cpu.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
sequential_access=false
size=32768
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
sequential_access=false
size=4194304
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=4194304
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
+data_latency=50
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=50
is_read_only=false
max_miss_count=0
mshrs=20
sequential_access=false
size=1024
system=system
+tag_latency=50
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
assoc=8
block_size=64
clk_domain=system.clk_domain
+data_latency=50
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=50
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1024
+tag_latency=50
[system.membus]
type=CoherentXBar
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+info: Entering event queue @ 0. Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:53:08
-gem5 executing on e108600-lin, pid 17485
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor
+gem5 compiled Mar 29 2017 19:38:26
+gem5 started Mar 29 2017 19:38:42
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83599
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2854925996500 because m5_exit instruction encountered
+Exiting @ tick 2854927627500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.854944 # Number of seconds simulated
-sim_ticks 2854944380500 # Number of ticks simulated
-final_tick 2854944380500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 264512 # Simulator instruction rate (inst/s)
-host_op_rate 319813 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6754449586 # Simulator tick rate (ticks/s)
-host_mem_usage 588784 # Number of bytes of host memory used
-host_seconds 422.68 # Real time elapsed on the host
-sim_insts 111803105 # Number of instructions simulated
-sim_ops 135177203 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker 6784 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1665024 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9168492 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10841388 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1665024 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1665024 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7956736 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7974260 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 106 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 26016 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 143779 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 169918 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 124324 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 128705 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 2376 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 583207 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3211443 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3797408 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 583207 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 583207 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2787002 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 6138 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2793140 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2787002 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 2376 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 583207 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3217581 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6590548 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 169918 # Number of read requests accepted
-system.physmem.writeReqs 128705 # Number of write requests accepted
-system.physmem.readBursts 169918 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 128705 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10866560 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7986688 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10841388 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7974260 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 10675 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10444 # Per bank write bursts
-system.physmem.perBankRdBursts::2 10743 # Per bank write bursts
-system.physmem.perBankRdBursts::3 10387 # Per bank write bursts
-system.physmem.perBankRdBursts::4 13022 # Per bank write bursts
-system.physmem.perBankRdBursts::5 10182 # Per bank write bursts
-system.physmem.perBankRdBursts::6 10267 # Per bank write bursts
-system.physmem.perBankRdBursts::7 10712 # Per bank write bursts
-system.physmem.perBankRdBursts::8 10430 # Per bank write bursts
-system.physmem.perBankRdBursts::9 10642 # Per bank write bursts
-system.physmem.perBankRdBursts::10 10231 # Per bank write bursts
-system.physmem.perBankRdBursts::11 9545 # Per bank write bursts
-system.physmem.perBankRdBursts::12 10746 # Per bank write bursts
-system.physmem.perBankRdBursts::13 11530 # Per bank write bursts
-system.physmem.perBankRdBursts::14 10184 # Per bank write bursts
-system.physmem.perBankRdBursts::15 10050 # Per bank write bursts
-system.physmem.perBankWrBursts::0 7937 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7870 # Per bank write bursts
-system.physmem.perBankWrBursts::2 8420 # Per bank write bursts
-system.physmem.perBankWrBursts::3 7905 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7296 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7361 # Per bank write bursts
-system.physmem.perBankWrBursts::6 7425 # Per bank write bursts
-system.physmem.perBankWrBursts::7 7903 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7956 # Per bank write bursts
-system.physmem.perBankWrBursts::9 8136 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7613 # Per bank write bursts
-system.physmem.perBankWrBursts::11 7341 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8127 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8673 # Per bank write bursts
-system.physmem.perBankWrBursts::14 7491 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7338 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 64 # Number of times write queue was full causing retry
-system.physmem.totGap 2854943930000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 543 # Read request sizes (log2)
-system.physmem.readPktSize::3 14 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 169361 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 4381 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 124324 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 159846 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 9630 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 301 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1816 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2607 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5988 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6261 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6563 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6237 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6589 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6896 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 7686 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 7433 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 8575 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 9015 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 7444 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 6965 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 7063 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 6763 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6551 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 6616 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 505 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 478 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 255 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 298 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 296 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 266 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 262 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 267 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 278 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 351 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 215 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 210 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 195 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 213 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 220 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 178 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 208 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 164 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 179 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 244 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 124 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 201 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 238 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 159 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 74 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 166 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 60346 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 312.418122 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 185.510807 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 328.995418 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 21664 35.90% 35.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 14701 24.36% 60.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6745 11.18% 71.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3562 5.90% 77.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2510 4.16% 81.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1679 2.78% 84.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1014 1.68% 85.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1006 1.67% 87.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7465 12.37% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 60346 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6177 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 27.486158 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 583.334644 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6176 99.98% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6177 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6177 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.202687 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.306581 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 15.265718 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5466 88.49% 88.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 67 1.08% 89.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 30 0.49% 90.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 47 0.76% 90.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 264 4.27% 95.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 28 0.45% 95.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 18 0.29% 95.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 6 0.10% 95.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 9 0.15% 96.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 7 0.11% 96.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 4 0.06% 96.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 7 0.11% 96.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 143 2.32% 98.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 4 0.06% 98.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 1 0.02% 98.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 7 0.11% 98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 5 0.08% 98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 1 0.02% 98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 1 0.02% 99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 1 0.02% 99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 11 0.18% 99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 2 0.03% 99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 3 0.05% 99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 3 0.05% 99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 14 0.23% 99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 3 0.05% 99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 4 0.06% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 4 0.06% 99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 1 0.02% 99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.02% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 1 0.02% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171 1 0.02% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 5 0.08% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183 1 0.02% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191 2 0.03% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 4 0.06% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6177 # Writes before turning the bus around for reads
-system.physmem.totQLat 4574555750 # Total ticks spent queuing
-system.physmem.totMemAccLat 7758118250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 848950000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 26942.43 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 45692.43 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.05 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.37 # Average write queue length when enqueuing
-system.physmem.readRowHits 140247 # Number of row buffer hits during reads
-system.physmem.writeRowHits 93988 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.60 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.30 # Row buffer hit rate for writes
-system.physmem.avgGap 9560361.83 # Average gap between requests
-system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 217834260 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 115781655 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 617124480 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 324250740 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 6010564560.000001 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 4580096490 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 375795840 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 12507827490 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 8401113600 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 671912403285 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 705065679060 # Total energy per rank (pJ)
-system.physmem_0.averagePower 246.963017 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 2843582682250 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 706056250 # Time in different power states
-system.physmem_0.memoryStateTime::REF 2555890000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 2794607920750 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 21877952250 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 7767045000 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 27429516250 # Time in different power states
-system.physmem_1.actEnergy 213043320 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 113231415 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 595176120 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 327163500 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 6093540960.000001 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 4507043580 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 367350240 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 12209497470 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 8677272480 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 672029778480 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 705136507095 # Total energy per rank (pJ)
-system.physmem_1.averagePower 246.987826 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 2844096160000 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 691055750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 2591938000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 2794723975250 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 22596980000 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 7565161250 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 26775270250 # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 31068063 # Number of BP lookups
-system.cpu.branchPred.condPredicted 16834819 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2474290 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 18684214 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 10413110 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 55.732128 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 7904720 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1504932 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 3038151 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 2849063 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 189088 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 109706 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 67808 # Table walker walks requested
-system.cpu.dtb.walker.walksShort 67808 # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44545 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23263 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples 67808 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 67808 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 67808 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 7897 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 10074.838546 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 8443.809763 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 7240.808120 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-16383 7014 88.82% 88.82% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::16384-32767 876 11.09% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::81920-98303 5 0.06% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::245760-262143 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 7897 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 276581000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0 276581000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 276581000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 6507 82.40% 82.40% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M 1390 17.60% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 7897 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 67808 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 67808 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7897 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7897 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 75705 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 24693754 # DTB read hits
-system.cpu.dtb.read_misses 60831 # DTB read misses
-system.cpu.dtb.write_hits 19411318 # DTB write hits
-system.cpu.dtb.write_misses 6977 # DTB write misses
-system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4277 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 1491 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 1775 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 779 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 24754585 # DTB read accesses
-system.cpu.dtb.write_accesses 19418295 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 44105072 # DTB hits
-system.cpu.dtb.misses 67808 # DTB misses
-system.cpu.dtb.accesses 44172880 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 5860 # Table walker walks requested
-system.cpu.itb.walker.walksShort 5860 # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1 319 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2 5541 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples 5860 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 5860 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 5860 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 3216 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 10484.452736 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 8664.992606 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 6927.635793 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-8191 1845 57.37% 57.37% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::8192-16383 815 25.34% 82.71% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-24575 549 17.07% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::24576-32767 6 0.19% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 3216 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 276141500 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 276141500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 276141500 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 2906 90.36% 90.36% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M 310 9.64% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 3216 # Table walker page sizes translated
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5860 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 5860 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3216 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 3216 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 9076 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 57505769 # ITB inst hits
-system.cpu.itb.inst_misses 5860 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2934 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 8328 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 57511629 # ITB inst accesses
-system.cpu.itb.hits 57505769 # DTB hits
-system.cpu.itb.misses 5860 # DTB misses
-system.cpu.itb.accesses 57511629 # DTB accesses
-system.cpu.numPwrStateTransitions 6066 # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean 887942089.664688 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev 17437807884.014717 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 499966671100 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON 161816022547 # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 2693128357953 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 323634999 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 111803105 # Number of instructions committed
-system.cpu.committedOps 135177203 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 7783284 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles 5386318328 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi 2.894687 # CPI: cycles per instruction
-system.cpu.ipc 0.345460 # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction
-system.cpu.op_class_0::IntAlu 90612203 67.03% 67.03% # Class of committed instruction
-system.cpu.op_class_0::IntMult 113141 0.08% 67.12% # Class of committed instruction
-system.cpu.op_class_0::IntDiv 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::FloatMult 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::FloatMisc 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdMult 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdShift 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc 8473 0.01% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.12% # Class of committed instruction
-system.cpu.op_class_0::MemRead 24199534 17.90% 85.03% # Class of committed instruction
-system.cpu.op_class_0::MemWrite 20230283 14.97% 99.99% # Class of committed instruction
-system.cpu.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction
-system.cpu.op_class_0::FloatMemWrite 8524 0.01% 100.00% # Class of committed instruction
-system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::total 135177203 # Class of committed instruction
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed
-system.cpu.tickCycles 217984467 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 105650532 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 844606 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.945154 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 42562338 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 845118 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 50.362598 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 330588500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.945154 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999893 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 175904316 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 175904316 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 23049763 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23049763 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18249075 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18249075 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 357182 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 357182 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 443419 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 443419 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 460030 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 460030 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 41298838 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 41298838 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 41656020 # number of overall hits
-system.cpu.dcache.overall_hits::total 41656020 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 464983 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 464983 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 548530 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 548530 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 169407 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 169407 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 22402 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 22402 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 1013513 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1013513 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1182920 # number of overall misses
-system.cpu.dcache.overall_misses::total 1182920 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 7335235000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 7335235000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 26749219979 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 26749219979 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 303724500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 303724500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 169000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 169000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 34084454979 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 34084454979 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 34084454979 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 34084454979 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 23514746 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 23514746 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 18797605 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 18797605 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 526589 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 526589 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465821 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 465821 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 460032 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 460032 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 42312351 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 42312351 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 42838940 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 42838940 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019774 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.019774 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029181 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.029181 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321706 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.321706 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048091 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048091 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.023953 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.023953 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.027613 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.027613 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15775.275655 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15775.275655 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48765.281715 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48765.281715 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13557.918936 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13557.918936 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 84500 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 84500 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 33630.012618 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 33630.012618 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 28813.829320 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 28813.829320 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 813 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.954545 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 701993 # number of writebacks
-system.cpu.dcache.writebacks::total 701993 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45638 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 45638 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249404 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 249404 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14200 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 14200 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 295042 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 295042 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 295042 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 295042 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419345 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 419345 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299126 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 299126 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121262 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 121262 # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8202 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 8202 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 718471 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 718471 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 839733 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 839733 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total 31130 # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6449852500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 6449852500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14240256000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 14240256000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1658671000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1658671000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118600500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118600500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 167000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 167000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20690108500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 20690108500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22348779500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 22348779500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6305317500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6305317500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6305317500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 6305317500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017833 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017833 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015913 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015913 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230278 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230278 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017608 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017608 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016980 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.016980 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019602 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.019602 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15380.778357 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15380.778357 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47606.212767 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47606.212767 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13678.407085 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13678.407085 # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14459.948793 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14459.948793 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 83500 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 83500 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28797.416319 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28797.416319 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26614.149378 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26614.149378 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202547.944105 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202547.944105 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107390.358347 # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107390.358347 # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 2890432 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.371135 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 54606166 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 2890944 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 18.888697 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 16096310500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.371135 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.998772 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.998772 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 60388077 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 60388077 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 54606166 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 54606166 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 54606166 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 54606166 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 54606166 # number of overall hits
-system.cpu.icache.overall_hits::total 54606166 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 2890956 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 2890956 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 2890956 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 2890956 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 2890956 # number of overall misses
-system.cpu.icache.overall_misses::total 2890956 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 39801907000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 39801907000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 39801907000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 39801907000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 39801907000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 39801907000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 57497122 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 57497122 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 57497122 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 57497122 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 57497122 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 57497122 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050280 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.050280 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.050280 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.050280 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.050280 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.050280 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13767.731851 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13767.731851 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13767.731851 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13767.731851 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13767.731851 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13767.731851 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks 2890432 # number of writebacks
-system.cpu.icache.writebacks::total 2890432 # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2890956 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 2890956 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 2890956 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 2890956 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 2890956 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 2890956 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3119 # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total 3119 # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3119 # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total 3119 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36910952000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 36910952000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36910952000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 36910952000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36910952000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 36910952000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 265216500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 265216500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 265216500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total 265216500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050280 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050280 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050280 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.050280 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050280 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.050280 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12767.732197 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12767.732197 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12767.732197 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12767.732197 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12767.732197 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12767.732197 # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85032.542482 # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85032.542482 # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85032.542482 # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85032.542482 # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 96713 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 65145.108369 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 7318914 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 162108 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 45.148383 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 100163301000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 70.225039 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.032952 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 12109.105789 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 52965.744589 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001072 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.184770 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.808193 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.994035 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 65349 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4 45 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4579 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60686 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000702 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997147 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 60066606 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 60066606 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68164 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3376 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 71540 # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks 701993 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 701993 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 2839731 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 2839731 # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 2785 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 2785 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 167030 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 167030 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2867992 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 2867992 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 534347 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 534347 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 68164 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 3376 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 2867992 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 701377 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 3640909 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 68164 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 3376 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 2867992 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 701377 # number of overall hits
-system.cpu.l2cache.overall_hits::total 3640909 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 106 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 108 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 129309 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 129309 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22923 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 22923 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14458 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 14458 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 106 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 22923 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 143767 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 166798 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 106 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 22923 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 143767 # number of overall misses
-system.cpu.l2cache.overall_misses::total 166798 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 35537000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 193500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 35730500 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 172000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 172000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 164000 # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total 164000 # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12000174000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 12000174000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2393515000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 2393515000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1752753500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 1752753500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 35537000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 193500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 2393515000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 13752927500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 16182173000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 35537000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 193500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 2393515000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 13752927500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 16182173000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68270 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3378 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 71648 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 701993 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 701993 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks 2839731 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 2839731 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2791 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 2791 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 296339 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 296339 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2890915 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 2890915 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548805 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 548805 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68270 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 3378 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 2890915 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 845144 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 3807707 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68270 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 3378 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 2890915 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 845144 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 3807707 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001553 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000592 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.001507 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002150 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002150 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436355 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.436355 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007929 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007929 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026345 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026345 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001553 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000592 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007929 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.170109 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.043805 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001553 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000592 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007929 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.170109 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.043805 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 335254.716981 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 96750 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 330837.962963 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 28666.666667 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 28666.666667 # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82000 # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82000 # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92802.310744 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92802.310744 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 104415.434280 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 104415.434280 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121230.702725 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121230.702725 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 335254.716981 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 96750 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 104415.434280 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95661.226151 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 97016.588928 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 335254.716981 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 96750 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 104415.434280 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95661.226151 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 97016.588928 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks 88134 # number of writebacks
-system.cpu.l2cache.writebacks::total 88134 # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 15 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total 15 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 143 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total 143 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 143 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 158 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 143 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 158 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 106 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 108 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129309 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 129309 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22908 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22908 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14315 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14315 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 106 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 22908 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 143624 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 166640 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 106 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 22908 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 143624 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 166640 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3119 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34249 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3119 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61833 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 34477000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 173500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34650500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 112000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 112000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 144000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 144000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10707084000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10707084000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2162492500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2162492500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1597831000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1597831000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 34477000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 173500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2162492500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12304915000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 14502058000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 34477000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 173500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2162492500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12304915000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 14502058000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 216819500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5916117000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6132936500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 216819500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5916117000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6132936500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001553 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000592 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001507 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002150 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002150 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436355 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436355 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007924 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007924 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026084 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026084 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001553 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000592 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007924 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169940 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.043764 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001553 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000592 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007924 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169940 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.043764 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 325254.716981 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 86750 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 320837.962963 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18666.666667 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18666.666667 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82802.310744 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82802.310744 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 94399.009080 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 94399.009080 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 111619.350332 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 111619.350332 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 325254.716981 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 86750 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 94399.009080 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85674.504261 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87026.272204 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 325254.716981 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 86750 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 94399.009080 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85674.504261 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87026.272204 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190045.518792 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179069.067710 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100761.607112 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99185.491566 # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 7504755 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768676 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58052 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 184 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 184 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq 136721 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 3576628 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 790127 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 2890432 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 151192 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2791 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2793 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 296339 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 296339 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 2890956 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 549028 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 4410 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp 13 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8678540 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2658068 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14779 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159341 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 11510728 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370205760 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99209257 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13512 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 273080 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 469701609 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 132371 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 5775904 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 4004544 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.022245 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.147479 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 3915463 97.78% 97.78% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 89081 2.22% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 4004544 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 7425335000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 287877 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 4341709800 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1314266535 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 11403994 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 91100441 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 46325500 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 623000 # Layer occupancy (ticks)
-system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6084500 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 39097500 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 187729822 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 36424 # number of replacements
-system.iocache.tags.tagsinuse 1.033985 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 272037045000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 1.033985 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.064624 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.064624 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 328122 # Number of tag accesses
-system.iocache.tags.data_accesses 328122 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
-system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses
-system.iocache.demand_misses::total 36458 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide 36458 # number of overall misses
-system.iocache.overall_misses::total 36458 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 37405377 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 37405377 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 4361655445 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 4361655445 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 4399060822 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 4399060822 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 4399060822 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 4399060822 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 159852.038462 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 159852.038462 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120407.891039 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 120407.891039 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 120661.057162 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 120661.057162 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 120661.057162 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 120661.057162 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 36190 # number of writebacks
-system.iocache.writebacks::total 36190 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 25705377 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 25705377 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2548589823 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 2548589823 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 2574295200 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 2574295200 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 2574295200 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 2574295200 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 109852.038462 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 109852.038462 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70356.388665 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70356.388665 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 70609.885348 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70609.885348 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 70609.885348 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70609.885348 # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests 336307 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 137733 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 538 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 34249 # Transaction distribution
-system.membus.trans_dist::ReadResp 71814 # Transaction distribution
-system.membus.trans_dist::WriteReq 27584 # Transaction distribution
-system.membus.trans_dist::WriteResp 27584 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 124324 # Transaction distribution
-system.membus.trans_dist::CleanEvict 8813 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 128 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::ReadExReq 129187 # Transaction distribution
-system.membus.trans_dist::ReadExResp 129187 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 37565 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 4361 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445694 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553262 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 626159 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16498528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16662313 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 18979433 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 4865 # Total snoops (count)
-system.membus.snoopTraffic 32128 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 264939 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.018563 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.134975 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 260021 98.14% 98.14% # Request fanout histogram
-system.membus.snoop_fanout::1 4918 1.86% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 264939 # Request fanout histogram
-system.membus.reqLayer0.occupancy 92843000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 8000 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1694500 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 903707925 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 987836250 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 5807414 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
+sim_seconds 2.854928
+sim_ticks 2854927627500
+final_tick 2854927627500
+sim_freq 1000000000000
+host_inst_rate 259896
+host_op_rate 314233
+host_tick_rate 6638397944
+host_mem_usage 597276
+host_seconds 430.06
+sim_insts 111771703
+sim_ops 135139786
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.physmem.bytes_read::cpu.dtb.walker 6976
+system.physmem.bytes_read::cpu.itb.walker 128
+system.physmem.bytes_read::cpu.inst 1665856
+system.physmem.bytes_read::cpu.data 9168876
+system.physmem.bytes_read::realview.ide 960
+system.physmem.bytes_read::total 10842796
+system.physmem.bytes_inst_read::cpu.inst 1665856
+system.physmem.bytes_inst_read::total 1665856
+system.physmem.bytes_written::writebacks 7956992
+system.physmem.bytes_written::cpu.data 17524
+system.physmem.bytes_written::total 7974516
+system.physmem.num_reads::cpu.dtb.walker 109
+system.physmem.num_reads::cpu.itb.walker 2
+system.physmem.num_reads::cpu.inst 26029
+system.physmem.num_reads::cpu.data 143785
+system.physmem.num_reads::realview.ide 15
+system.physmem.num_reads::total 169940
+system.physmem.num_writes::writebacks 124328
+system.physmem.num_writes::cpu.data 4381
+system.physmem.num_writes::total 128709
+system.physmem.bw_read::cpu.dtb.walker 2443
+system.physmem.bw_read::cpu.itb.walker 45
+system.physmem.bw_read::cpu.inst 583502
+system.physmem.bw_read::cpu.data 3211597
+system.physmem.bw_read::realview.ide 336
+system.physmem.bw_read::total 3797923
+system.physmem.bw_inst_read::cpu.inst 583502
+system.physmem.bw_inst_read::total 583502
+system.physmem.bw_write::writebacks 2787108
+system.physmem.bw_write::cpu.data 6138
+system.physmem.bw_write::total 2793246
+system.physmem.bw_total::writebacks 2787108
+system.physmem.bw_total::cpu.dtb.walker 2443
+system.physmem.bw_total::cpu.itb.walker 45
+system.physmem.bw_total::cpu.inst 583502
+system.physmem.bw_total::cpu.data 3217735
+system.physmem.bw_total::realview.ide 336
+system.physmem.bw_total::total 6591170
+system.physmem.readReqs 169940
+system.physmem.writeReqs 128709
+system.physmem.readBursts 169940
+system.physmem.writeBursts 128709
+system.physmem.bytesReadDRAM 10867392
+system.physmem.bytesReadWrQ 8768
+system.physmem.bytesWritten 7987136
+system.physmem.bytesReadSys 10842796
+system.physmem.bytesWrittenSys 7974516
+system.physmem.servicedByWrQ 137
+system.physmem.mergedWrBursts 3888
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 10681
+system.physmem.perBankRdBursts::1 10442
+system.physmem.perBankRdBursts::2 10751
+system.physmem.perBankRdBursts::3 10388
+system.physmem.perBankRdBursts::4 13039
+system.physmem.perBankRdBursts::5 10185
+system.physmem.perBankRdBursts::6 10269
+system.physmem.perBankRdBursts::7 10713
+system.physmem.perBankRdBursts::8 10427
+system.physmem.perBankRdBursts::9 10646
+system.physmem.perBankRdBursts::10 10209
+system.physmem.perBankRdBursts::11 9539
+system.physmem.perBankRdBursts::12 10748
+system.physmem.perBankRdBursts::13 11527
+system.physmem.perBankRdBursts::14 10187
+system.physmem.perBankRdBursts::15 10052
+system.physmem.perBankWrBursts::0 7942
+system.physmem.perBankWrBursts::1 7866
+system.physmem.perBankWrBursts::2 8424
+system.physmem.perBankWrBursts::3 7907
+system.physmem.perBankWrBursts::4 7304
+system.physmem.perBankWrBursts::5 7363
+system.physmem.perBankWrBursts::6 7424
+system.physmem.perBankWrBursts::7 7906
+system.physmem.perBankWrBursts::8 7951
+system.physmem.perBankWrBursts::9 8140
+system.physmem.perBankWrBursts::10 7603
+system.physmem.perBankWrBursts::11 7336
+system.physmem.perBankWrBursts::12 8128
+system.physmem.perBankWrBursts::13 8674
+system.physmem.perBankWrBursts::14 7494
+system.physmem.perBankWrBursts::15 7337
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 63
+system.physmem.totGap 2854927178000
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 543
+system.physmem.readPktSize::3 14
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 169383
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 4381
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 124328
+system.physmem.rdQLenPdf::0 159867
+system.physmem.rdQLenPdf::1 9622
+system.physmem.rdQLenPdf::2 302
+system.physmem.rdQLenPdf::3 1
+system.physmem.rdQLenPdf::4 1
+system.physmem.rdQLenPdf::5 1
+system.physmem.rdQLenPdf::6 1
+system.physmem.rdQLenPdf::7 1
+system.physmem.rdQLenPdf::8 1
+system.physmem.rdQLenPdf::9 1
+system.physmem.rdQLenPdf::10 1
+system.physmem.rdQLenPdf::11 1
+system.physmem.rdQLenPdf::12 1
+system.physmem.rdQLenPdf::13 1
+system.physmem.rdQLenPdf::14 1
+system.physmem.rdQLenPdf::15 0
+system.physmem.rdQLenPdf::16 0
+system.physmem.rdQLenPdf::17 0
+system.physmem.rdQLenPdf::18 0
+system.physmem.rdQLenPdf::19 0
+system.physmem.rdQLenPdf::20 0
+system.physmem.rdQLenPdf::21 0
+system.physmem.rdQLenPdf::22 0
+system.physmem.rdQLenPdf::23 0
+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
+system.physmem.rdQLenPdf::26 0
+system.physmem.rdQLenPdf::27 0
+system.physmem.rdQLenPdf::28 0
+system.physmem.rdQLenPdf::29 0
+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 1
+system.physmem.wrQLenPdf::1 1
+system.physmem.wrQLenPdf::2 1
+system.physmem.wrQLenPdf::3 1
+system.physmem.wrQLenPdf::4 1
+system.physmem.wrQLenPdf::5 1
+system.physmem.wrQLenPdf::6 1
+system.physmem.wrQLenPdf::7 1
+system.physmem.wrQLenPdf::8 1
+system.physmem.wrQLenPdf::9 1
+system.physmem.wrQLenPdf::10 1
+system.physmem.wrQLenPdf::11 1
+system.physmem.wrQLenPdf::12 1
+system.physmem.wrQLenPdf::13 1
+system.physmem.wrQLenPdf::14 1
+system.physmem.wrQLenPdf::15 1807
+system.physmem.wrQLenPdf::16 2634
+system.physmem.wrQLenPdf::17 5993
+system.physmem.wrQLenPdf::18 6240
+system.physmem.wrQLenPdf::19 6528
+system.physmem.wrQLenPdf::20 6224
+system.physmem.wrQLenPdf::21 6599
+system.physmem.wrQLenPdf::22 6844
+system.physmem.wrQLenPdf::23 7638
+system.physmem.wrQLenPdf::24 7446
+system.physmem.wrQLenPdf::25 8542
+system.physmem.wrQLenPdf::26 8952
+system.physmem.wrQLenPdf::27 7381
+system.physmem.wrQLenPdf::28 7006
+system.physmem.wrQLenPdf::29 7076
+system.physmem.wrQLenPdf::30 6795
+system.physmem.wrQLenPdf::31 6597
+system.physmem.wrQLenPdf::32 6634
+system.physmem.wrQLenPdf::33 523
+system.physmem.wrQLenPdf::34 519
+system.physmem.wrQLenPdf::35 465
+system.physmem.wrQLenPdf::36 320
+system.physmem.wrQLenPdf::37 323
+system.physmem.wrQLenPdf::38 337
+system.physmem.wrQLenPdf::39 278
+system.physmem.wrQLenPdf::40 262
+system.physmem.wrQLenPdf::41 254
+system.physmem.wrQLenPdf::42 262
+system.physmem.wrQLenPdf::43 262
+system.physmem.wrQLenPdf::44 318
+system.physmem.wrQLenPdf::45 228
+system.physmem.wrQLenPdf::46 233
+system.physmem.wrQLenPdf::47 215
+system.physmem.wrQLenPdf::48 201
+system.physmem.wrQLenPdf::49 203
+system.physmem.wrQLenPdf::50 208
+system.physmem.wrQLenPdf::51 161
+system.physmem.wrQLenPdf::52 244
+system.physmem.wrQLenPdf::53 193
+system.physmem.wrQLenPdf::54 194
+system.physmem.wrQLenPdf::55 175
+system.physmem.wrQLenPdf::56 236
+system.physmem.wrQLenPdf::57 244
+system.physmem.wrQLenPdf::58 125
+system.physmem.wrQLenPdf::59 254
+system.physmem.wrQLenPdf::60 211
+system.physmem.wrQLenPdf::61 185
+system.physmem.wrQLenPdf::62 90
+system.physmem.wrQLenPdf::63 147
+system.physmem.bytesPerActivate::samples 60375
+system.physmem.bytesPerActivate::mean 312.289259
+system.physmem.bytesPerActivate::gmean 185.250729
+system.physmem.bytesPerActivate::stdev 329.192831
+system.physmem.bytesPerActivate::0-127 21750 36.02% 36.02%
+system.physmem.bytesPerActivate::128-255 14686 24.32% 60.35%
+system.physmem.bytesPerActivate::256-383 6697 11.09% 71.44%
+system.physmem.bytesPerActivate::384-511 3542 5.87% 77.31%
+system.physmem.bytesPerActivate::512-639 2540 4.21% 81.52%
+system.physmem.bytesPerActivate::640-767 1648 2.73% 84.25%
+system.physmem.bytesPerActivate::768-895 1031 1.71% 85.95%
+system.physmem.bytesPerActivate::896-1023 1005 1.66% 87.62%
+system.physmem.bytesPerActivate::1024-1151 7476 12.38% 100.00%
+system.physmem.bytesPerActivate::total 60375
+system.physmem.rdPerTurnAround::samples 6174
+system.physmem.rdPerTurnAround::mean 27.501944
+system.physmem.rdPerTurnAround::stdev 583.476919
+system.physmem.rdPerTurnAround::0-2047 6173 99.98% 99.98%
+system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00%
+system.physmem.rdPerTurnAround::total 6174
+system.physmem.wrPerTurnAround::samples 6174
+system.physmem.wrPerTurnAround::mean 20.213638
+system.physmem.wrPerTurnAround::gmean 18.315719
+system.physmem.wrPerTurnAround::stdev 15.257991
+system.physmem.wrPerTurnAround::16-19 5458 88.40% 88.40%
+system.physmem.wrPerTurnAround::20-23 62 1.00% 89.41%
+system.physmem.wrPerTurnAround::24-27 37 0.60% 90.01%
+system.physmem.wrPerTurnAround::28-31 45 0.73% 90.74%
+system.physmem.wrPerTurnAround::32-35 268 4.34% 95.08%
+system.physmem.wrPerTurnAround::36-39 28 0.45% 95.53%
+system.physmem.wrPerTurnAround::40-43 16 0.26% 95.79%
+system.physmem.wrPerTurnAround::44-47 14 0.23% 96.02%
+system.physmem.wrPerTurnAround::48-51 9 0.15% 96.16%
+system.physmem.wrPerTurnAround::52-55 2 0.03% 96.19%
+system.physmem.wrPerTurnAround::56-59 2 0.03% 96.23%
+system.physmem.wrPerTurnAround::60-63 4 0.06% 96.29%
+system.physmem.wrPerTurnAround::64-67 146 2.36% 98.66%
+system.physmem.wrPerTurnAround::68-71 7 0.11% 98.77%
+system.physmem.wrPerTurnAround::76-79 8 0.13% 98.90%
+system.physmem.wrPerTurnAround::80-83 6 0.10% 99.00%
+system.physmem.wrPerTurnAround::84-87 1 0.02% 99.01%
+system.physmem.wrPerTurnAround::92-95 1 0.02% 99.03%
+system.physmem.wrPerTurnAround::104-107 3 0.05% 99.08%
+system.physmem.wrPerTurnAround::108-111 8 0.13% 99.21%
+system.physmem.wrPerTurnAround::112-115 1 0.02% 99.22%
+system.physmem.wrPerTurnAround::120-123 1 0.02% 99.24%
+system.physmem.wrPerTurnAround::124-127 1 0.02% 99.25%
+system.physmem.wrPerTurnAround::128-131 10 0.16% 99.42%
+system.physmem.wrPerTurnAround::132-135 7 0.11% 99.53%
+system.physmem.wrPerTurnAround::136-139 7 0.11% 99.64%
+system.physmem.wrPerTurnAround::140-143 4 0.06% 99.71%
+system.physmem.wrPerTurnAround::144-147 3 0.05% 99.76%
+system.physmem.wrPerTurnAround::152-155 1 0.02% 99.77%
+system.physmem.wrPerTurnAround::156-159 2 0.03% 99.81%
+system.physmem.wrPerTurnAround::168-171 1 0.02% 99.82%
+system.physmem.wrPerTurnAround::172-175 2 0.03% 99.85%
+system.physmem.wrPerTurnAround::176-179 1 0.02% 99.87%
+system.physmem.wrPerTurnAround::180-183 1 0.02% 99.89%
+system.physmem.wrPerTurnAround::188-191 1 0.02% 99.90%
+system.physmem.wrPerTurnAround::192-195 5 0.08% 99.98%
+system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00%
+system.physmem.wrPerTurnAround::total 6174
+system.physmem.totQLat 4595611500
+system.physmem.totMemAccLat 7779417750
+system.physmem.totBusLat 849015000
+system.physmem.avgQLat 27064.37
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 45814.37
+system.physmem.avgRdBW 3.81
+system.physmem.avgWrBW 2.80
+system.physmem.avgRdBWSys 3.80
+system.physmem.avgWrBWSys 2.79
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 0.05
+system.physmem.busUtilRead 0.03
+system.physmem.busUtilWrite 0.02
+system.physmem.avgRdQLen 1.01
+system.physmem.avgWrQLen 27.80
+system.physmem.readRowHits 140227
+system.physmem.writeRowHits 93999
+system.physmem.readRowHitRate 82.58
+system.physmem.writeRowHitRate 75.31
+system.physmem.avgGap 9559473.42
+system.physmem.pageHitRate 79.50
+system.physmem_0.actEnergy 217969920
+system.physmem_0.preEnergy 115853760
+system.physmem_0.readEnergy 617381520
+system.physmem_0.writeEnergy 324349920
+system.physmem_0.refreshEnergy 6032076960.000001
+system.physmem_0.actBackEnergy 4594766580
+system.physmem_0.preBackEnergy 373267680
+system.physmem_0.actPowerDownEnergy 12534119310
+system.physmem_0.prePowerDownEnergy 8428819680
+system.physmem_0.selfRefreshEnergy 671880069150
+system.physmem_0.totalEnergy 705122067060
+system.physmem_0.averagePower 246.984218
+system.physmem_0.totalIdleTime 2843538521500
+system.physmem_0.memoryStateTime::IDLE 699213750
+system.physmem_0.memoryStateTime::REF 2565056000
+system.physmem_0.memoryStateTime::SREF 2794434653000
+system.physmem_0.memoryStateTime::PRE_PDN 21950094250
+system.physmem_0.memoryStateTime::ACT 7791322250
+system.physmem_0.memoryStateTime::ACT_PDN 27487288250
+system.physmem_1.actEnergy 213114720
+system.physmem_1.preEnergy 113269365
+system.physmem_1.readEnergy 595011900
+system.physmem_1.writeEnergy 327100860
+system.physmem_1.refreshEnergy 6107677680.000001
+system.physmem_1.actBackEnergy 4499395890
+system.physmem_1.preBackEnergy 364524960
+system.physmem_1.actPowerDownEnergy 12239824890
+system.physmem_1.prePowerDownEnergy 8713020000
+system.physmem_1.selfRefreshEnergy 671996557920
+system.physmem_1.totalEnergy 705172962825
+system.physmem_1.averagePower 247.002045
+system.physmem_1.totalIdleTime 2844103397000
+system.physmem_1.memoryStateTime::IDLE 682111750
+system.physmem_1.memoryStateTime::REF 2597942000
+system.physmem_1.memoryStateTime::SREF 2794571640750
+system.physmem_1.memoryStateTime::PRE_PDN 22690140250
+system.physmem_1.memoryStateTime::ACT 7544112250
+system.physmem_1.memoryStateTime::ACT_PDN 26841680500
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.nvmem.bytes_read::cpu.inst 512
+system.realview.nvmem.bytes_read::total 512
+system.realview.nvmem.bytes_inst_read::cpu.inst 512
+system.realview.nvmem.bytes_inst_read::total 512
+system.realview.nvmem.num_reads::cpu.inst 8
+system.realview.nvmem.num_reads::total 8
+system.realview.nvmem.bw_read::cpu.inst 179
+system.realview.nvmem.bw_read::total 179
+system.realview.nvmem.bw_inst_read::cpu.inst 179
+system.realview.nvmem.bw_inst_read::total 179
+system.realview.nvmem.bw_total::cpu.inst 179
+system.realview.nvmem.bw_total::total 179
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.cf0.dma_read_full_pages 0
+system.cf0.dma_read_bytes 1024
+system.cf0.dma_read_txs 1
+system.cf0.dma_write_full_pages 540
+system.cf0.dma_write_bytes 2318336
+system.cf0.dma_write_txs 631
+system.cpu.branchPred.lookups 31061880
+system.cpu.branchPred.condPredicted 16830353
+system.cpu.branchPred.condIncorrect 2474418
+system.cpu.branchPred.BTBLookups 18693305
+system.cpu.branchPred.BTBHits 10411167
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 55.694630
+system.cpu.branchPred.usedRAS 7903109
+system.cpu.branchPred.RASInCorrect 1504989
+system.cpu.branchPred.indirectLookups 3038231
+system.cpu.branchPred.indirectHits 2848867
+system.cpu.branchPred.indirectMisses 189364
+system.cpu.branchPredindirectMispredicted 109645
+system.cpu_clk_domain.clock 500
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.hits 0
+system.cpu.dstage2_mmu.stage2_tlb.misses 0
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.cpu.dtb.walker.walks 67659
+system.cpu.dtb.walker.walksShort 67659
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44567
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23092
+system.cpu.dtb.walker.walkWaitTime::samples 67659
+system.cpu.dtb.walker.walkWaitTime::0 67659 100.00% 100.00%
+system.cpu.dtb.walker.walkWaitTime::total 67659
+system.cpu.dtb.walker.walkCompletionTime::samples 7871
+system.cpu.dtb.walker.walkCompletionTime::mean 10125.206454
+system.cpu.dtb.walker.walkCompletionTime::gmean 8429.942657
+system.cpu.dtb.walker.walkCompletionTime::stdev 9907.051248
+system.cpu.dtb.walker.walkCompletionTime::0-65535 7864 99.91% 99.91%
+system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.05% 99.96%
+system.cpu.dtb.walker.walkCompletionTime::196608-262143 2 0.03% 99.99%
+system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00%
+system.cpu.dtb.walker.walkCompletionTime::total 7871
+system.cpu.dtb.walker.walksPending::samples 276581000
+system.cpu.dtb.walker.walksPending::0 276581000 100.00% 100.00%
+system.cpu.dtb.walker.walksPending::total 276581000
+system.cpu.dtb.walker.walkPageSizes::4K 6485 82.39% 82.39%
+system.cpu.dtb.walker.walkPageSizes::1M 1386 17.61% 100.00%
+system.cpu.dtb.walker.walkPageSizes::total 7871
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 67659
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 67659
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7871
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7871
+system.cpu.dtb.walker.walkRequestOrigin::total 75530
+system.cpu.dtb.inst_hits 0
+system.cpu.dtb.inst_misses 0
+system.cpu.dtb.read_hits 24684864
+system.cpu.dtb.read_misses 60689
+system.cpu.dtb.write_hits 19405463
+system.cpu.dtb.write_misses 6970
+system.cpu.dtb.flush_tlb 64
+system.cpu.dtb.flush_tlb_mva 917
+system.cpu.dtb.flush_tlb_mva_asid 0
+system.cpu.dtb.flush_tlb_asid 0
+system.cpu.dtb.flush_entries 4278
+system.cpu.dtb.align_faults 1498
+system.cpu.dtb.prefetch_faults 1782
+system.cpu.dtb.domain_faults 0
+system.cpu.dtb.perms_faults 765
+system.cpu.dtb.read_accesses 24745553
+system.cpu.dtb.write_accesses 19412433
+system.cpu.dtb.inst_accesses 0
+system.cpu.dtb.hits 44090327
+system.cpu.dtb.misses 67659
+system.cpu.dtb.accesses 44157986
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.hits 0
+system.cpu.istage2_mmu.stage2_tlb.misses 0
+system.cpu.istage2_mmu.stage2_tlb.accesses 0
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.cpu.itb.walker.walks 5834
+system.cpu.itb.walker.walksShort 5834
+system.cpu.itb.walker.walksShortTerminationLevel::Level1 322
+system.cpu.itb.walker.walksShortTerminationLevel::Level2 5512
+system.cpu.itb.walker.walkWaitTime::samples 5834
+system.cpu.itb.walker.walkWaitTime::0 5834 100.00% 100.00%
+system.cpu.itb.walker.walkWaitTime::total 5834
+system.cpu.itb.walker.walkCompletionTime::samples 3212
+system.cpu.itb.walker.walkCompletionTime::mean 10503.424658
+system.cpu.itb.walker.walkCompletionTime::gmean 8675.185995
+system.cpu.itb.walker.walkCompletionTime::stdev 6953.542108
+system.cpu.itb.walker.walkCompletionTime::0-8191 1846 57.47% 57.47%
+system.cpu.itb.walker.walkCompletionTime::8192-16383 802 24.97% 82.44%
+system.cpu.itb.walker.walkCompletionTime::16384-24575 556 17.31% 99.75%
+system.cpu.itb.walker.walkCompletionTime::24576-32767 7 0.22% 99.97%
+system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00%
+system.cpu.itb.walker.walkCompletionTime::total 3212
+system.cpu.itb.walker.walksPending::samples 276141500
+system.cpu.itb.walker.walksPending::0 276141500 100.00% 100.00%
+system.cpu.itb.walker.walksPending::total 276141500
+system.cpu.itb.walker.walkPageSizes::4K 2902 90.35% 90.35%
+system.cpu.itb.walker.walkPageSizes::1M 310 9.65% 100.00%
+system.cpu.itb.walker.walkPageSizes::total 3212
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5834
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 5834
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3212
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 3212
+system.cpu.itb.walker.walkRequestOrigin::total 9046
+system.cpu.itb.inst_hits 57493677
+system.cpu.itb.inst_misses 5834
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.flush_tlb 64
+system.cpu.itb.flush_tlb_mva 917
+system.cpu.itb.flush_tlb_mva_asid 0
+system.cpu.itb.flush_tlb_asid 0
+system.cpu.itb.flush_entries 2927
+system.cpu.itb.align_faults 0
+system.cpu.itb.prefetch_faults 0
+system.cpu.itb.domain_faults 0
+system.cpu.itb.perms_faults 8355
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.inst_accesses 57499511
+system.cpu.itb.hits 57493677
+system.cpu.itb.misses 5834
+system.cpu.itb.accesses 57499511
+system.cpu.numPwrStateTransitions 6066
+system.cpu.pwrStateClkGateDist::samples 3033
+system.cpu.pwrStateClkGateDist::mean 887944417.634355
+system.cpu.pwrStateClkGateDist::stdev 17437789844.803165
+system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89%
+system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80%
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84%
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87%
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90%
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00%
+system.cpu.pwrStateClkGateDist::min_value 501
+system.cpu.pwrStateClkGateDist::max_value 499967984888
+system.cpu.pwrStateClkGateDist::total 3033
+system.cpu.pwrStateResidencyTicks::ON 161792208815
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2693135418685
+system.cpu.numCycles 323587374
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 111771703
+system.cpu.committedOps 135139786
+system.cpu.discardedOps 7780501
+system.cpu.numFetchSuspends 3033
+system.cpu.quiesceCycles 5386332607
+system.cpu.cpi 2.895074
+system.cpu.ipc 0.345414
+system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00%
+system.cpu.op_class_0::IntAlu 90588447 67.03% 67.03%
+system.cpu.op_class_0::IntMult 113124 0.08% 67.12%
+system.cpu.op_class_0::IntDiv 0 0.00% 67.12%
+system.cpu.op_class_0::FloatAdd 0 0.00% 67.12%
+system.cpu.op_class_0::FloatCmp 0 0.00% 67.12%
+system.cpu.op_class_0::FloatCvt 0 0.00% 67.12%
+system.cpu.op_class_0::FloatMult 0 0.00% 67.12%
+system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.12%
+system.cpu.op_class_0::FloatDiv 0 0.00% 67.12%
+system.cpu.op_class_0::FloatMisc 0 0.00% 67.12%
+system.cpu.op_class_0::FloatSqrt 0 0.00% 67.12%
+system.cpu.op_class_0::SimdAdd 0 0.00% 67.12%
+system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.12%
+system.cpu.op_class_0::SimdAlu 0 0.00% 67.12%
+system.cpu.op_class_0::SimdCmp 0 0.00% 67.12%
+system.cpu.op_class_0::SimdCvt 0 0.00% 67.12%
+system.cpu.op_class_0::SimdMisc 0 0.00% 67.12%
+system.cpu.op_class_0::SimdMult 0 0.00% 67.12%
+system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.12%
+system.cpu.op_class_0::SimdShift 0 0.00% 67.12%
+system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.12%
+system.cpu.op_class_0::SimdSqrt 0 0.00% 67.12%
+system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.12%
+system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.12%
+system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.12%
+system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.12%
+system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.12%
+system.cpu.op_class_0::SimdFloatMisc 8479 0.01% 67.12%
+system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.12%
+system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.12%
+system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.12%
+system.cpu.op_class_0::MemRead 24191569 17.90% 85.03%
+system.cpu.op_class_0::MemWrite 20224534 14.97% 99.99%
+system.cpu.op_class_0::FloatMemRead 2708 0.00% 99.99%
+system.cpu.op_class_0::FloatMemWrite 8588 0.01% 100.00%
+system.cpu.op_class_0::IprAccess 0 0.00% 100.00%
+system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class_0::total 135139786
+system.cpu.kern.inst.arm 0
+system.cpu.kern.inst.quiesce 3033
+system.cpu.tickCycles 217929622
+system.cpu.idleCycles 105657752
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.cpu.dcache.tags.replacements 844447
+system.cpu.dcache.tags.tagsinuse 511.945153
+system.cpu.dcache.tags.total_refs 42548483
+system.cpu.dcache.tags.sampled_refs 844959
+system.cpu.dcache.tags.avg_refs 50.355678
+system.cpu.dcache.tags.warmup_cycle 330588500
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.945153
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999893
+system.cpu.dcache.tags.occ_percent::total 0.999893
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 94
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 360
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 58
+system.cpu.dcache.tags.occ_task_id_percent::1024 1
+system.cpu.dcache.tags.tag_accesses 175848001
+system.cpu.dcache.tags.data_accesses 175848001
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.cpu.dcache.ReadReq_hits::cpu.data 23041668
+system.cpu.dcache.ReadReq_hits::total 23041668
+system.cpu.dcache.WriteReq_hits::cpu.data 18243760
+system.cpu.dcache.WriteReq_hits::total 18243760
+system.cpu.dcache.SoftPFReq_hits::cpu.data 357146
+system.cpu.dcache.SoftPFReq_hits::total 357146
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 443213
+system.cpu.dcache.LoadLockedReq_hits::total 443213
+system.cpu.dcache.StoreCondReq_hits::cpu.data 459828
+system.cpu.dcache.StoreCondReq_hits::total 459828
+system.cpu.dcache.demand_hits::cpu.data 41285428
+system.cpu.dcache.demand_hits::total 41285428
+system.cpu.dcache.overall_hits::cpu.data 41642574
+system.cpu.dcache.overall_hits::total 41642574
+system.cpu.dcache.ReadReq_misses::cpu.data 464854
+system.cpu.dcache.ReadReq_misses::total 464854
+system.cpu.dcache.WriteReq_misses::cpu.data 548525
+system.cpu.dcache.WriteReq_misses::total 548525
+system.cpu.dcache.SoftPFReq_misses::cpu.data 169352
+system.cpu.dcache.SoftPFReq_misses::total 169352
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 22406
+system.cpu.dcache.LoadLockedReq_misses::total 22406
+system.cpu.dcache.StoreCondReq_misses::cpu.data 2
+system.cpu.dcache.StoreCondReq_misses::total 2
+system.cpu.dcache.demand_misses::cpu.data 1013379
+system.cpu.dcache.demand_misses::total 1013379
+system.cpu.dcache.overall_misses::cpu.data 1182731
+system.cpu.dcache.overall_misses::total 1182731
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 7330473500
+system.cpu.dcache.ReadReq_miss_latency::total 7330473500
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 26773562480
+system.cpu.dcache.WriteReq_miss_latency::total 26773562480
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304848500
+system.cpu.dcache.LoadLockedReq_miss_latency::total 304848500
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 171000
+system.cpu.dcache.StoreCondReq_miss_latency::total 171000
+system.cpu.dcache.demand_miss_latency::cpu.data 34104035980
+system.cpu.dcache.demand_miss_latency::total 34104035980
+system.cpu.dcache.overall_miss_latency::cpu.data 34104035980
+system.cpu.dcache.overall_miss_latency::total 34104035980
+system.cpu.dcache.ReadReq_accesses::cpu.data 23506522
+system.cpu.dcache.ReadReq_accesses::total 23506522
+system.cpu.dcache.WriteReq_accesses::cpu.data 18792285
+system.cpu.dcache.WriteReq_accesses::total 18792285
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 526498
+system.cpu.dcache.SoftPFReq_accesses::total 526498
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465619
+system.cpu.dcache.LoadLockedReq_accesses::total 465619
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 459830
+system.cpu.dcache.StoreCondReq_accesses::total 459830
+system.cpu.dcache.demand_accesses::cpu.data 42298807
+system.cpu.dcache.demand_accesses::total 42298807
+system.cpu.dcache.overall_accesses::cpu.data 42825305
+system.cpu.dcache.overall_accesses::total 42825305
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019776
+system.cpu.dcache.ReadReq_miss_rate::total 0.019776
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029189
+system.cpu.dcache.WriteReq_miss_rate::total 0.029189
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321657
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.321657
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048121
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048121
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004
+system.cpu.dcache.demand_miss_rate::cpu.data 0.023958
+system.cpu.dcache.demand_miss_rate::total 0.023958
+system.cpu.dcache.overall_miss_rate::cpu.data 0.027618
+system.cpu.dcache.overall_miss_rate::total 0.027618
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15769.410396
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15769.410396
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48810.104334
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48810.104334
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13605.663662
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13605.663662
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 85500
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 85500
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33653.782030
+system.cpu.dcache.demand_avg_miss_latency::total 33653.782030
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28834.989512
+system.cpu.dcache.overall_avg_miss_latency::total 28834.989512
+system.cpu.dcache.blocked_cycles::no_mshrs 210
+system.cpu.dcache.blocked_cycles::no_targets 0
+system.cpu.dcache.blocked::no_mshrs 21
+system.cpu.dcache.blocked::no_targets 0
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 10
+system.cpu.dcache.avg_blocked_cycles::no_targets nan
+system.cpu.dcache.writebacks::writebacks 701832
+system.cpu.dcache.writebacks::total 701832
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45599
+system.cpu.dcache.ReadReq_mshr_hits::total 45599
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249413
+system.cpu.dcache.WriteReq_mshr_hits::total 249413
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14207
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 14207
+system.cpu.dcache.demand_mshr_hits::cpu.data 295012
+system.cpu.dcache.demand_mshr_hits::total 295012
+system.cpu.dcache.overall_mshr_hits::cpu.data 295012
+system.cpu.dcache.overall_mshr_hits::total 295012
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419255
+system.cpu.dcache.ReadReq_mshr_misses::total 419255
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299112
+system.cpu.dcache.WriteReq_mshr_misses::total 299112
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121209
+system.cpu.dcache.SoftPFReq_mshr_misses::total 121209
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8199
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 8199
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2
+system.cpu.dcache.StoreCondReq_mshr_misses::total 2
+system.cpu.dcache.demand_mshr_misses::cpu.data 718367
+system.cpu.dcache.demand_mshr_misses::total 718367
+system.cpu.dcache.overall_mshr_misses::cpu.data 839576
+system.cpu.dcache.overall_mshr_misses::total 839576
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31110
+system.cpu.dcache.ReadReq_mshr_uncacheable::total 31110
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27574
+system.cpu.dcache.WriteReq_mshr_uncacheable::total 27574
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58684
+system.cpu.dcache.overall_mshr_uncacheable_misses::total 58684
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6445053500
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 6445053500
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14252180000
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 14252180000
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1665054500
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1665054500
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118677000
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118677000
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169000
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169000
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20697233500
+system.cpu.dcache.demand_mshr_miss_latency::total 20697233500
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22362288000
+system.cpu.dcache.overall_mshr_miss_latency::total 22362288000
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6302505000
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6302505000
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6302505000
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 6302505000
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017836
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017836
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015917
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015917
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230217
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230217
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017609
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017609
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016983
+system.cpu.dcache.demand_mshr_miss_rate::total 0.016983
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019605
+system.cpu.dcache.overall_mshr_miss_rate::total 0.019605
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15372.633600
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15372.633600
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47648.305651
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47648.305651
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13737.053354
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13737.053354
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14474.570070
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14474.570070
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 84500
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 84500
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28811.503730
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28811.503730
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26635.215871
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26635.215871
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202587.753134
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202587.753134
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107397.331470
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107397.331470
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.cpu.icache.tags.replacements 2889221
+system.cpu.icache.tags.tagsinuse 511.371129
+system.cpu.icache.tags.total_refs 54595271
+system.cpu.icache.tags.sampled_refs 2889733
+system.cpu.icache.tags.avg_refs 18.892843
+system.cpu.icache.tags.warmup_cycle 16096310500
+system.cpu.icache.tags.occ_blocks::cpu.inst 511.371129
+system.cpu.icache.tags.occ_percent::cpu.inst 0.998772
+system.cpu.icache.tags.occ_percent::total 0.998772
+system.cpu.icache.tags.occ_task_id_blocks::1024 512
+system.cpu.icache.tags.age_task_id_blocks_1024::0 101
+system.cpu.icache.tags.age_task_id_blocks_1024::1 214
+system.cpu.icache.tags.age_task_id_blocks_1024::2 197
+system.cpu.icache.tags.occ_task_id_percent::1024 1
+system.cpu.icache.tags.tag_accesses 60374760
+system.cpu.icache.tags.data_accesses 60374760
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.cpu.icache.ReadReq_hits::cpu.inst 54595271
+system.cpu.icache.ReadReq_hits::total 54595271
+system.cpu.icache.demand_hits::cpu.inst 54595271
+system.cpu.icache.demand_hits::total 54595271
+system.cpu.icache.overall_hits::cpu.inst 54595271
+system.cpu.icache.overall_hits::total 54595271
+system.cpu.icache.ReadReq_misses::cpu.inst 2889745
+system.cpu.icache.ReadReq_misses::total 2889745
+system.cpu.icache.demand_misses::cpu.inst 2889745
+system.cpu.icache.demand_misses::total 2889745
+system.cpu.icache.overall_misses::cpu.inst 2889745
+system.cpu.icache.overall_misses::total 2889745
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 39793127500
+system.cpu.icache.ReadReq_miss_latency::total 39793127500
+system.cpu.icache.demand_miss_latency::cpu.inst 39793127500
+system.cpu.icache.demand_miss_latency::total 39793127500
+system.cpu.icache.overall_miss_latency::cpu.inst 39793127500
+system.cpu.icache.overall_miss_latency::total 39793127500
+system.cpu.icache.ReadReq_accesses::cpu.inst 57485016
+system.cpu.icache.ReadReq_accesses::total 57485016
+system.cpu.icache.demand_accesses::cpu.inst 57485016
+system.cpu.icache.demand_accesses::total 57485016
+system.cpu.icache.overall_accesses::cpu.inst 57485016
+system.cpu.icache.overall_accesses::total 57485016
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050270
+system.cpu.icache.ReadReq_miss_rate::total 0.050270
+system.cpu.icache.demand_miss_rate::cpu.inst 0.050270
+system.cpu.icache.demand_miss_rate::total 0.050270
+system.cpu.icache.overall_miss_rate::cpu.inst 0.050270
+system.cpu.icache.overall_miss_rate::total 0.050270
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13770.463311
+system.cpu.icache.ReadReq_avg_miss_latency::total 13770.463311
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13770.463311
+system.cpu.icache.demand_avg_miss_latency::total 13770.463311
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13770.463311
+system.cpu.icache.overall_avg_miss_latency::total 13770.463311
+system.cpu.icache.blocked_cycles::no_mshrs 0
+system.cpu.icache.blocked_cycles::no_targets 0
+system.cpu.icache.blocked::no_mshrs 0
+system.cpu.icache.blocked::no_targets 0
+system.cpu.icache.avg_blocked_cycles::no_mshrs nan
+system.cpu.icache.avg_blocked_cycles::no_targets nan
+system.cpu.icache.writebacks::writebacks 2889221
+system.cpu.icache.writebacks::total 2889221
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2889745
+system.cpu.icache.ReadReq_mshr_misses::total 2889745
+system.cpu.icache.demand_mshr_misses::cpu.inst 2889745
+system.cpu.icache.demand_mshr_misses::total 2889745
+system.cpu.icache.overall_mshr_misses::cpu.inst 2889745
+system.cpu.icache.overall_mshr_misses::total 2889745
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3119
+system.cpu.icache.ReadReq_mshr_uncacheable::total 3119
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3119
+system.cpu.icache.overall_mshr_uncacheable_misses::total 3119
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36903383500
+system.cpu.icache.ReadReq_mshr_miss_latency::total 36903383500
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36903383500
+system.cpu.icache.demand_mshr_miss_latency::total 36903383500
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36903383500
+system.cpu.icache.overall_mshr_miss_latency::total 36903383500
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 265216500
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 265216500
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 265216500
+system.cpu.icache.overall_mshr_uncacheable_latency::total 265216500
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050270
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050270
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050270
+system.cpu.icache.demand_mshr_miss_rate::total 0.050270
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050270
+system.cpu.icache.overall_mshr_miss_rate::total 0.050270
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12770.463657
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12770.463657
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12770.463657
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12770.463657
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12770.463657
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12770.463657
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85032.542482
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85032.542482
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85032.542482
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85032.542482
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.cpu.l2cache.tags.replacements 96735
+system.cpu.l2cache.tags.tagsinuse 65145.168684
+system.cpu.l2cache.tags.total_refs 7316055
+system.cpu.l2cache.tags.sampled_refs 162131
+system.cpu.l2cache.tags.avg_refs 45.124344
+system.cpu.l2cache.tags.warmup_cycle 100163301000
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 70.099174
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.032946
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 12110.066628
+system.cpu.l2cache.tags.occ_blocks::cpu.data 52964.969936
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001070
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.184785
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.808181
+system.cpu.l2cache.tags.occ_percent::total 0.994036
+system.cpu.l2cache.tags.occ_task_id_blocks::1023 46
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 65350
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4 46
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 89
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4574
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60686
+system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000702
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997162
+system.cpu.l2cache.tags.tag_accesses 60043597
+system.cpu.l2cache.tags.data_accesses 60043597
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67906
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3398
+system.cpu.l2cache.ReadReq_hits::total 71304
+system.cpu.l2cache.WritebackDirty_hits::writebacks 701832
+system.cpu.l2cache.WritebackDirty_hits::total 701832
+system.cpu.l2cache.WritebackClean_hits::writebacks 2838620
+system.cpu.l2cache.WritebackClean_hits::total 2838620
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 2784
+system.cpu.l2cache.UpgradeReq_hits::total 2784
+system.cpu.l2cache.ReadExReq_hits::cpu.data 167004
+system.cpu.l2cache.ReadExReq_hits::total 167004
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2866770
+system.cpu.l2cache.ReadCleanReq_hits::total 2866770
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 534209
+system.cpu.l2cache.ReadSharedReq_hits::total 534209
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 67906
+system.cpu.l2cache.demand_hits::cpu.itb.walker 3398
+system.cpu.l2cache.demand_hits::cpu.inst 2866770
+system.cpu.l2cache.demand_hits::cpu.data 701213
+system.cpu.l2cache.demand_hits::total 3639287
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 67906
+system.cpu.l2cache.overall_hits::cpu.itb.walker 3398
+system.cpu.l2cache.overall_hits::cpu.inst 2866770
+system.cpu.l2cache.overall_hits::cpu.data 701213
+system.cpu.l2cache.overall_hits::total 3639287
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 109
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2
+system.cpu.l2cache.ReadReq_misses::total 111
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 6
+system.cpu.l2cache.UpgradeReq_misses::total 6
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2
+system.cpu.l2cache.SCUpgradeReq_misses::total 2
+system.cpu.l2cache.ReadExReq_misses::cpu.data 129322
+system.cpu.l2cache.ReadExReq_misses::total 129322
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22936
+system.cpu.l2cache.ReadCleanReq_misses::total 22936
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14450
+system.cpu.l2cache.ReadSharedReq_misses::total 14450
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 109
+system.cpu.l2cache.demand_misses::cpu.itb.walker 2
+system.cpu.l2cache.demand_misses::cpu.inst 22936
+system.cpu.l2cache.demand_misses::cpu.data 143772
+system.cpu.l2cache.demand_misses::total 166819
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 109
+system.cpu.l2cache.overall_misses::cpu.itb.walker 2
+system.cpu.l2cache.overall_misses::cpu.inst 22936
+system.cpu.l2cache.overall_misses::cpu.data 143772
+system.cpu.l2cache.overall_misses::total 166819
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 35817000
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 193000
+system.cpu.l2cache.ReadReq_miss_latency::total 36010000
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 174000
+system.cpu.l2cache.UpgradeReq_miss_latency::total 174000
+system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 166000
+system.cpu.l2cache.SCUpgradeReq_miss_latency::total 166000
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12012379500
+system.cpu.l2cache.ReadExReq_miss_latency::total 12012379500
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2400764000
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 2400764000
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1756081500
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 1756081500
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 35817000
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 193000
+system.cpu.l2cache.demand_miss_latency::cpu.inst 2400764000
+system.cpu.l2cache.demand_miss_latency::cpu.data 13768461000
+system.cpu.l2cache.demand_miss_latency::total 16205235000
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 35817000
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 193000
+system.cpu.l2cache.overall_miss_latency::cpu.inst 2400764000
+system.cpu.l2cache.overall_miss_latency::cpu.data 13768461000
+system.cpu.l2cache.overall_miss_latency::total 16205235000
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68015
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3400
+system.cpu.l2cache.ReadReq_accesses::total 71415
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 701832
+system.cpu.l2cache.WritebackDirty_accesses::total 701832
+system.cpu.l2cache.WritebackClean_accesses::writebacks 2838620
+system.cpu.l2cache.WritebackClean_accesses::total 2838620
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2790
+system.cpu.l2cache.UpgradeReq_accesses::total 2790
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2
+system.cpu.l2cache.SCUpgradeReq_accesses::total 2
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 296326
+system.cpu.l2cache.ReadExReq_accesses::total 296326
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2889706
+system.cpu.l2cache.ReadCleanReq_accesses::total 2889706
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548659
+system.cpu.l2cache.ReadSharedReq_accesses::total 548659
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68015
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 3400
+system.cpu.l2cache.demand_accesses::cpu.inst 2889706
+system.cpu.l2cache.demand_accesses::cpu.data 844985
+system.cpu.l2cache.demand_accesses::total 3806106
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68015
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 3400
+system.cpu.l2cache.overall_accesses::cpu.inst 2889706
+system.cpu.l2cache.overall_accesses::cpu.data 844985
+system.cpu.l2cache.overall_accesses::total 3806106
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001603
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000588
+system.cpu.l2cache.ReadReq_miss_rate::total 0.001554
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002151
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002151
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436418
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.436418
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007937
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007937
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026337
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026337
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001603
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000588
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007937
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.170147
+system.cpu.l2cache.demand_miss_rate::total 0.043829
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001603
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000588
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007937
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.170147
+system.cpu.l2cache.overall_miss_rate::total 0.043829
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 328596.330275
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 96500
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 324414.414414
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29000
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29000
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 83000
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 83000
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92887.362552
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92887.362552
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 104672.305546
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 104672.305546
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121528.131488
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121528.131488
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 328596.330275
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 96500
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 104672.305546
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95765.941908
+system.cpu.l2cache.demand_avg_miss_latency::total 97142.621644
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 328596.330275
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 96500
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 104672.305546
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95765.941908
+system.cpu.l2cache.overall_avg_miss_latency::total 97142.621644
+system.cpu.l2cache.blocked_cycles::no_mshrs 0
+system.cpu.l2cache.blocked_cycles::no_targets 0
+system.cpu.l2cache.blocked::no_mshrs 0
+system.cpu.l2cache.blocked::no_targets 0
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu.l2cache.writebacks::writebacks 88138
+system.cpu.l2cache.writebacks::total 88138
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 15
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total 15
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 141
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total 141
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 15
+system.cpu.l2cache.demand_mshr_hits::cpu.data 141
+system.cpu.l2cache.demand_mshr_hits::total 156
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 15
+system.cpu.l2cache.overall_mshr_hits::cpu.data 141
+system.cpu.l2cache.overall_mshr_hits::total 156
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 109
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2
+system.cpu.l2cache.ReadReq_mshr_misses::total 111
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 6
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129322
+system.cpu.l2cache.ReadExReq_mshr_misses::total 129322
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22921
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22921
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14309
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14309
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 109
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 22921
+system.cpu.l2cache.demand_mshr_misses::cpu.data 143631
+system.cpu.l2cache.demand_mshr_misses::total 166663
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 109
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 22921
+system.cpu.l2cache.overall_mshr_misses::cpu.data 143631
+system.cpu.l2cache.overall_mshr_misses::total 166663
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3119
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31110
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34229
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27574
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27574
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3119
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58684
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61803
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 34727000
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 173000
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34900000
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114000
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114000
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 146000
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 146000
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10719159500
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10719159500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2169633500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2169633500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1600506000
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1600506000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 34727000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 173000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2169633500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12319665500
+system.cpu.l2cache.demand_mshr_miss_latency::total 14524199000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 34727000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 173000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2169633500
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12319665500
+system.cpu.l2cache.overall_mshr_miss_latency::total 14524199000
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 216819500
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5913550000
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6130369500
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 216819500
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5913550000
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6130369500
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001603
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000588
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001554
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002151
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002151
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436418
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436418
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007932
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007932
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026080
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026080
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001603
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000588
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007932
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169981
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.043788
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001603
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000588
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007932
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169981
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.043788
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 318596.330275
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 86500
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 314414.414414
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19000
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19000
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 73000
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 73000
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82887.362552
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82887.362552
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 94657.017582
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 94657.017582
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 111853.099448
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 111853.099448
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 318596.330275
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 86500
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 94657.017582
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85773.026018
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87147.111236
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 318596.330275
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 86500
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 94657.017582
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85773.026018
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87147.111236
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69515.710164
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190085.181614
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179098.702854
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69515.710164
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100769.374957
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99192.102325
+system.cpu.toL2Bus.snoop_filter.tot_requests 7501872
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 3767165
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 57954
+system.cpu.toL2Bus.snoop_filter.tot_snoops 184
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 184
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.cpu.toL2Bus.trans_dist::ReadReq 136326
+system.cpu.toL2Bus.trans_dist::ReadResp 3574876
+system.cpu.toL2Bus.trans_dist::WriteReq 27574
+system.cpu.toL2Bus.trans_dist::WriteResp 27574
+system.cpu.toL2Bus.trans_dist::WritebackDirty 789970
+system.cpu.toL2Bus.trans_dist::WritebackClean 2889221
+system.cpu.toL2Bus.trans_dist::CleanEvict 151212
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2790
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2792
+system.cpu.toL2Bus.trans_dist::ReadExReq 296326
+system.cpu.toL2Bus.trans_dist::ReadExResp 296326
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 2889745
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 548882
+system.cpu.toL2Bus.trans_dist::InvalidateReq 4410
+system.cpu.toL2Bus.trans_dist::InvalidateResp 13
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8674909
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2657529
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14746
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158766
+system.cpu.toL2Bus.pkt_count::total 11505950
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370050880
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99188687
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13600
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 272060
+system.cpu.toL2Bus.pkt_size::total 469525227
+system.cpu.toL2Bus.snoops 132249
+system.cpu.toL2Bus.snoopTraffic 5775464
+system.cpu.toL2Bus.snoop_fanout::samples 4002790
+system.cpu.toL2Bus.snoop_fanout::mean 0.022195
+system.cpu.toL2Bus.snoop_fanout::stdev 0.147318
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 3913947 97.78% 97.78%
+system.cpu.toL2Bus.snoop_fanout::1 88843 2.22% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 1
+system.cpu.toL2Bus.snoop_fanout::total 4002790
+system.cpu.toL2Bus.reqLayer0.occupancy 7422385000
+system.cpu.toL2Bus.reqLayer0.utilization 0.3
+system.cpu.toL2Bus.snoopLayer0.occupancy 287877
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer0.occupancy 4339897791
+system.cpu.toL2Bus.respLayer0.utilization 0.2
+system.cpu.toL2Bus.respLayer1.occupancy 1314003533
+system.cpu.toL2Bus.respLayer1.utilization 0.0
+system.cpu.toL2Bus.respLayer2.occupancy 11348994
+system.cpu.toL2Bus.respLayer2.utilization 0.0
+system.cpu.toL2Bus.respLayer3.occupancy 90782437
+system.cpu.toL2Bus.respLayer3.utilization 0.0
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.iobus.trans_dist::ReadReq 30173
+system.iobus.trans_dist::ReadResp 30173
+system.iobus.trans_dist::WriteReq 59014
+system.iobus.trans_dist::WriteResp 59014
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268
+system.iobus.pkt_count_system.bridge.master::total 105458
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916
+system.iobus.pkt_count_system.realview.ide.dma::total 72916
+system.iobus.pkt_count::total 178374
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536
+system.iobus.pkt_size_system.bridge.master::total 159115
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104
+system.iobus.pkt_size_system.realview.ide.dma::total 2321104
+system.iobus.pkt_size::total 2480219
+system.iobus.reqLayer0.occupancy 46330500
+system.iobus.reqLayer0.utilization 0.0
+system.iobus.reqLayer1.occupancy 106500
+system.iobus.reqLayer1.utilization 0.0
+system.iobus.reqLayer2.occupancy 322500
+system.iobus.reqLayer2.utilization 0.0
+system.iobus.reqLayer3.occupancy 30000
+system.iobus.reqLayer3.utilization 0.0
+system.iobus.reqLayer4.occupancy 14500
+system.iobus.reqLayer4.utilization 0.0
+system.iobus.reqLayer7.occupancy 85500
+system.iobus.reqLayer7.utilization 0.0
+system.iobus.reqLayer8.occupancy 606500
+system.iobus.reqLayer8.utilization 0.0
+system.iobus.reqLayer10.occupancy 22000
+system.iobus.reqLayer10.utilization 0.0
+system.iobus.reqLayer13.occupancy 11000
+system.iobus.reqLayer13.utilization 0.0
+system.iobus.reqLayer14.occupancy 11000
+system.iobus.reqLayer14.utilization 0.0
+system.iobus.reqLayer15.occupancy 10500
+system.iobus.reqLayer15.utilization 0.0
+system.iobus.reqLayer16.occupancy 51500
+system.iobus.reqLayer16.utilization 0.0
+system.iobus.reqLayer17.occupancy 9500
+system.iobus.reqLayer17.utilization 0.0
+system.iobus.reqLayer18.occupancy 10000
+system.iobus.reqLayer18.utilization 0.0
+system.iobus.reqLayer19.occupancy 2500
+system.iobus.reqLayer19.utilization 0.0
+system.iobus.reqLayer20.occupancy 10000
+system.iobus.reqLayer20.utilization 0.0
+system.iobus.reqLayer21.occupancy 9000
+system.iobus.reqLayer21.utilization 0.0
+system.iobus.reqLayer23.occupancy 6091500
+system.iobus.reqLayer23.utilization 0.0
+system.iobus.reqLayer24.occupancy 39097500
+system.iobus.reqLayer24.utilization 0.0
+system.iobus.reqLayer25.occupancy 187695840
+system.iobus.reqLayer25.utilization 0.0
+system.iobus.respLayer0.occupancy 82668000
+system.iobus.respLayer0.utilization 0.0
+system.iobus.respLayer3.occupancy 36740000
+system.iobus.respLayer3.utilization 0.0
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.iocache.tags.replacements 36424
+system.iocache.tags.tagsinuse 1.033903
+system.iocache.tags.total_refs 0
+system.iocache.tags.sampled_refs 36440
+system.iocache.tags.avg_refs 0
+system.iocache.tags.warmup_cycle 272037045000
+system.iocache.tags.occ_blocks::realview.ide 1.033903
+system.iocache.tags.occ_percent::realview.ide 0.064619
+system.iocache.tags.occ_percent::total 0.064619
+system.iocache.tags.occ_task_id_blocks::1023 16
+system.iocache.tags.age_task_id_blocks_1023::3 16
+system.iocache.tags.occ_task_id_percent::1023 1
+system.iocache.tags.tag_accesses 328122
+system.iocache.tags.data_accesses 328122
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.iocache.ReadReq_misses::realview.ide 234
+system.iocache.ReadReq_misses::total 234
+system.iocache.WriteLineReq_misses::realview.ide 36224
+system.iocache.WriteLineReq_misses::total 36224
+system.iocache.demand_misses::realview.ide 36458
+system.iocache.demand_misses::total 36458
+system.iocache.overall_misses::realview.ide 36458
+system.iocache.overall_misses::total 36458
+system.iocache.ReadReq_miss_latency::realview.ide 37408377
+system.iocache.ReadReq_miss_latency::total 37408377
+system.iocache.WriteLineReq_miss_latency::realview.ide 4382403463
+system.iocache.WriteLineReq_miss_latency::total 4382403463
+system.iocache.demand_miss_latency::realview.ide 4419811840
+system.iocache.demand_miss_latency::total 4419811840
+system.iocache.overall_miss_latency::realview.ide 4419811840
+system.iocache.overall_miss_latency::total 4419811840
+system.iocache.ReadReq_accesses::realview.ide 234
+system.iocache.ReadReq_accesses::total 234
+system.iocache.WriteLineReq_accesses::realview.ide 36224
+system.iocache.WriteLineReq_accesses::total 36224
+system.iocache.demand_accesses::realview.ide 36458
+system.iocache.demand_accesses::total 36458
+system.iocache.overall_accesses::realview.ide 36458
+system.iocache.overall_accesses::total 36458
+system.iocache.ReadReq_miss_rate::realview.ide 1
+system.iocache.ReadReq_miss_rate::total 1
+system.iocache.WriteLineReq_miss_rate::realview.ide 1
+system.iocache.WriteLineReq_miss_rate::total 1
+system.iocache.demand_miss_rate::realview.ide 1
+system.iocache.demand_miss_rate::total 1
+system.iocache.overall_miss_rate::realview.ide 1
+system.iocache.overall_miss_rate::total 1
+system.iocache.ReadReq_avg_miss_latency::realview.ide 159864.858974
+system.iocache.ReadReq_avg_miss_latency::total 159864.858974
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120980.660971
+system.iocache.WriteLineReq_avg_miss_latency::total 120980.660971
+system.iocache.demand_avg_miss_latency::realview.ide 121230.233145
+system.iocache.demand_avg_miss_latency::total 121230.233145
+system.iocache.overall_avg_miss_latency::realview.ide 121230.233145
+system.iocache.overall_avg_miss_latency::total 121230.233145
+system.iocache.blocked_cycles::no_mshrs 31
+system.iocache.blocked_cycles::no_targets 0
+system.iocache.blocked::no_mshrs 2
+system.iocache.blocked::no_targets 0
+system.iocache.avg_blocked_cycles::no_mshrs 15.500000
+system.iocache.avg_blocked_cycles::no_targets nan
+system.iocache.writebacks::writebacks 36190
+system.iocache.writebacks::total 36190
+system.iocache.ReadReq_mshr_misses::realview.ide 234
+system.iocache.ReadReq_mshr_misses::total 234
+system.iocache.WriteLineReq_mshr_misses::realview.ide 36224
+system.iocache.WriteLineReq_mshr_misses::total 36224
+system.iocache.demand_mshr_misses::realview.ide 36458
+system.iocache.demand_mshr_misses::total 36458
+system.iocache.overall_mshr_misses::realview.ide 36458
+system.iocache.overall_mshr_misses::total 36458
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 25708377
+system.iocache.ReadReq_mshr_miss_latency::total 25708377
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2569352147
+system.iocache.WriteLineReq_mshr_miss_latency::total 2569352147
+system.iocache.demand_mshr_miss_latency::realview.ide 2595060524
+system.iocache.demand_mshr_miss_latency::total 2595060524
+system.iocache.overall_mshr_miss_latency::realview.ide 2595060524
+system.iocache.overall_mshr_miss_latency::total 2595060524
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1
+system.iocache.ReadReq_mshr_miss_rate::total 1
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1
+system.iocache.WriteLineReq_mshr_miss_rate::total 1
+system.iocache.demand_mshr_miss_rate::realview.ide 1
+system.iocache.demand_mshr_miss_rate::total 1
+system.iocache.overall_mshr_miss_rate::realview.ide 1
+system.iocache.overall_mshr_miss_rate::total 1
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 109864.858974
+system.iocache.ReadReq_avg_mshr_miss_latency::total 109864.858974
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70929.553528
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70929.553528
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 71179.453728
+system.iocache.demand_avg_mshr_miss_latency::total 71179.453728
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 71179.453728
+system.iocache.overall_avg_mshr_miss_latency::total 71179.453728
+system.membus.snoop_filter.tot_requests 336351
+system.membus.snoop_filter.hit_single_requests 137754
+system.membus.snoop_filter.hit_multi_requests 539
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.membus.trans_dist::ReadReq 34229
+system.membus.trans_dist::ReadResp 71804
+system.membus.trans_dist::WriteReq 27574
+system.membus.trans_dist::WriteResp 27574
+system.membus.trans_dist::WritebackDirty 124328
+system.membus.trans_dist::CleanEvict 8831
+system.membus.trans_dist::UpgradeReq 128
+system.membus.trans_dist::SCUpgradeReq 2
+system.membus.trans_dist::UpgradeResp 2
+system.membus.trans_dist::ReadExReq 129200
+system.membus.trans_dist::ReadExResp 129200
+system.membus.trans_dist::ReadSharedReq 37575
+system.membus.trans_dist::InvalidateReq 36224
+system.membus.trans_dist::InvalidateResp 4361
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105458
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2034
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445761
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553269
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897
+system.membus.pkt_count_system.iocache.mem_side::total 72897
+system.membus.pkt_count::total 626166
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159115
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4068
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16500192
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16663887
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120
+system.membus.pkt_size_system.iocache.mem_side::total 2317120
+system.membus.pkt_size::total 18981007
+system.membus.snoops 4866
+system.membus.snoopTraffic 32192
+system.membus.snoop_fanout::samples 264932
+system.membus.snoop_fanout::mean 0.018567
+system.membus.snoop_fanout::stdev 0.134990
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 260013 98.14% 98.14%
+system.membus.snoop_fanout::1 4919 1.86% 100.00%
+system.membus.snoop_fanout::2 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 1
+system.membus.snoop_fanout::total 264932
+system.membus.reqLayer0.occupancy 92832000
+system.membus.reqLayer0.utilization 0.0
+system.membus.reqLayer1.occupancy 8000
+system.membus.reqLayer1.utilization 0.0
+system.membus.reqLayer2.occupancy 1658500
+system.membus.reqLayer2.utilization 0.0
+system.membus.reqLayer5.occupancy 903719482
+system.membus.reqLayer5.utilization 0.0
+system.membus.respLayer2.occupancy 987883000
+system.membus.respLayer2.utilization 0.0
+system.membus.respLayer3.occupancy 5809413
+system.membus.respLayer3.utilization 0.0
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.dcc.osc_cpu.clock 16667
+system.realview.dcc.osc_ddr.clock 25000
+system.realview.dcc.osc_hsbm.clock 25000
+system.realview.dcc.osc_pxl.clock 42105
+system.realview.dcc.osc_smb.clock 20000
+system.realview.dcc.osc_sys.clock 16667
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.ethernet.descDMAReads 0
+system.realview.ethernet.descDMAWrites 0
+system.realview.ethernet.descDmaReadBytes 0
+system.realview.ethernet.descDmaWriteBytes 0
+system.realview.ethernet.postedSwi 0
+system.realview.ethernet.coalescedSwi nan
+system.realview.ethernet.totalSwi 0
+system.realview.ethernet.postedRxIdle 0
+system.realview.ethernet.coalescedRxIdle nan
+system.realview.ethernet.totalRxIdle 0
+system.realview.ethernet.postedRxOk 0
+system.realview.ethernet.coalescedRxOk nan
+system.realview.ethernet.totalRxOk 0
+system.realview.ethernet.postedRxDesc 0
+system.realview.ethernet.coalescedRxDesc nan
+system.realview.ethernet.totalRxDesc 0
+system.realview.ethernet.postedTxOk 0
+system.realview.ethernet.coalescedTxOk nan
+system.realview.ethernet.totalTxOk 0
+system.realview.ethernet.postedTxIdle 0
+system.realview.ethernet.coalescedTxIdle nan
+system.realview.ethernet.totalTxIdle 0
+system.realview.ethernet.postedTxDesc 0
+system.realview.ethernet.coalescedTxDesc nan
+system.realview.ethernet.totalTxDesc 0
+system.realview.ethernet.postedRxOrn 0
+system.realview.ethernet.coalescedRxOrn nan
+system.realview.ethernet.totalRxOrn 0
+system.realview.ethernet.coalescedTotal nan
+system.realview.ethernet.postedInterrupts 0
+system.realview.ethernet.droppedPackets 0
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.mcc.osc_clcd.clock 42105
+system.realview.mcc.osc_mcc.clock 20000
+system.realview.mcc.osc_peripheral.clock 41667
+system.realview.mcc.osc_system_bus.clock 41667
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854927627500
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
+boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_panic=true
phys_addr_range_64=40
power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
+readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
+image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
activity=0
backComSize=5
branchPred=system.cpu0.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu0.tracer
trapLatency=13
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
sequential_access=false
size=32768
system=system
+tag_latency=2
tags=system.cpu0.dcache.tags
tgts_per_mshr=8
write_buffers=16
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=2
[system.cpu0.dstage2_mmu]
type=ArmStage2MMU
[system.cpu0.fuPool.FUList2]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu0.fuPool.FUList2.opList
+opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1
-[system.cpu0.fuPool.FUList2.opList]
+[system.cpu0.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
+[system.cpu0.fuPool.FUList2.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=2
+pipelined=true
+
[system.cpu0.fuPool.FUList3]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu0.fuPool.FUList3.opList
+opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1
-[system.cpu0.fuPool.FUList3.opList]
+[system.cpu0.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
+[system.cpu0.fuPool.FUList3.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=2
+pipelined=true
+
[system.cpu0.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
-opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25
+opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25 system.cpu0.fuPool.FUList4.opList26 system.cpu0.fuPool.FUList4.opList27
[system.cpu0.fuPool.FUList4.opList00]
type=OpDesc
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
-opLat=1
+opLat=5
pipelined=true
[system.cpu0.fuPool.FUList4.opList19]
opLat=4
pipelined=true
+[system.cpu0.fuPool.FUList4.opList26]
+type=OpDesc
+eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu0.fuPool.FUList4.opList27]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
[system.cpu0.icache]
type=Cache
children=tags
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
sequential_access=false
size=32768
system=system
+tag_latency=1
tags=system.cpu0.icache.tags
tgts_per_mshr=8
write_buffers=8
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=1
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=1
[system.cpu0.interrupts]
type=ArmInterrupts
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
+data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
sequential_access=false
size=1048576
system=system
+tag_latency=12
tags=system.cpu0.l2cache.tags
tgts_per_mshr=8
write_buffers=8
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=12
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
+tag_latency=12
[system.cpu0.toL2Bus]
type=CoherentXBar
activity=0
backComSize=5
branchPred=system.cpu1.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu1.tracer
trapLatency=13
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
sequential_access=false
size=32768
system=system
+tag_latency=2
tags=system.cpu1.dcache.tags
tgts_per_mshr=8
write_buffers=16
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=2
[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
[system.cpu1.fuPool.FUList2]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu1.fuPool.FUList2.opList
+opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1
-[system.cpu1.fuPool.FUList2.opList]
+[system.cpu1.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
+[system.cpu1.fuPool.FUList2.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=2
+pipelined=true
+
[system.cpu1.fuPool.FUList3]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu1.fuPool.FUList3.opList
+opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1
-[system.cpu1.fuPool.FUList3.opList]
+[system.cpu1.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
+[system.cpu1.fuPool.FUList3.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=2
+pipelined=true
+
[system.cpu1.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
-opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25
+opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25 system.cpu1.fuPool.FUList4.opList26 system.cpu1.fuPool.FUList4.opList27
[system.cpu1.fuPool.FUList4.opList00]
type=OpDesc
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
-opLat=1
+opLat=5
pipelined=true
[system.cpu1.fuPool.FUList4.opList19]
opLat=4
pipelined=true
+[system.cpu1.fuPool.FUList4.opList26]
+type=OpDesc
+eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu1.fuPool.FUList4.opList27]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
[system.cpu1.icache]
type=Cache
children=tags
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
sequential_access=false
size=32768
system=system
+tag_latency=1
tags=system.cpu1.icache.tags
tgts_per_mshr=8
write_buffers=8
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=1
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=1
[system.cpu1.interrupts]
type=ArmInterrupts
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
+data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
sequential_access=false
size=1048576
system=system
+tag_latency=12
tags=system.cpu1.l2cache.tags
tgts_per_mshr=8
write_buffers=8
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=12
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
+tag_latency=12
[system.cpu1.toL2Bus]
type=CoherentXBar
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
+data_latency=50
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=50
is_read_only=false
max_miss_count=0
mshrs=20
sequential_access=false
size=1024
system=system
+tag_latency=50
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
assoc=8
block_size=64
clk_domain=system.clk_domain
+data_latency=50
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=50
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1024
+tag_latency=50
[system.l2c]
type=Cache
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
sequential_access=false
size=4194304
system=system
+tag_latency=20
tags=system.l2c.tags
tgts_per_mshr=12
write_buffers=8
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=4194304
+tag_latency=20
[system.membus]
type=CoherentXBar
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+info: Entering event queue @ 0. Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[4], opc1[4], crm[0], opc2[0]
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: instruction 'mcr bpiall' unimplemented
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
warn: allocating bonus target for snoop
+warn: allocating bonus target for snoop
warn: Returning zero for read from miscreg pmcr
warn: Ignoring write to miscreg pmcntenclr
warn: Ignoring write to miscreg pmintenclr
warn: Ignoring write to miscreg pmovsr
warn: Ignoring write to miscreg pmcr
warn: instruction 'mcr dcisw' unimplemented
-warn: CP14 unimplemented crn[3], opc1[5], crm[8], opc2[0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 21:00:48
-gem5 executing on e108600-lin, pid 17551
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-dual
+gem5 compiled Mar 29 2017 19:38:26
+gem5 started Mar 29 2017 19:38:42
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83601
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2826594924500 because m5_exit instruction encountered
+Exiting @ tick 2826661822500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.826673 # Number of seconds simulated
-sim_ticks 2826672558500 # Number of ticks simulated
-final_tick 2826672558500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 170041 # Simulator instruction rate (inst/s)
-host_op_rate 206302 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4002646805 # Simulator tick rate (ticks/s)
-host_mem_usage 627056 # Number of bytes of host memory used
-host_seconds 706.20 # Real time elapsed on the host
-sim_insts 120082757 # Number of instructions simulated
-sim_ops 145690782 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1308688 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 1308456 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8387648 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 193312 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 594324 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 432320 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12228268 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1308688 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 193312 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1502000 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8790464 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8808028 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 22699 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 20965 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 131057 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 3088 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 9307 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 6755 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 193926 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 137351 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 141742 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 657 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 462978 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 462896 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 2967322 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 158 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 68389 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 210256 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 152943 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4326029 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 462978 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 68389 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 531367 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3109827 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6200 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3116041 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3109827 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 657 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 462978 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 469096 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 2967322 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 158 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 68389 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 210270 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 152943 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7442070 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 193927 # Number of read requests accepted
-system.physmem.writeReqs 141742 # Number of write requests accepted
-system.physmem.readBursts 193927 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 141742 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 12400768 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 10496 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8820224 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 12228332 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8808028 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 164 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11912 # Per bank write bursts
-system.physmem.perBankRdBursts::1 11892 # Per bank write bursts
-system.physmem.perBankRdBursts::2 12330 # Per bank write bursts
-system.physmem.perBankRdBursts::3 12174 # Per bank write bursts
-system.physmem.perBankRdBursts::4 14942 # Per bank write bursts
-system.physmem.perBankRdBursts::5 12676 # Per bank write bursts
-system.physmem.perBankRdBursts::6 12556 # Per bank write bursts
-system.physmem.perBankRdBursts::7 12785 # Per bank write bursts
-system.physmem.perBankRdBursts::8 12022 # Per bank write bursts
-system.physmem.perBankRdBursts::9 12081 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11226 # Per bank write bursts
-system.physmem.perBankRdBursts::11 10162 # Per bank write bursts
-system.physmem.perBankRdBursts::12 11365 # Per bank write bursts
-system.physmem.perBankRdBursts::13 11848 # Per bank write bursts
-system.physmem.perBankRdBursts::14 11951 # Per bank write bursts
-system.physmem.perBankRdBursts::15 11840 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8683 # Per bank write bursts
-system.physmem.perBankWrBursts::1 8758 # Per bank write bursts
-system.physmem.perBankWrBursts::2 9038 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8776 # Per bank write bursts
-system.physmem.perBankWrBursts::4 8736 # Per bank write bursts
-system.physmem.perBankWrBursts::5 9287 # Per bank write bursts
-system.physmem.perBankWrBursts::6 9143 # Per bank write bursts
-system.physmem.perBankWrBursts::7 9209 # Per bank write bursts
-system.physmem.perBankWrBursts::8 8594 # Per bank write bursts
-system.physmem.perBankWrBursts::9 8600 # Per bank write bursts
-system.physmem.perBankWrBursts::10 8159 # Per bank write bursts
-system.physmem.perBankWrBursts::11 7478 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8406 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8230 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8500 # Per bank write bursts
-system.physmem.perBankWrBursts::15 8219 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 60 # Number of times write queue was full causing retry
-system.physmem.totGap 2826672288500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 551 # Read request sizes (log2)
-system.physmem.readPktSize::3 28 # Read request sizes (log2)
-system.physmem.readPktSize::4 3091 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 190257 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 4391 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 137351 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 58372 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 70356 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 15687 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 12836 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 8377 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 7582 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 6463 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 5422 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 4671 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1517 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1143 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 747 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 311 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 270 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2460 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 3319 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 3946 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 4422 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5293 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5687 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6555 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 7267 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 8245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 8247 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 9579 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 10099 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 8863 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 8597 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 9328 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 10498 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 8586 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 8360 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 1159 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 775 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 597 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 398 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 318 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 317 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 293 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 239 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 192 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 226 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 221 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 226 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 192 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 236 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 194 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 206 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 213 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 201 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 160 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 174 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 181 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 190 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 229 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 202 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 157 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 155 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 208 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 159 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 187 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 84506 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 251.118169 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 142.721377 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 307.168687 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 42580 50.39% 50.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 17667 20.91% 71.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6229 7.37% 78.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3460 4.09% 82.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2829 3.35% 86.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1565 1.85% 87.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 960 1.14% 89.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 994 1.18% 90.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8222 9.73% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 84506 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6824 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 28.393318 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 563.270042 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6822 99.97% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6824 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6824 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.195780 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.530637 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 13.731147 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5748 84.23% 84.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 362 5.30% 89.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 98 1.44% 90.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 53 0.78% 91.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 250 3.66% 95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 24 0.35% 95.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 17 0.25% 96.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 13 0.19% 96.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 6 0.09% 96.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 8 0.12% 96.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 10 0.15% 96.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 144 2.11% 98.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 13 0.19% 98.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 7 0.10% 98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 6 0.09% 99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 7 0.10% 99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 2 0.03% 99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 1 0.01% 99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.01% 99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 4 0.06% 99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 1 0.01% 99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 7 0.10% 99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 5 0.07% 99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 2 0.03% 99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 2 0.03% 99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 5 0.07% 99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 9 0.13% 99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 1 0.01% 99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 5 0.07% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 2 0.03% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 3 0.04% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 1 0.01% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 3 0.04% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6824 # Writes before turning the bus around for reads
-system.physmem.totQLat 10004432906 # Total ticks spent queuing
-system.physmem.totMemAccLat 13637470406 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 968810000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 51632.32 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 70382.22 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 4.39 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 4.33 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.06 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.32 # Average write queue length when enqueuing
-system.physmem.readRowHits 161584 # Number of row buffer hits during reads
-system.physmem.writeRowHits 85488 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.39 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 62.02 # Row buffer hit rate for writes
-system.physmem.avgGap 8421010.84 # Average gap between requests
-system.physmem.pageHitRate 74.51 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 316830360 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 168399330 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 723046380 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 373908600 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 4521291840.000001 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 4723358580 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 248942400 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 9096613470 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 6505168320 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 667621594905 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 694301661855 # Total energy per rank (pJ)
-system.physmem_0.averagePower 245.625060 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 2815660418258 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 439528927 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1920369500 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 2778771385500 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 16940567035 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 8652241815 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 19948465723 # Time in different power states
-system.physmem_1.actEnergy 286542480 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 152300940 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 660414300 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 345490920 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 4558170240.000001 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 4719582900 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 238189440 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 8751236790 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 6789483360 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 667674392880 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 694177600920 # Total energy per rank (pJ)
-system.physmem_1.averagePower 245.581186 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 2815698296531 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 410333187 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1936500000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 2778826050750 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 17681028809 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 8627428782 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 19191216972 # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 23882865 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 15636955 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 931558 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 14470894 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 9520533 # Number of BTB hits
-system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 65.790911 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 3844072 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 34146 # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups 1359371 # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits 1203202 # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses 156169 # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted 49075 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks 66298 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 66298 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25087 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 19168 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 22043 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 44255 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 493.831206 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 3088.958464 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-8191 43053 97.28% 97.28% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::8192-16383 899 2.03% 99.32% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-24575 141 0.32% 99.63% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::24576-32767 95 0.21% 99.85% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-40959 32 0.07% 99.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::57344-65535 14 0.03% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 44255 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 16149 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 11407.424608 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 9685.730755 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 9901.207568 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383 14668 90.83% 90.83% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1230 7.62% 98.45% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151 211 1.31% 99.75% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535 16 0.10% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.02% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::114688-131071 4 0.02% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::229376-245759 17 0.11% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 16149 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 86482404152 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.594104 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.503301 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 86424292152 99.93% 99.93% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3 40499500 0.05% 99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5 7958000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7 4655000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9 1502500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11 969000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13 1099000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15 1428000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17 1000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 86482404152 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 5106 78.70% 78.70% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1382 21.30% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 6488 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66298 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66298 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6488 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6488 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 72786 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.inst_hits 0 # ITB inst hits
-system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 17693188 # DTB read hits
-system.cpu0.dtb.read_misses 55688 # DTB read misses
-system.cpu0.dtb.write_hits 14580631 # DTB write hits
-system.cpu0.dtb.write_misses 10610 # DTB write misses
-system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 159 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 2213 # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 845 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 17748876 # DTB read accesses
-system.cpu0.dtb.write_accesses 14591241 # DTB write accesses
-system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 32273819 # DTB hits
-system.cpu0.dtb.misses 66298 # DTB misses
-system.cpu0.dtb.accesses 32340117 # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks 11677 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 11677 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3850 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6772 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore 1055 # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples 10622 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean 1021.559028 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 3971.298769 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-4095 9829 92.53% 92.53% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::4096-8191 232 2.18% 94.72% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-12287 234 2.20% 96.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::12288-16383 118 1.11% 98.03% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-20479 84 0.79% 98.82% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::20480-24575 68 0.64% 99.46% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-28671 21 0.20% 99.66% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::28672-32767 17 0.16% 99.82% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-36863 11 0.10% 99.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::36864-40959 4 0.04% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::49152-53247 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 10622 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 3671 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12324.162354 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11375.149198 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 5369.602272 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191 593 16.15% 16.15% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383 2793 76.08% 92.24% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575 150 4.09% 96.32% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767 91 2.48% 98.80% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-40959 38 1.04% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.03% 99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.08% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 3671 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 22057105212 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 0.847252 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev 0.360404 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 3373925500 15.30% 15.30% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 18678889712 84.68% 99.98% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2 3873000 0.02% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3 379500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4 37500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 22057105212 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 2281 87.19% 87.19% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 335 12.81% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 2616 # Table walker page sizes translated
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11677 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11677 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2616 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2616 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 14293 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 37442886 # ITB inst hits
-system.cpu0.itb.inst_misses 11677 # ITB inst misses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2325 # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 2439 # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 37454563 # ITB inst accesses
-system.cpu0.itb.hits 37442886 # DTB hits
-system.cpu0.itb.misses 11677 # DTB misses
-system.cpu0.itb.accesses 37454563 # DTB accesses
-system.cpu0.numPwrStateTransitions 3670 # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples 1835 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean 1504014886.326976 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev 24031487578.448807 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows 1058 57.66% 57.66% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10 770 41.96% 99.62% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 499970835992 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total 1835 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON 66805242090 # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 2759867316410 # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles 133611951 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 19303849 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 111829084 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 23882865 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 14567807 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 107369786 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 2747392 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 153767 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 58387 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 435607 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 423633 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 97811 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 37442098 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 257331 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 6030 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 129216536 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.043099 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 1.255701 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 67189169 52.00% 52.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 21288743 16.48% 68.47% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 8719000 6.75% 75.22% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 32019624 24.78% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 129216536 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.178748 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.836969 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 19892285 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 62318410 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 41002144 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 4961574 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1042123 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 8668351 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 335752 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 109935605 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 3778741 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1042123 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 25542587 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 12841185 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 37729185 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 40176897 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 11884559 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 104971930 # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts 1005936 # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents 1490559 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 163297 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 57296 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 7681326 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 109147487 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 479167735 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 120008007 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 9453 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 98091135 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 11056341 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1226764 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 1083940 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 12369905 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 18622381 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 16045587 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1690063 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 2196173 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 102089116 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1690972 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 100270845 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 450536 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 9007472 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 21276029 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 120459 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 129216536 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.775991 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.026149 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 73187499 56.64% 56.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 23243158 17.99% 74.63% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 22432715 17.36% 91.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 9250445 7.16% 99.15% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1102673 0.85% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 46 0.00% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 129216536 # Number of insts issued each cycle
-system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 9305182 40.57% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 67 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMisc 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 5565388 24.27% 64.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 8055351 35.12% 99.96% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMemRead 2851 0.01% 99.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMemWrite 6938 0.03% 100.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 66163298 65.98% 65.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 92264 0.09% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 8058 0.01% 66.09% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 18375460 18.33% 84.41% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 15618206 15.58% 99.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMemRead 3108 0.00% 99.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMemWrite 8177 0.01% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 100270845 # Type of FU issued
-system.cpu0.iq.rate 0.750463 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 22935777 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.228738 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 353112143 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 112794988 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 98251090 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 32395 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 11310 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 9716 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 123183269 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 21080 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 364715 # Number of loads that had data forwarded from stores
-system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1893331 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2466 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 18814 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 881018 # Number of stores squashed
-system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 109546 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 360879 # Number of times an access to memory failed due to the cache being blocked
-system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1042123 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 1649895 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 244572 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 103932598 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 18622381 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 16045587 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 874828 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 27967 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 192686 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 18814 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 252890 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 404204 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 657094 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 99256545 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 17939836 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 948116 # Number of squashed instructions skipped in execute
-system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 152510 # number of nop insts executed
-system.cpu0.iew.exec_refs 33405569 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 16813883 # Number of branches executed
-system.cpu0.iew.exec_stores 15465733 # Number of stores executed
-system.cpu0.iew.exec_rate 0.742872 # Inst execution rate
-system.cpu0.iew.wb_sent 98711091 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 98260806 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 51187228 # num instructions producing a value
-system.cpu0.iew.wb_consumers 84552650 # num instructions consuming a value
-system.cpu0.iew.wb_rate 0.735419 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.605389 # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts 8010093 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 1570513 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 599985 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 127532122 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.744084 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.464109 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 83238506 65.27% 65.27% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 24683933 19.36% 84.62% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 8242078 6.46% 91.09% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 3223359 2.53% 93.61% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 3451127 2.71% 96.32% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 1466865 1.15% 97.47% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 1171264 0.92% 98.39% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 549844 0.43% 98.82% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1505146 1.18% 100.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 127532122 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 78880347 # Number of instructions committed
-system.cpu0.commit.committedOps 94894659 # Number of ops (including micro ops) committed
-system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 31893618 # Number of memory references committed
-system.cpu0.commit.loads 16729049 # Number of loads committed
-system.cpu0.commit.membars 646523 # Number of memory barriers committed
-system.cpu0.commit.branches 16211772 # Number of branches committed
-system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 81832780 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 1927003 # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 62903043 66.29% 66.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 89941 0.09% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 8057 0.01% 66.39% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 16726793 17.63% 84.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 15157121 15.97% 99.99% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMemWrite 7448 0.01% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 94894659 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 1505146 # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads 224742704 # The number of ROB reads
-system.cpu0.rob.rob_writes 207484818 # The number of ROB writes
-system.cpu0.timesIdled 136289 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 4395415 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 5519733867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 78758295 # Number of Instructions Simulated
-system.cpu0.committedOps 94772607 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 1.696481 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 1.696481 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.589455 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.589455 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 110218064 # number of integer regfile reads
-system.cpu0.int_regfile_writes 59484746 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 8170 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes
-system.cpu0.cc_regfile_reads 349694687 # number of cc regfile reads
-system.cpu0.cc_regfile_writes 40999571 # number of cc regfile writes
-system.cpu0.misc_regfile_reads 254801117 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 1223326 # number of misc regfile writes
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements 712506 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 498.213160 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 28740042 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 713018 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 40.307597 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 296154500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.213160 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.973073 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.973073 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 63341698 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 63341698 # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data 15523802 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 15523802 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 11993925 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 11993925 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307586 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 307586 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 362517 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 362517 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360768 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 360768 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 27517727 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 27517727 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 27825313 # number of overall hits
-system.cpu0.dcache.overall_hits::total 27825313 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 649486 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 649486 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1895154 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1895154 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148364 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 148364 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25286 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 25286 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20247 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 20247 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 2544640 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 2544640 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 2693004 # number of overall misses
-system.cpu0.dcache.overall_misses::total 2693004 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9367064500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 9367064500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33076385872 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 33076385872 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 412133000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 412133000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 479472000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 479472000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 454500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 454500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 42443450372 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 42443450372 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 42443450372 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 42443450372 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 16173288 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 16173288 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 13889079 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 13889079 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 455950 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 455950 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387803 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 387803 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381015 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 381015 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 30062367 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 30062367 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 30518317 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 30518317 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040158 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.040158 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136449 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.136449 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325395 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325395 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065203 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065203 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053140 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053140 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084645 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.084645 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088242 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.088242 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14422.273151 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14422.273151 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17453.138833 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 17453.138833 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16298.861030 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16298.861030 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23681.137946 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23681.137946 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16679.550102 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16679.550102 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15760.633988 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 15760.633988 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 689 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 4988118 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 32 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 201830 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.531250 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 24.714453 # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks 712509 # number of writebacks
-system.cpu0.dcache.writebacks::total 712509 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 261058 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 261058 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1569543 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1569543 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18570 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18570 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830601 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 1830601 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1830601 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 1830601 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388428 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 388428 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325611 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 325611 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102372 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 102372 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6716 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6716 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20247 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 20247 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 714039 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 714039 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 816411 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 816411 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20577 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19269 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19269 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39846 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5013254500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5013254500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6647950897 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6647950897 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1709667500 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1709667500 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 108314000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 108314000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 459237000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 459237000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 442500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 442500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11661205397 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 11661205397 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13370872897 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 13370872897 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4595503500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4595503500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4595503500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4595503500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024017 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024017 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023444 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023444 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224525 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224525 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017318 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017318 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053140 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053140 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023752 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.023752 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026752 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.026752 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12906.521929 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12906.521929 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20416.849852 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20416.849852 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16700.538233 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16700.538233 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16127.754616 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16127.754616 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22681.730627 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22681.730627 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16331.328397 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16331.328397 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16377.624624 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16377.624624 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223332.045488 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223332.045488 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115331.614215 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115331.614215 # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements 1246758 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.757641 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 36137139 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1247269 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 28.973011 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 6586723000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757641 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999527 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 76124237 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 76124237 # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst 36137142 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 36137142 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 36137142 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 36137142 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 36137142 # number of overall hits
-system.cpu0.icache.overall_hits::total 36137142 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 1301318 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 1301318 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 1301318 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 1301318 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 1301318 # number of overall misses
-system.cpu0.icache.overall_misses::total 1301318 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14070925518 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 14070925518 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 14070925518 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 14070925518 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 14070925518 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 14070925518 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 37438460 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 37438460 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 37438460 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 37438460 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 37438460 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 37438460 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034759 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.034759 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034759 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.034759 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034759 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.034759 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10812.826318 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10812.826318 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10812.826318 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10812.826318 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10812.826318 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10812.826318 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 1742114 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 1649 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 114160 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.260284 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets 126.846154 # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks 1246758 # number of writebacks
-system.cpu0.icache.writebacks::total 1246758 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54000 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 54000 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 54000 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 54000 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 54000 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 54000 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1247318 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 1247318 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 1247318 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 1247318 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 1247318 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 1247318 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total 3008 # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total 3008 # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12734729518 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 12734729518 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12734729518 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 12734729518 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12734729518 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 12734729518 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 287646998 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 287646998 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 287646998 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total 287646998 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033316 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033316 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033316 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.033316 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033316 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.033316 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10209.689524 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10209.689524 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10209.689524 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10209.689524 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10209.689524 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10209.689524 # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95627.326463 # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95627.326463 # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued 1845705 # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified 1848223 # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit 2284 # number of redundant prefetches already in prefetch queue
-system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage 235089 # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements 270085 # number of replacements
-system.cpu0.l2cache.tags.tagsinuse 15641.965642 # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs 1885208 # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs 285711 # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs 6.598304 # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 14498.888394 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.509265 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.944405 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1130.623578 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks 0.884942 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000702 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000058 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.069008 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total 0.954710 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022 275 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15342 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 64 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 136 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 282 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1456 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7618 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4683 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1303 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.016785 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936401 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses 67537653 # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses 67537653 # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55283 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 14603 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total 69886 # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks 482862 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total 482862 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks 1445066 # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total 1445066 # number of WritebackClean hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data 220992 # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total 220992 # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1177410 # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total 1177410 # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 389847 # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total 389847 # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55283 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker 14603 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst 1177410 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data 610839 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total 1858135 # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55283 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker 14603 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst 1177410 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data 610839 # number of overall hits
-system.cpu0.l2cache.overall_hits::total 1858135 # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 528 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 200 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total 728 # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55774 # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total 55774 # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20246 # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total 20246 # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data 49029 # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total 49029 # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 69866 # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total 69866 # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 107548 # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total 107548 # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 528 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker 200 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst 69866 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data 156577 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total 227171 # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 528 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker 200 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst 69866 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data 156577 # number of overall misses
-system.cpu0.l2cache.overall_misses::total 227171 # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 17967500 # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4680500 # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total 22648000 # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 38083500 # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total 38083500 # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9705500 # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9705500 # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 424500 # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 424500 # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3399006998 # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total 3399006998 # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3707068000 # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3707068000 # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3498037999 # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3498037999 # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 17967500 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4680500 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3707068000 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data 6897044997 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total 10626760997 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 17967500 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4680500 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3707068000 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data 6897044997 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total 10626760997 # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55811 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 14803 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total 70614 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks 482862 # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total 482862 # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks 1445066 # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total 1445066 # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55774 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total 55774 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20246 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total 20246 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270021 # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total 270021 # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1247276 # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total 1247276 # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 497395 # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total 497395 # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55811 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 14803 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst 1247276 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data 767416 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total 2085306 # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55811 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 14803 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst 1247276 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data 767416 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total 2085306 # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009461 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.013511 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total 0.010310 # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.181575 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total 0.181575 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056015 # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056015 # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.216223 # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.216223 # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009461 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.013511 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056015 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.204031 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total 0.108939 # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009461 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.013511 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056015 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.204031 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total 0.108939 # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34029.356061 # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23402.500000 # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31109.890110 # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 682.818159 # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 682.818159 # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 479.378643 # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 479.378643 # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 424500 # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 424500 # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69326.459810 # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69326.459810 # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53059.685684 # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53059.685684 # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32525.365409 # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32525.365409 # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34029.356061 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23402.500000 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53059.685684 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44048.902438 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 46778.686527 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34029.356061 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23402.500000 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53059.685684 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44048.902438 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 46778.686527 # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs 192 # number of cycles access was blocked
-system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches 10583 # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks 229428 # number of writebacks
-system.cpu0.l2cache.writebacks::total 229428 # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5884 # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total 5884 # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 42 # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 42 # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 782 # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 782 # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 2 # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 42 # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6666 # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total 6712 # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 2 # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 42 # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6666 # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total 6712 # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 526 # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 198 # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total 724 # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262267 # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total 262267 # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55774 # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55774 # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20246 # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20246 # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43145 # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total 43145 # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 69824 # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 69824 # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 106766 # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 106766 # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 526 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 198 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 69824 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data 149911 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total 220459 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 526 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 198 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 69824 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data 149911 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262267 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total 482726 # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23585 # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19269 # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19269 # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 42854 # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 14785500 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3455500 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 18241000 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17281059402 # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17281059402 # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 963844000 # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 963844000 # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 306251499 # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 306251499 # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 352500 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 352500 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2242873000 # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2242873000 # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3286309500 # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3286309500 # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2812269499 # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2812269499 # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 14785500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3455500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3286309500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5055142499 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total 8359692999 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 14785500 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3455500 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3286309500 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5055142499 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17281059402 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 25640752401 # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265086000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4430574500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4695660500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 265086000 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4430574500 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4695660500 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009425 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013376 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010253 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159784 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159784 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.055981 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.055981 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.214650 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.214650 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009425 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013376 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.055981 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.195345 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.105720 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009425 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013376 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.055981 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.195345 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231489 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28109.315589 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17452.020202 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25194.751381 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65891.093435 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65891.093435 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17281.242156 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17281.242156 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15126.518769 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15126.518769 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 352500 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 352500 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 51984.540503 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 51984.540503 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47065.614975 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47065.614975 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26340.496965 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26340.496965 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28109.315589 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17452.020202 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47065.614975 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33720.957762 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37919.490694 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28109.315589 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17452.020202 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47065.614975 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33720.957762 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65891.093435 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53116.576279 # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215316.834330 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 199095.208819 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111192.453446 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109573.447053 # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests 4070347 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2055545 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32650 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 214495 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212607 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1888 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq 104418 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 1897981 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 19269 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 19269 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 712665 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 1476401 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 88407 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 330099 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 87722 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42827 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 113743 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 288516 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 284937 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1247318 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 587795 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 3260 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 16 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3747367 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2580614 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 32197 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119234 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 6479412 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 159666240 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98907572 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 59212 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223244 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 258856268 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 926807 # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic 18833272 # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples 3029449 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.088921 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.286812 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 2761954 91.17% 91.17% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 265607 8.77% 99.94% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 1888 0.06% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 3029449 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 4055747992 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 114619003 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 1874463037 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1221112489 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 17401984 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 63454935 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 33856624 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 11500186 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 284574 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 18698220 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 5965214 # Number of BTB hits
-system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 31.902577 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 12503434 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 7767 # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups 9010077 # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits 8973983 # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses 36094 # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted 10763 # Number of mispredicted indirect branches.
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks 21842 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 21842 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8830 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5887 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 7125 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 14717 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 626.588299 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 3443.893339 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-4095 14047 95.45% 95.45% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::4096-8191 191 1.30% 96.75% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::8192-12287 228 1.55% 98.29% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::12288-16383 115 0.78% 99.08% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-20479 21 0.14% 99.22% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::20480-24575 23 0.16% 99.37% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::24576-28671 7 0.05% 99.42% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::28672-32767 61 0.41% 99.84% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-36863 9 0.06% 99.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::36864-40959 3 0.02% 99.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::40960-45055 7 0.05% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::57344-61439 4 0.03% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 14717 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 5501 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11163.061262 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 9675.830911 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 6263.258432 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191 1953 35.50% 35.50% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2904 52.79% 88.29% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575 452 8.22% 96.51% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767 149 2.71% 99.22% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959 15 0.27% 99.49% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151 22 0.40% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-57343 4 0.07% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 5501 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 77610116560 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.192083 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.397646 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 62747643816 80.85% 80.85% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 14840857744 19.12% 99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2 12907000 0.02% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::3 3989500 0.01% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4 1311000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::5 947500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6 1279000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::7 355000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8 209000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::9 144500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10 123000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::11 26500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12 158000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::13 24500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14 7000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::15 133500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 77610116560 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 1910 75.26% 75.26% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 628 24.74% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 2538 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21842 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21842 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2538 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2538 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 24380 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.inst_hits 0 # ITB inst hits
-system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 10130559 # DTB read hits
-system.cpu1.dtb.read_misses 18924 # DTB read misses
-system.cpu1.dtb.write_hits 6492882 # DTB write hits
-system.cpu1.dtb.write_misses 2918 # DTB write misses
-system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1948 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 62 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 418 # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 414 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 10149483 # DTB read accesses
-system.cpu1.dtb.write_accesses 6495800 # DTB write accesses
-system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 16623441 # DTB hits
-system.cpu1.dtb.misses 21842 # DTB misses
-system.cpu1.dtb.accesses 16645283 # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks 6562 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 6562 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2897 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 3033 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore 632 # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples 5930 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean 575.716695 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 2785.933852 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-4095 5654 95.35% 95.35% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::4096-8191 104 1.75% 97.10% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-12287 84 1.42% 98.52% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::12288-16383 46 0.78% 99.29% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-20479 13 0.22% 99.51% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::20480-24575 9 0.15% 99.66% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-28671 14 0.24% 99.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::28672-32767 3 0.05% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-36863 2 0.03% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::36864-40959 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 5930 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 1787 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12039.171796 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 10885.386949 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 5807.969289 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191 326 18.24% 18.24% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383 1260 70.51% 88.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575 112 6.27% 95.02% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767 73 4.09% 99.10% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.28% 99.38% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151 6 0.34% 99.72% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.22% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 1787 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 17460932916 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean 0.922072 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev 0.268326 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 1361890264 7.80% 7.80% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1 16097906652 92.19% 99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2 1078000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3 58000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 17460932916 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 986 85.37% 85.37% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 169 14.63% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 1155 # Table walker page sizes translated
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6562 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6562 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1155 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1155 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 7717 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 43481037 # ITB inst hits
-system.cpu1.itb.inst_misses 6562 # ITB inst misses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1123 # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 565 # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 43487599 # ITB inst accesses
-system.cpu1.itb.hits 43481037 # DTB hits
-system.cpu1.itb.misses 6562 # DTB misses
-system.cpu1.itb.accesses 43487599 # DTB accesses
-system.cpu1.numPwrStateTransitions 5583 # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples 2792 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean 993380119.566619 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev 25601801103.735863 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows 1979 70.88% 70.88% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10 809 28.98% 99.86% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 959983178648 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total 2792 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON 53155264670 # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 2773517293830 # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles 106311330 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 10498191 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 108665043 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 33856624 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 27442631 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 92291638 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3748932 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 86712 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 30975 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 185919 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 298023 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 23349 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 43479865 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 112855 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 2560 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 105289273 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.278878 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.339497 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 48625526 46.18% 46.18% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 13920511 13.22% 59.40% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 7498101 7.12% 66.53% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 35245135 33.47% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 105289273 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.318467 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 1.022140 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 13318727 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 62566078 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 26583147 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 1076022 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1745299 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 4334852 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 132018 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 67655162 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 1099039 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 1745299 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 17698509 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 2385948 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 57515508 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 23258780 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 2685229 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 54782270 # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts 214949 # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents 261715 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 37045 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 16294 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 1684754 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands 54670319 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 258827504 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 58243055 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 52176795 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 2493524 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1869295 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 1798183 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 13052424 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 10386014 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 6834101 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 620797 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 744232 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 53921335 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 577687 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 53701083 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 93984 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 3580846 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 5052182 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 42977 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 105289273 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.510034 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 0.848273 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 72135914 68.51% 68.51% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 16498960 15.67% 84.18% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 13045494 12.39% 96.57% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 3324500 3.16% 99.73% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 284390 0.27% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 15 0.00% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 105289273 # Number of insts issued each cycle
-system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 2891632 45.26% 45.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 674 0.01% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMisc 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 1660257 25.99% 71.25% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 1834987 28.72% 99.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMemRead 656 0.01% 99.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMemWrite 1067 0.02% 100.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 36615420 68.18% 68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 46378 0.09% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 3321 0.01% 68.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 10339913 19.25% 87.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 6693876 12.47% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMemRead 720 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMemWrite 1389 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 53701083 # Type of FU issued
-system.cpu1.iq.rate 0.505130 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 6389273 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.118978 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 219168744 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 58087331 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 51738316 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 5952 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 2080 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 1787 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 60086458 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 3832 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 90387 # Number of loads that had data forwarded from stores
-system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 431562 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 735 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 9576 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 270603 # Number of stores squashed
-system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 51945 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 76138 # Number of times an access to memory failed due to the cache being blocked
-system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1745299 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 526771 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 105542 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 54540026 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 10386014 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 6834101 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 292206 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 7827 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 90888 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 9576 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 43509 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 122774 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 166283 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 53458422 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 10243364 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 220834 # Number of squashed instructions skipped in execute
-system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 41004 # number of nop insts executed
-system.cpu1.iew.exec_refs 16887479 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 11797622 # Number of branches executed
-system.cpu1.iew.exec_stores 6644115 # Number of stores executed
-system.cpu1.iew.exec_rate 0.502848 # Inst execution rate
-system.cpu1.iew.wb_sent 53318700 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 51740103 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 25143993 # num instructions producing a value
-system.cpu1.iew.wb_consumers 38375917 # num instructions consuming a value
-system.cpu1.iew.wb_rate 0.486685 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.655202 # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts 3338971 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 534710 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 155407 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 103400366 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.492755 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.151487 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 77772385 75.21% 75.21% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 14344116 13.87% 89.09% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 6076791 5.88% 94.96% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 698306 0.68% 95.64% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1980317 1.92% 97.55% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 1651720 1.60% 99.15% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 355943 0.34% 99.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 123415 0.12% 99.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 397373 0.38% 100.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 103400366 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 41357318 # Number of instructions committed
-system.cpu1.commit.committedOps 50951031 # Number of ops (including micro ops) committed
-system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 16517950 # Number of memory references committed
-system.cpu1.commit.loads 9954452 # Number of loads committed
-system.cpu1.commit.membars 209769 # Number of memory barriers committed
-system.cpu1.commit.branches 11645067 # Number of branches committed
-system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 45808028 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 3371132 # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 34384478 67.49% 67.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 45282 0.09% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 3321 0.01% 67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 9953936 19.54% 87.12% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 6562230 12.88% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMemRead 516 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMemWrite 1268 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 50951031 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 397373 # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads 137214928 # The number of ROB reads
-system.cpu1.rob.rob_writes 110460111 # The number of ROB writes
-system.cpu1.timesIdled 59286 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 1022057 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 5546467999 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 41324462 # Number of Instructions Simulated
-system.cpu1.committedOps 50918175 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 2.572600 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 2.572600 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.388712 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.388712 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 56077052 # number of integer regfile reads
-system.cpu1.int_regfile_writes 35632532 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 1385 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 516 # number of floating regfile writes
-system.cpu1.cc_regfile_reads 190521590 # number of cc regfile reads
-system.cpu1.cc_regfile_writes 15513949 # number of cc regfile writes
-system.cpu1.misc_regfile_reads 212156067 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 383841 # number of misc regfile writes
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements 187625 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 471.246001 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 15706444 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 187980 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 83.553804 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 89314291000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.246001 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920402 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.920402 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.693359 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 32901851 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 32901851 # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data 9540637 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 9540637 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 5911714 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 5911714 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49749 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 49749 # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78973 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 78973 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71099 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 71099 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 15452351 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 15452351 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 15502100 # number of overall hits
-system.cpu1.dcache.overall_hits::total 15502100 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 214896 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 214896 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 395681 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 395681 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30189 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 30189 # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18483 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 18483 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23644 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 23644 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 610577 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 610577 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 640766 # number of overall misses
-system.cpu1.dcache.overall_misses::total 640766 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3583570500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 3583570500 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10071608465 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 10071608465 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363005500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 363005500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 554928000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 554928000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 408500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 408500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 13655178965 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 13655178965 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 13655178965 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 13655178965 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 9755533 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 9755533 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 6307395 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 6307395 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79938 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 79938 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97456 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 97456 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94743 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 94743 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 16062928 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 16062928 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 16142866 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 16142866 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022028 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.022028 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062733 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.062733 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377655 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377655 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.189655 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.189655 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249559 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249559 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038012 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.038012 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039693 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.039693 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16675.836218 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16675.836218 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25453.859207 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 25453.859207 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19639.966456 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19639.966456 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23470.140416 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23470.140416 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22364.384779 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 22364.384779 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21310.710876 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 21310.710876 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 381 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 1471779 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 29 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 39630 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.137931 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 37.138002 # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks 187625 # number of writebacks
-system.cpu1.dcache.writebacks::total 187625 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 78547 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 78547 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 305511 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 305511 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13157 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13157 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 384058 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 384058 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 384058 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 384058 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136349 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 136349 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90170 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 90170 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28879 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 28879 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5326 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5326 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23644 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 23644 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 226519 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 226519 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 255398 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 255398 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14314 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14314 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11648 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11648 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 25962 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 25962 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988454500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1988454500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2445262471 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2445262471 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 492196500 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 492196500 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93636000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93636000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 531294000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 531294000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 398500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 398500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4433716971 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 4433716971 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4925913471 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 4925913471 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2472670000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2472670000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2472670000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2472670000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013977 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013977 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014296 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014296 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361267 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361267 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054650 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054650 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249559 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249559 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014102 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.014102 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015821 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.015821 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14583.564969 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14583.564969 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27118.359443 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27118.359443 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17043.405243 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17043.405243 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17580.923770 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17580.923770 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22470.563356 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22470.563356 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19573.267457 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19573.267457 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19287.204563 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19287.204563 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172744.865167 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172744.865167 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95241.891996 # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95241.891996 # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements 599092 # number of replacements
-system.cpu1.icache.tags.tagsinuse 499.435973 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 42856272 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 599604 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 71.474293 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 79139515500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.435973 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975461 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.975461 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 87558770 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 87558770 # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst 42856272 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 42856272 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 42856272 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 42856272 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 42856272 # number of overall hits
-system.cpu1.icache.overall_hits::total 42856272 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 623309 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 623309 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 623309 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 623309 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 623309 # number of overall misses
-system.cpu1.icache.overall_misses::total 623309 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5905173986 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 5905173986 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 5905173986 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 5905173986 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 5905173986 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 5905173986 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 43479581 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 43479581 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 43479581 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 43479581 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 43479581 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 43479581 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014336 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.014336 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014336 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.014336 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014336 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.014336 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9473.910991 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 9473.910991 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9473.910991 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 9473.910991 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9473.910991 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 9473.910991 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 533657 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 290 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 42078 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.682566 # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets 290 # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks 599092 # number of writebacks
-system.cpu1.icache.writebacks::total 599092 # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 23701 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 23701 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 23701 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 23701 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 23701 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 23701 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 599608 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 599608 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 599608 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 599608 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 599608 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 599608 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable
-system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable
-system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses
-system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5403181271 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 5403181271 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5403181271 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 5403181271 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5403181271 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 5403181271 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9499999 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9499999 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9499999 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 9499999 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013791 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013791 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013791 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.013791 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013791 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.013791 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9011.189429 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9011.189429 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9011.189429 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 9011.189429 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9011.189429 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 9011.189429 # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94059.396040 # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94059.396040 # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94059.396040 # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94059.396040 # average overall mshr uncacheable latency
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued 194821 # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified 195463 # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit 575 # number of redundant prefetches already in prefetch queue
-system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage 59841 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements 44456 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 14684.761874 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 706823 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 58616 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 12.058534 # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14300.099102 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.020323 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.955758 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 371.686691 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks 0.872809 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000612 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000180 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.022686 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total 0.896287 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022 332 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023 32 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13796 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 10 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 205 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 117 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1791 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8656 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3349 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020264 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.842041 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses 27731086 # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses 27731086 # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17081 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7133 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total 24214 # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks 114521 # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total 114521 # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks 659711 # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total 659711 # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27226 # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total 27226 # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 575115 # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total 575115 # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98702 # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total 98702 # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17081 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7133 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst 575115 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data 125928 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total 725257 # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17081 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7133 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst 575115 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data 125928 # number of overall hits
-system.cpu1.l2cache.overall_hits::total 725257 # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 517 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 296 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total 813 # number of ReadReq misses
-system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses
-system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29667 # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total 29667 # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23643 # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total 23643 # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33950 # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total 33950 # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 24491 # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total 24491 # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 71832 # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total 71832 # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 517 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker 296 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst 24491 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data 105782 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total 131086 # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 517 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker 296 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst 24491 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data 105782 # number of overall misses
-system.cpu1.l2cache.overall_misses::total 131086 # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 11135000 # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6028000 # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total 17163000 # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 12712500 # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total 12712500 # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 18521500 # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 18521500 # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 382999 # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 382999 # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1470067999 # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total 1470067999 # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1003037500 # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1003037500 # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1657187499 # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1657187499 # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 11135000 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6028000 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1003037500 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data 3127255498 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total 4147455998 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 11135000 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6028000 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1003037500 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data 3127255498 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total 4147455998 # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17598 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7429 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total 25027 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114522 # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total 114522 # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks 659711 # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total 659711 # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29667 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total 29667 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23643 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total 23643 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61176 # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total 61176 # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 599606 # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total 599606 # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 170534 # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total 170534 # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17598 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7429 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst 599606 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data 231710 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total 856343 # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17598 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7429 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst 599606 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data 231710 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total 856343 # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.029378 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.039844 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total 0.032485 # miss rate for ReadReq accesses
-system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000009 # miss rate for WritebackDirty accesses
-system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000009 # miss rate for WritebackDirty accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.554956 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total 0.554956 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040845 # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040845 # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.421218 # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.421218 # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.029378 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.039844 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040845 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.456528 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total 0.153077 # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.029378 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.039844 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040845 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.456528 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total 0.153077 # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21537.717602 # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20364.864865 # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21110.701107 # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 428.506421 # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 428.506421 # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 783.381974 # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 783.381974 # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 382999 # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 382999 # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43300.971988 # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43300.971988 # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40955.350945 # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40955.350945 # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23070.323797 # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23070.323797 # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21537.717602 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20364.864865 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40955.350945 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29563.210168 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 31639.198679 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21537.717602 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20364.864865 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40955.350945 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29563.210168 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 31639.198679 # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs 182 # number of cycles access was blocked
-system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30.333333 # average number of cycles each access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches 827 # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks 31720 # number of writebacks
-system.cpu1.l2cache.writebacks::total 31720 # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 426 # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total 426 # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 7 # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 74 # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 74 # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data 500 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total 509 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data 500 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total 509 # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 516 # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 295 # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total 811 # number of ReadReq MSHR misses
-system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses
-system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25186 # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total 25186 # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29667 # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29667 # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23643 # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23643 # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33524 # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total 33524 # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 24484 # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 24484 # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 71758 # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 71758 # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 516 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 295 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 24484 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data 105282 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total 130577 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 516 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 295 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 24484 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data 105282 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25186 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total 155763 # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14314 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14415 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11648 # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11648 # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 25962 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26063 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8020500 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4240500 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 12261000 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1092841786 # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1092841786 # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 456571000 # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 456571000 # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 353660000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 353660000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 322999 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 322999 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1211819000 # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1211819000 # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 855998500 # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 855998500 # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1224293499 # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1224293499 # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8020500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4240500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 855998500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2436112499 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total 3304371999 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8020500 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4240500 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 855998500 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2436112499 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1092841786 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total 4397213785 # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8742000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2358114500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2366856500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8742000 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2358114500 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2366856500 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.029322 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.039709 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032405 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000009 # mshr miss rate for WritebackDirty accesses
-system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000009 # mshr miss rate for WritebackDirty accesses
-system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.547993 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.547993 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.040833 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040833 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.420784 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.420784 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.029322 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.039709 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.040833 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454370 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152482 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.029322 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.039709 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.040833 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454370 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181893 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15543.604651 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14374.576271 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15118.372380 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43390.843564 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43390.843564 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15389.860788 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15389.860788 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14958.338620 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14958.338620 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 322999 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 322999 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36147.804558 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.804558 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34961.546316 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34961.546316 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17061.421709 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17061.421709 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15543.604651 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14374.576271 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34961.546316 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23138.926873 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25305.926764 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15543.604651 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14374.576271 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34961.546316 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23138.926873 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43390.843564 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28230.155974 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86554.455446 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164741.826184 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164193.999306 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86554.455446 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90829.462291 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90812.895676 # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests 1681326 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 850022 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12491 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 115149 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106381 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8768 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq 43982 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 852476 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 11648 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 11648 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 147635 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 672194 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 29901 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 30357 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 73327 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42065 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 86118 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 68535 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 65700 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 599608 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 274791 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 374 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1798508 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 885295 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 16392 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38202 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 2738397 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 76718288 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29683872 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29716 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70392 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 106502268 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 347702 # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic 4882288 # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples 1207717 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.121214 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.347910 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 1070093 88.60% 88.60% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 128856 10.67% 99.27% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 8768 0.73% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1207717 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 1656031495 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 80775328 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 899618286 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 396030671 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 8974477 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 20614978 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 31012 # Transaction distribution
-system.iobus.trans_dist::ReadResp 31012 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59420 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59420 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56598 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71542 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 162792 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2484040 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 40387001 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 330000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 574500 # Layer occupancy (ticks)
-system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 53000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6115000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 33791000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 187784301 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 84716000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 36458 # number of replacements
-system.iocache.tags.tagsinuse 14.554359 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 255387586000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 14.554359 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.909647 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.909647 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 328284 # Number of tag accesses
-system.iocache.tags.data_accesses 328284 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
-system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses
-system.iocache.demand_misses::total 36476 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide 36476 # number of overall misses
-system.iocache.overall_misses::total 36476 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 40605876 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 40605876 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 4346476425 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 4346476425 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 4387082301 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 4387082301 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 4387082301 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 4387082301 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 161134.428571 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 161134.428571 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119988.858906 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 119988.858906 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 120273.119339 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 120273.119339 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 120273.119339 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 120273.119339 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 191 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 63.666667 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 36206 # number of writebacks
-system.iocache.writebacks::total 36206 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 28005876 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 28005876 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2533401277 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 2533401277 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 2561407153 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 2561407153 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 2561407153 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 2561407153 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 111134.428571 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 111134.428571 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69937.093557 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69937.093557 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 70221.711619 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70221.711619 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 70221.711619 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70221.711619 # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements 137443 # number of replacements
-system.l2c.tags.tagsinuse 65137.298659 # Cycle average of tags in use
-system.l2c.tags.total_refs 547823 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 202801 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 2.701284 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 87493786000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 6068.008119 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.951872 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 1.052619 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 7988.261154 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 6937.855049 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37116.430492 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 3.708460 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909745 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 1897.444635 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 3115.453147 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1993.223368 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.092590 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000228 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.121891 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.105863 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.566352 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000057 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.028953 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.047538 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030414 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.993916 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022 33259 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 32074 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2 185 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3 5974 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4 27100 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 4863 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 27079 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022 0.507492 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023 0.000381 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.489410 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 6288814 # Number of tag accesses
-system.l2c.tags.data_accesses 6288814 # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks 261149 # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total 261149 # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data 41513 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 4842 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 46355 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 2681 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 2272 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 4953 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 4003 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 1563 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 5566 # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 282 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker 80 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst 50115 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data 57309 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46378 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 44 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker 17 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst 21480 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data 11675 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4930 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 192310 # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 282 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 80 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 50115 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 61312 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher 46378 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 44 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 17 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 21480 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 13238 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher 4930 # number of demand (read+write) hits
-system.l2c.demand_hits::total 197876 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 282 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 80 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 50115 # number of overall hits
-system.l2c.overall_hits::cpu0.data 61312 # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher 46378 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 44 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 17 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 21480 # number of overall hits
-system.l2c.overall_hits::cpu1.data 13238 # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher 4930 # number of overall hits
-system.l2c.overall_hits::total 197876 # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data 453 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 282 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 735 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 99 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 81 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 180 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 11239 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 8266 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 19505 # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 29 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst 19709 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data 9351 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131214 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 7 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst 3001 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data 1024 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6755 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total 171094 # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 19709 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 20590 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher 131214 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker 7 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 3001 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 9290 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher 6755 # number of demand (read+write) misses
-system.l2c.demand_misses::total 190599 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 29 # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 19709 # number of overall misses
-system.l2c.overall_misses::cpu0.data 20590 # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher 131214 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 7 # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 3001 # number of overall misses
-system.l2c.overall_misses::cpu1.data 9290 # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher 6755 # number of overall misses
-system.l2c.overall_misses::total 190599 # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data 8930500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 709000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 9639500 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 540000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 293500 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 833500 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 1649495000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 781758500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 2431253500 # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 5602000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 249000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2048083000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data 1082250500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16438409497 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 622500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 89500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst 340295000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data 119337000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 980449226 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 21015387223 # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker 5602000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker 249000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 2048083000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 2731745500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16438409497 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker 622500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker 89500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 340295000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 901095500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 980449226 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 23446640723 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker 5602000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker 249000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 2048083000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 2731745500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16438409497 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker 622500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker 89500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 340295000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 901095500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 980449226 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 23446640723 # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks 261149 # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total 261149 # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 41966 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 5124 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 47090 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 2780 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 2353 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 5133 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 15242 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 9829 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 25071 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 311 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 83 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst 69824 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data 66660 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177592 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 51 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 18 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst 24481 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data 12699 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11685 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total 363404 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 311 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 83 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 69824 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 81902 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177592 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 51 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 18 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 24481 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 22528 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11685 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 388475 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 311 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 83 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 69824 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 81902 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177592 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 51 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 18 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 24481 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 22528 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11685 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 388475 # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.010794 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.055035 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.015608 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.035612 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.034424 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.035067 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.737370 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.840981 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.777991 # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.093248 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.036145 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.282267 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.140279 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738851 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.137255 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.055556 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.122585 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.080636 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.578092 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total 0.470809 # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.093248 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.036145 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.282267 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.251398 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738851 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.137255 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker 0.055556 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.122585 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.412376 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.578092 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.490634 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.093248 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.036145 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.282267 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.251398 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738851 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.137255 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker 0.055556 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.122585 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.412376 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.578092 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.490634 # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19714.128035 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2514.184397 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 13114.965986 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5454.545455 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3623.456790 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 4630.555556 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 146765.281609 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 94575.187515 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 124647.705716 # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 193172.413793 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 83000 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 103916.129687 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 115736.338360 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 125279.387085 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 88928.571429 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89500 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 113393.868710 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116540.039062 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 145144.222946 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 122829.481005 # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 193172.413793 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 103916.129687 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 132673.409422 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 125279.387085 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88928.571429 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89500 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 113393.868710 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 96996.286329 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 145144.222946 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 123015.549520 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 193172.413793 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 103916.129687 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 132673.409422 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 125279.387085 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88928.571429 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89500 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 113393.868710 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 96996.286329 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 145144.222946 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 123015.549520 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 153 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs 76.500000 # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks 101145 # number of writebacks
-system.l2c.writebacks::total 101145 # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 8 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 3 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total 12 # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks 4176 # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total 4176 # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data 453 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 282 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 735 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 99 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 81 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 180 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 11239 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 8266 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 19505 # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 29 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19701 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9351 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 131214 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 7 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2998 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1023 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6755 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total 171082 # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker 29 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 19701 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 20590 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 131214 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker 7 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 2998 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 9289 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6755 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 190587 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker 29 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 19701 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 20590 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 131214 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker 7 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 2998 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 9289 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6755 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 190587 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14311 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total 37997 # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19269 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11648 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total 30917 # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data 25959 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total 68914 # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 10270000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 6598500 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 16868500 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2606000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1791000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 4397000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1537104501 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 699098500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 2236203001 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 5312000 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 219000 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1850579001 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 988740500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15126263509 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 552500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 79500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 310216001 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 108988500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 912899226 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total 19303849737 # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 5312000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 219000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 1850579001 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 2525845001 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 15126263509 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 552500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 79500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 310216001 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 808087000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 912899226 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 21540052738 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 5312000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 219000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 1850579001 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 2525845001 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15126263509 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 552500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 79500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 310216001 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 808087000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 912899226 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 21540052738 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 210941500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4060149000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6923000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2100456000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 6378469500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 210941500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4060149000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6923000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2100456000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 6378469500 # number of overall MSHR uncacheable cycles
-system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
-system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.010794 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.055035 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.015608 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.035612 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.034424 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.035067 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.737370 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.840981 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.777991 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.093248 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.036145 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.282152 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.140279 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738851 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.137255 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.122462 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.080558 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578092 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.470776 # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.093248 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.036145 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.282152 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.251398 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738851 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.137255 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.122462 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.412331 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578092 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.490603 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.093248 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.036145 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.282152 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.251398 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738851 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.137255 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.122462 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.412331 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578092 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.490603 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22671.081678 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23398.936170 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22950.340136 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26323.232323 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 22111.111111 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24427.777778 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 136765.237210 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84575.187515 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 114647.680133 # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 183172.413793 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 93933.252170 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 105736.338360 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115279.341450 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 78928.571429 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 103474.316544 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106538.123167 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135144.222946 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112833.902672 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 183172.413793 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 93933.252170 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 122673.385187 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115279.341450 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78928.571429 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 103474.316544 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86993.971364 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135144.222946 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 113019.527764 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 183172.413793 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 93933.252170 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 122673.385187 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115279.341450 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78928.571429 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 103474.316544 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86993.971364 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135144.222946 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 113019.527764 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197314.914711 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 68544.554455 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146772.133324 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167867.713241 # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101896.024695 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 68544.554455 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80914.364960 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 92556.947790 # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests 505078 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 284284 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 621 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 37997 # Transaction distribution
-system.membus.trans_dist::ReadResp 209330 # Transaction distribution
-system.membus.trans_dist::WriteReq 30917 # Transaction distribution
-system.membus.trans_dist::WriteResp 30917 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 137351 # Transaction distribution
-system.membus.trans_dist::CleanEvict 16880 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 65170 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 38916 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
-system.membus.trans_dist::ReadExReq 39129 # Transaction distribution
-system.membus.trans_dist::ReadExResp 19493 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 171334 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 4604 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13758 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638434 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 760140 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 833089 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162792 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27516 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18718152 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 18908748 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 21226892 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 127972 # Total snoops (count)
-system.membus.snoopTraffic 36480 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 419691 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.012454 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.110902 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 414464 98.75% 98.75% # Request fanout histogram
-system.membus.snoop_fanout::1 5227 1.25% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 419691 # Request fanout histogram
-system.membus.reqLayer0.occupancy 81605499 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 11449000 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 986014542 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1099737525 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 7231369 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests 1045202 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 540825 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 201129 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 29372 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 28126 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 1246 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq 38000 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 522906 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 30917 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 30917 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 362294 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 129646 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 111513 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 43869 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 155382 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 50631 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 50631 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 484911 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 4651 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 3495 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1260717 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 366727 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1627444 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35956648 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5894436 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 41851084 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 396095 # Total snoops (count)
-system.toL2Bus.snoopTraffic 15886732 # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples 901981 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.407509 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.494174 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 535662 59.39% 59.39% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 365073 40.47% 99.86% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 1246 0.14% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 901981 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 896811514 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2185239 # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 675176627 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 261628851 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 1835 # number of quiesce instructions executed
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2792 # number of quiesce instructions executed
+sim_seconds 2.826662
+sim_ticks 2826661822500
+final_tick 2826661822500
+sim_freq 1000000000000
+host_inst_rate 165299
+host_op_rate 200549
+host_tick_rate 3891148832
+host_mem_usage 635692
+host_seconds 726.43
+sim_insts 120078679
+sim_ops 145685700
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.physmem.bytes_read::cpu0.dtb.walker 1920
+system.physmem.bytes_read::cpu0.itb.walker 192
+system.physmem.bytes_read::cpu0.inst 1308752
+system.physmem.bytes_read::cpu0.data 1307816
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 8391040
+system.physmem.bytes_read::cpu1.dtb.walker 320
+system.physmem.bytes_read::cpu1.itb.walker 64
+system.physmem.bytes_read::cpu1.inst 194400
+system.physmem.bytes_read::cpu1.data 594836
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 432000
+system.physmem.bytes_read::realview.ide 960
+system.physmem.bytes_read::total 12232300
+system.physmem.bytes_inst_read::cpu0.inst 1308752
+system.physmem.bytes_inst_read::cpu1.inst 194400
+system.physmem.bytes_inst_read::total 1503152
+system.physmem.bytes_written::writebacks 8791616
+system.physmem.bytes_written::cpu0.data 17524
+system.physmem.bytes_written::cpu1.data 40
+system.physmem.bytes_written::total 8809180
+system.physmem.num_reads::cpu0.dtb.walker 30
+system.physmem.num_reads::cpu0.itb.walker 3
+system.physmem.num_reads::cpu0.inst 22700
+system.physmem.num_reads::cpu0.data 20955
+system.physmem.num_reads::cpu0.l2cache.prefetcher 131110
+system.physmem.num_reads::cpu1.dtb.walker 5
+system.physmem.num_reads::cpu1.itb.walker 1
+system.physmem.num_reads::cpu1.inst 3105
+system.physmem.num_reads::cpu1.data 9315
+system.physmem.num_reads::cpu1.l2cache.prefetcher 6750
+system.physmem.num_reads::realview.ide 15
+system.physmem.num_reads::total 193989
+system.physmem.num_writes::writebacks 137369
+system.physmem.num_writes::cpu0.data 4381
+system.physmem.num_writes::cpu1.data 10
+system.physmem.num_writes::total 141760
+system.physmem.bw_read::cpu0.dtb.walker 679
+system.physmem.bw_read::cpu0.itb.walker 68
+system.physmem.bw_read::cpu0.inst 463003
+system.physmem.bw_read::cpu0.data 462672
+system.physmem.bw_read::cpu0.l2cache.prefetcher 2968533
+system.physmem.bw_read::cpu1.dtb.walker 113
+system.physmem.bw_read::cpu1.itb.walker 23
+system.physmem.bw_read::cpu1.inst 68774
+system.physmem.bw_read::cpu1.data 210438
+system.physmem.bw_read::cpu1.l2cache.prefetcher 152830
+system.physmem.bw_read::realview.ide 340
+system.physmem.bw_read::total 4327472
+system.physmem.bw_inst_read::cpu0.inst 463003
+system.physmem.bw_inst_read::cpu1.inst 68774
+system.physmem.bw_inst_read::total 531776
+system.physmem.bw_write::writebacks 3110247
+system.physmem.bw_write::cpu0.data 6200
+system.physmem.bw_write::cpu1.data 14
+system.physmem.bw_write::total 3116461
+system.physmem.bw_total::writebacks 3110247
+system.physmem.bw_total::cpu0.dtb.walker 679
+system.physmem.bw_total::cpu0.itb.walker 68
+system.physmem.bw_total::cpu0.inst 463003
+system.physmem.bw_total::cpu0.data 468871
+system.physmem.bw_total::cpu0.l2cache.prefetcher 2968533
+system.physmem.bw_total::cpu1.dtb.walker 113
+system.physmem.bw_total::cpu1.itb.walker 23
+system.physmem.bw_total::cpu1.inst 68774
+system.physmem.bw_total::cpu1.data 210452
+system.physmem.bw_total::cpu1.l2cache.prefetcher 152830
+system.physmem.bw_total::realview.ide 340
+system.physmem.bw_total::total 7443933
+system.physmem.readReqs 193990
+system.physmem.writeReqs 141760
+system.physmem.readBursts 193990
+system.physmem.writeBursts 141760
+system.physmem.bytesReadDRAM 12404352
+system.physmem.bytesReadWrQ 10944
+system.physmem.bytesWritten 8822208
+system.physmem.bytesReadSys 12232364
+system.physmem.bytesWrittenSys 8809180
+system.physmem.servicedByWrQ 171
+system.physmem.mergedWrBursts 3896
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 11914
+system.physmem.perBankRdBursts::1 11892
+system.physmem.perBankRdBursts::2 12334
+system.physmem.perBankRdBursts::3 12168
+system.physmem.perBankRdBursts::4 14940
+system.physmem.perBankRdBursts::5 12679
+system.physmem.perBankRdBursts::6 12580
+system.physmem.perBankRdBursts::7 12786
+system.physmem.perBankRdBursts::8 12011
+system.physmem.perBankRdBursts::9 12103
+system.physmem.perBankRdBursts::10 11235
+system.physmem.perBankRdBursts::11 10159
+system.physmem.perBankRdBursts::12 11352
+system.physmem.perBankRdBursts::13 11878
+system.physmem.perBankRdBursts::14 11948
+system.physmem.perBankRdBursts::15 11839
+system.physmem.perBankWrBursts::0 8668
+system.physmem.perBankWrBursts::1 8756
+system.physmem.perBankWrBursts::2 9041
+system.physmem.perBankWrBursts::3 8790
+system.physmem.perBankWrBursts::4 8750
+system.physmem.perBankWrBursts::5 9282
+system.physmem.perBankWrBursts::6 9153
+system.physmem.perBankWrBursts::7 9187
+system.physmem.perBankWrBursts::8 8579
+system.physmem.perBankWrBursts::9 8637
+system.physmem.perBankWrBursts::10 8170
+system.physmem.perBankWrBursts::11 7474
+system.physmem.perBankWrBursts::12 8401
+system.physmem.perBankWrBursts::13 8247
+system.physmem.perBankWrBursts::14 8495
+system.physmem.perBankWrBursts::15 8217
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 62
+system.physmem.totGap 2826661535500
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 551
+system.physmem.readPktSize::3 28
+system.physmem.readPktSize::4 3091
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 190320
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 4391
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 137369
+system.physmem.rdQLenPdf::0 58346
+system.physmem.rdQLenPdf::1 70372
+system.physmem.rdQLenPdf::2 15665
+system.physmem.rdQLenPdf::3 12814
+system.physmem.rdQLenPdf::4 8399
+system.physmem.rdQLenPdf::5 7609
+system.physmem.rdQLenPdf::6 6485
+system.physmem.rdQLenPdf::7 5441
+system.physmem.rdQLenPdf::8 4697
+system.physmem.rdQLenPdf::9 1516
+system.physmem.rdQLenPdf::10 1147
+system.physmem.rdQLenPdf::11 744
+system.physmem.rdQLenPdf::12 307
+system.physmem.rdQLenPdf::13 271
+system.physmem.rdQLenPdf::14 6
+system.physmem.rdQLenPdf::15 0
+system.physmem.rdQLenPdf::16 0
+system.physmem.rdQLenPdf::17 0
+system.physmem.rdQLenPdf::18 0
+system.physmem.rdQLenPdf::19 0
+system.physmem.rdQLenPdf::20 0
+system.physmem.rdQLenPdf::21 0
+system.physmem.rdQLenPdf::22 0
+system.physmem.rdQLenPdf::23 0
+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
+system.physmem.rdQLenPdf::26 0
+system.physmem.rdQLenPdf::27 0
+system.physmem.rdQLenPdf::28 0
+system.physmem.rdQLenPdf::29 0
+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 1
+system.physmem.wrQLenPdf::1 1
+system.physmem.wrQLenPdf::2 1
+system.physmem.wrQLenPdf::3 1
+system.physmem.wrQLenPdf::4 1
+system.physmem.wrQLenPdf::5 1
+system.physmem.wrQLenPdf::6 1
+system.physmem.wrQLenPdf::7 1
+system.physmem.wrQLenPdf::8 1
+system.physmem.wrQLenPdf::9 1
+system.physmem.wrQLenPdf::10 1
+system.physmem.wrQLenPdf::11 1
+system.physmem.wrQLenPdf::12 1
+system.physmem.wrQLenPdf::13 1
+system.physmem.wrQLenPdf::14 1
+system.physmem.wrQLenPdf::15 2452
+system.physmem.wrQLenPdf::16 3359
+system.physmem.wrQLenPdf::17 3947
+system.physmem.wrQLenPdf::18 4490
+system.physmem.wrQLenPdf::19 5358
+system.physmem.wrQLenPdf::20 5708
+system.physmem.wrQLenPdf::21 6610
+system.physmem.wrQLenPdf::22 7231
+system.physmem.wrQLenPdf::23 8280
+system.physmem.wrQLenPdf::24 8230
+system.physmem.wrQLenPdf::25 9615
+system.physmem.wrQLenPdf::26 10123
+system.physmem.wrQLenPdf::27 8884
+system.physmem.wrQLenPdf::28 8655
+system.physmem.wrQLenPdf::29 9256
+system.physmem.wrQLenPdf::30 10414
+system.physmem.wrQLenPdf::31 8635
+system.physmem.wrQLenPdf::32 8397
+system.physmem.wrQLenPdf::33 1065
+system.physmem.wrQLenPdf::34 726
+system.physmem.wrQLenPdf::35 579
+system.physmem.wrQLenPdf::36 450
+system.physmem.wrQLenPdf::37 333
+system.physmem.wrQLenPdf::38 297
+system.physmem.wrQLenPdf::39 278
+system.physmem.wrQLenPdf::40 216
+system.physmem.wrQLenPdf::41 222
+system.physmem.wrQLenPdf::42 229
+system.physmem.wrQLenPdf::43 228
+system.physmem.wrQLenPdf::44 213
+system.physmem.wrQLenPdf::45 190
+system.physmem.wrQLenPdf::46 255
+system.physmem.wrQLenPdf::47 176
+system.physmem.wrQLenPdf::48 184
+system.physmem.wrQLenPdf::49 191
+system.physmem.wrQLenPdf::50 192
+system.physmem.wrQLenPdf::51 157
+system.physmem.wrQLenPdf::52 157
+system.physmem.wrQLenPdf::53 142
+system.physmem.wrQLenPdf::54 137
+system.physmem.wrQLenPdf::55 210
+system.physmem.wrQLenPdf::56 217
+system.physmem.wrQLenPdf::57 229
+system.physmem.wrQLenPdf::58 130
+system.physmem.wrQLenPdf::59 177
+system.physmem.wrQLenPdf::60 223
+system.physmem.wrQLenPdf::61 177
+system.physmem.wrQLenPdf::62 87
+system.physmem.wrQLenPdf::63 138
+system.physmem.bytesPerActivate::samples 84524
+system.physmem.bytesPerActivate::mean 251.130566
+system.physmem.bytesPerActivate::gmean 142.653313
+system.physmem.bytesPerActivate::stdev 307.296036
+system.physmem.bytesPerActivate::0-127 42638 50.44% 50.44%
+system.physmem.bytesPerActivate::128-255 17636 20.87% 71.31%
+system.physmem.bytesPerActivate::256-383 6205 7.34% 78.65%
+system.physmem.bytesPerActivate::384-511 3459 4.09% 82.74%
+system.physmem.bytesPerActivate::512-639 2826 3.34% 86.09%
+system.physmem.bytesPerActivate::640-767 1563 1.85% 87.94%
+system.physmem.bytesPerActivate::768-895 974 1.15% 89.09%
+system.physmem.bytesPerActivate::896-1023 1000 1.18% 90.27%
+system.physmem.bytesPerActivate::1024-1151 8223 9.73% 100.00%
+system.physmem.bytesPerActivate::total 84524
+system.physmem.rdPerTurnAround::samples 6835
+system.physmem.rdPerTurnAround::mean 28.356547
+system.physmem.rdPerTurnAround::stdev 562.818995
+system.physmem.rdPerTurnAround::0-2047 6833 99.97% 99.97%
+system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99%
+system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00%
+system.physmem.rdPerTurnAround::total 6835
+system.physmem.wrPerTurnAround::samples 6835
+system.physmem.wrPerTurnAround::mean 20.167813
+system.physmem.wrPerTurnAround::gmean 18.518444
+system.physmem.wrPerTurnAround::stdev 13.688369
+system.physmem.wrPerTurnAround::16-19 5748 84.10% 84.10%
+system.physmem.wrPerTurnAround::20-23 371 5.43% 89.52%
+system.physmem.wrPerTurnAround::24-27 97 1.42% 90.94%
+system.physmem.wrPerTurnAround::28-31 47 0.69% 91.63%
+system.physmem.wrPerTurnAround::32-35 263 3.85% 95.48%
+system.physmem.wrPerTurnAround::36-39 24 0.35% 95.83%
+system.physmem.wrPerTurnAround::40-43 21 0.31% 96.14%
+system.physmem.wrPerTurnAround::44-47 10 0.15% 96.28%
+system.physmem.wrPerTurnAround::48-51 9 0.13% 96.42%
+system.physmem.wrPerTurnAround::52-55 6 0.09% 96.50%
+system.physmem.wrPerTurnAround::56-59 3 0.04% 96.55%
+system.physmem.wrPerTurnAround::60-63 8 0.12% 96.66%
+system.physmem.wrPerTurnAround::64-67 142 2.08% 98.74%
+system.physmem.wrPerTurnAround::68-71 10 0.15% 98.89%
+system.physmem.wrPerTurnAround::72-75 7 0.10% 98.99%
+system.physmem.wrPerTurnAround::76-79 3 0.04% 99.03%
+system.physmem.wrPerTurnAround::80-83 8 0.12% 99.15%
+system.physmem.wrPerTurnAround::84-87 2 0.03% 99.18%
+system.physmem.wrPerTurnAround::88-91 3 0.04% 99.22%
+system.physmem.wrPerTurnAround::96-99 3 0.04% 99.27%
+system.physmem.wrPerTurnAround::100-103 1 0.01% 99.28%
+system.physmem.wrPerTurnAround::108-111 7 0.10% 99.39%
+system.physmem.wrPerTurnAround::112-115 4 0.06% 99.44%
+system.physmem.wrPerTurnAround::116-119 3 0.04% 99.49%
+system.physmem.wrPerTurnAround::128-131 14 0.20% 99.69%
+system.physmem.wrPerTurnAround::132-135 1 0.01% 99.71%
+system.physmem.wrPerTurnAround::136-139 1 0.01% 99.72%
+system.physmem.wrPerTurnAround::140-143 5 0.07% 99.80%
+system.physmem.wrPerTurnAround::144-147 1 0.01% 99.81%
+system.physmem.wrPerTurnAround::156-159 4 0.06% 99.87%
+system.physmem.wrPerTurnAround::160-163 2 0.03% 99.90%
+system.physmem.wrPerTurnAround::168-171 1 0.01% 99.91%
+system.physmem.wrPerTurnAround::172-175 2 0.03% 99.94%
+system.physmem.wrPerTurnAround::176-179 2 0.03% 99.97%
+system.physmem.wrPerTurnAround::192-195 1 0.01% 99.99%
+system.physmem.wrPerTurnAround::196-199 1 0.01% 100.00%
+system.physmem.wrPerTurnAround::total 6835
+system.physmem.totQLat 10069361106
+system.physmem.totMemAccLat 13703448606
+system.physmem.totBusLat 969090000
+system.physmem.avgQLat 51952.39
+system.physmem.avgBusLat 4999.97
+system.physmem.avgMemAccLat 70702.30
+system.physmem.avgRdBW 4.39
+system.physmem.avgWrBW 3.12
+system.physmem.avgRdBWSys 4.33
+system.physmem.avgWrBWSys 3.12
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 0.06
+system.physmem.busUtilRead 0.03
+system.physmem.busUtilWrite 0.02
+system.physmem.avgRdQLen 1.14
+system.physmem.avgWrQLen 23.27
+system.physmem.readRowHits 161621
+system.physmem.writeRowHits 85520
+system.physmem.readRowHitRate 83.39
+system.physmem.writeRowHitRate 62.03
+system.physmem.avgGap 8418947.24
+system.physmem.pageHitRate 74.51
+system.physmem_0.actEnergy 316530480
+system.physmem_0.preEnergy 168239940
+system.physmem_0.readEnergy 723232020
+system.physmem_0.writeEnergy 373892940
+system.physmem_0.refreshEnergy 4560628800.000001
+system.physmem_0.actBackEnergy 4738281180
+system.physmem_0.preBackEnergy 246338400
+system.physmem_0.actPowerDownEnergy 9126143460
+system.physmem_0.prePowerDownEnergy 6642032160
+system.physmem_0.selfRefreshEnergy 667515620400
+system.physmem_0.totalEnergy 694413647970
+system.physmem_0.averagePower 245.665627
+system.physmem_0.totalIdleTime 2815530854636
+system.physmem_0.memoryStateTime::IDLE 431590684
+system.physmem_0.memoryStateTime::REF 1937276000
+system.physmem_0.memoryStateTime::SREF 2778312906500
+system.physmem_0.memoryStateTime::PRE_PDN 17296954515
+system.physmem_0.memoryStateTime::ACT 8669745430
+system.physmem_0.memoryStateTime::ACT_PDN 20013349371
+system.physmem_1.actEnergy 286970880
+system.physmem_1.preEnergy 152528640
+system.physmem_1.readEnergy 660628500
+system.physmem_1.writeEnergy 345668400
+system.physmem_1.refreshEnergy 4566775200.000001
+system.physmem_1.actBackEnergy 4789448370
+system.physmem_1.preBackEnergy 246990720
+system.physmem_1.actPowerDownEnergy 8737527720
+system.physmem_1.prePowerDownEnergy 6775449120
+system.physmem_1.selfRefreshEnergy 667645471770
+system.physmem_1.totalEnergy 694209041370
+system.physmem_1.averagePower 245.593242
+system.physmem_1.totalIdleTime 2815511892167
+system.physmem_1.memoryStateTime::IDLE 431458200
+system.physmem_1.memoryStateTime::REF 1940194000
+system.physmem_1.memoryStateTime::SREF 2778706290250
+system.physmem_1.memoryStateTime::PRE_PDN 17644479066
+system.physmem_1.memoryStateTime::ACT 8778278133
+system.physmem_1.memoryStateTime::ACT_PDN 19161122851
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.nvmem.bytes_read::cpu0.inst 112
+system.realview.nvmem.bytes_read::cpu1.inst 176
+system.realview.nvmem.bytes_read::total 288
+system.realview.nvmem.bytes_inst_read::cpu0.inst 112
+system.realview.nvmem.bytes_inst_read::cpu1.inst 176
+system.realview.nvmem.bytes_inst_read::total 288
+system.realview.nvmem.num_reads::cpu0.inst 7
+system.realview.nvmem.num_reads::cpu1.inst 11
+system.realview.nvmem.num_reads::total 18
+system.realview.nvmem.bw_read::cpu0.inst 40
+system.realview.nvmem.bw_read::cpu1.inst 62
+system.realview.nvmem.bw_read::total 102
+system.realview.nvmem.bw_inst_read::cpu0.inst 40
+system.realview.nvmem.bw_inst_read::cpu1.inst 62
+system.realview.nvmem.bw_inst_read::total 102
+system.realview.nvmem.bw_total::cpu0.inst 40
+system.realview.nvmem.bw_total::cpu1.inst 62
+system.realview.nvmem.bw_total::total 102
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cf0.dma_read_full_pages 0
+system.cf0.dma_read_bytes 1024
+system.cf0.dma_read_txs 1
+system.cf0.dma_write_full_pages 540
+system.cf0.dma_write_bytes 2318336
+system.cf0.dma_write_txs 631
+system.cpu0.branchPred.lookups 23883617
+system.cpu0.branchPred.condPredicted 15636864
+system.cpu0.branchPred.condIncorrect 931262
+system.cpu0.branchPred.BTBLookups 14469127
+system.cpu0.branchPred.BTBHits 9520584
+system.cpu0.branchPred.BTBCorrect 0
+system.cpu0.branchPred.BTBHitPct 65.799298
+system.cpu0.branchPred.usedRAS 3844622
+system.cpu0.branchPred.RASInCorrect 34084
+system.cpu0.branchPred.indirectLookups 1359917
+system.cpu0.branchPred.indirectHits 1203673
+system.cpu0.branchPred.indirectMisses 156244
+system.cpu0.branchPredindirectMispredicted 49072
+system.cpu_clk_domain.clock 500
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu0.dtb.walker.walks 66222
+system.cpu0.dtb.walker.walksShort 66222
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25101
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 19183
+system.cpu0.dtb.walker.walksSquashedBefore 21938
+system.cpu0.dtb.walker.walkWaitTime::samples 44284
+system.cpu0.dtb.walker.walkWaitTime::mean 488.528588
+system.cpu0.dtb.walker.walkWaitTime::stdev 3047.976442
+system.cpu0.dtb.walker.walkWaitTime::0-8191 43088 97.30% 97.30%
+system.cpu0.dtb.walker.walkWaitTime::8192-16383 903 2.04% 99.34%
+system.cpu0.dtb.walker.walkWaitTime::16384-24575 143 0.32% 99.66%
+system.cpu0.dtb.walker.walkWaitTime::24576-32767 91 0.21% 99.87%
+system.cpu0.dtb.walker.walkWaitTime::32768-40959 25 0.06% 99.92%
+system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.96%
+system.cpu0.dtb.walker.walkWaitTime::57344-65535 14 0.03% 100.00%
+system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00%
+system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00%
+system.cpu0.dtb.walker.walkWaitTime::total 44284
+system.cpu0.dtb.walker.walkCompletionTime::samples 16163
+system.cpu0.dtb.walker.walkCompletionTime::mean 11253.913259
+system.cpu0.dtb.walker.walkCompletionTime::gmean 9626.898763
+system.cpu0.dtb.walker.walkCompletionTime::stdev 9656.482025
+system.cpu0.dtb.walker.walkCompletionTime::0-16383 14751 91.26% 91.26%
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1259 7.79% 99.05%
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151 113 0.70% 99.75%
+system.cpu0.dtb.walker.walkCompletionTime::49152-65535 16 0.10% 99.85%
+system.cpu0.dtb.walker.walkCompletionTime::98304-114687 4 0.02% 99.88%
+system.cpu0.dtb.walker.walkCompletionTime::114688-131071 3 0.02% 99.89%
+system.cpu0.dtb.walker.walkCompletionTime::229376-245759 17 0.11% 100.00%
+system.cpu0.dtb.walker.walkCompletionTime::total 16163
+system.cpu0.dtb.walker.walksPending::samples 86471688152
+system.cpu0.dtb.walker.walksPending::mean 0.594968
+system.cpu0.dtb.walker.walksPending::stdev 0.503107
+system.cpu0.dtb.walker.walksPending::0-1 86414761152 99.93% 99.93%
+system.cpu0.dtb.walker.walksPending::2-3 39539000 0.05% 99.98%
+system.cpu0.dtb.walker.walksPending::4-5 7796000 0.01% 99.99%
+system.cpu0.dtb.walker.walksPending::6-7 4501500 0.01% 99.99%
+system.cpu0.dtb.walker.walksPending::8-9 1529000 0.00% 100.00%
+system.cpu0.dtb.walker.walksPending::10-11 973000 0.00% 100.00%
+system.cpu0.dtb.walker.walksPending::12-13 1169500 0.00% 100.00%
+system.cpu0.dtb.walker.walksPending::14-15 1418000 0.00% 100.00%
+system.cpu0.dtb.walker.walksPending::16-17 1000 0.00% 100.00%
+system.cpu0.dtb.walker.walksPending::total 86471688152
+system.cpu0.dtb.walker.walkPageSizes::4K 5110 78.70% 78.70%
+system.cpu0.dtb.walker.walkPageSizes::1M 1383 21.30% 100.00%
+system.cpu0.dtb.walker.walkPageSizes::total 6493
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66222
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66222
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6493
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6493
+system.cpu0.dtb.walker.walkRequestOrigin::total 72715
+system.cpu0.dtb.inst_hits 0
+system.cpu0.dtb.inst_misses 0
+system.cpu0.dtb.read_hits 17690650
+system.cpu0.dtb.read_misses 55636
+system.cpu0.dtb.write_hits 14580006
+system.cpu0.dtb.write_misses 10586
+system.cpu0.dtb.flush_tlb 66
+system.cpu0.dtb.flush_tlb_mva 917
+system.cpu0.dtb.flush_tlb_mva_asid 0
+system.cpu0.dtb.flush_tlb_asid 0
+system.cpu0.dtb.flush_entries 3438
+system.cpu0.dtb.align_faults 151
+system.cpu0.dtb.prefetch_faults 2216
+system.cpu0.dtb.domain_faults 0
+system.cpu0.dtb.perms_faults 881
+system.cpu0.dtb.read_accesses 17746286
+system.cpu0.dtb.write_accesses 14590592
+system.cpu0.dtb.inst_accesses 0
+system.cpu0.dtb.hits 32270656
+system.cpu0.dtb.misses 66222
+system.cpu0.dtb.accesses 32336878
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu0.istage2_mmu.stage2_tlb.hits 0
+system.cpu0.istage2_mmu.stage2_tlb.misses 0
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu0.itb.walker.walks 11718
+system.cpu0.itb.walker.walksShort 11718
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3874
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6789
+system.cpu0.itb.walker.walksSquashedBefore 1055
+system.cpu0.itb.walker.walkWaitTime::samples 10663
+system.cpu0.itb.walker.walkWaitTime::mean 1163.040420
+system.cpu0.itb.walker.walkWaitTime::stdev 4429.625460
+system.cpu0.itb.walker.walkWaitTime::0-4095 9808 91.98% 91.98%
+system.cpu0.itb.walker.walkWaitTime::4096-8191 227 2.13% 94.11%
+system.cpu0.itb.walker.walkWaitTime::8192-12287 242 2.27% 96.38%
+system.cpu0.itb.walker.walkWaitTime::12288-16383 130 1.22% 97.60%
+system.cpu0.itb.walker.walkWaitTime::16384-20479 90 0.84% 98.44%
+system.cpu0.itb.walker.walkWaitTime::20480-24575 78 0.73% 99.17%
+system.cpu0.itb.walker.walkWaitTime::24576-28671 30 0.28% 99.46%
+system.cpu0.itb.walker.walkWaitTime::28672-32767 21 0.20% 99.65%
+system.cpu0.itb.walker.walkWaitTime::32768-36863 17 0.16% 99.81%
+system.cpu0.itb.walker.walkWaitTime::36864-40959 13 0.12% 99.93%
+system.cpu0.itb.walker.walkWaitTime::40960-45055 4 0.04% 99.97%
+system.cpu0.itb.walker.walkWaitTime::49152-53247 3 0.03% 100.00%
+system.cpu0.itb.walker.walkWaitTime::total 10663
+system.cpu0.itb.walker.walkCompletionTime::samples 3662
+system.cpu0.itb.walker.walkCompletionTime::mean 12240.988531
+system.cpu0.itb.walker.walkCompletionTime::gmean 11314.959654
+system.cpu0.itb.walker.walkCompletionTime::stdev 5192.867948
+system.cpu0.itb.walker.walkCompletionTime::0-8191 610 16.66% 16.66%
+system.cpu0.itb.walker.walkCompletionTime::8192-16383 2766 75.53% 92.19%
+system.cpu0.itb.walker.walkCompletionTime::16384-24575 158 4.31% 96.50%
+system.cpu0.itb.walker.walkCompletionTime::24576-32767 100 2.73% 99.24%
+system.cpu0.itb.walker.walkCompletionTime::32768-40959 24 0.66% 99.89%
+system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.03% 99.92%
+system.cpu0.itb.walker.walkCompletionTime::57344-65535 2 0.05% 99.97%
+system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00%
+system.cpu0.itb.walker.walkCompletionTime::total 3662
+system.cpu0.itb.walker.walksPending::samples 22046382212
+system.cpu0.itb.walker.walksPending::mean 0.864816
+system.cpu0.itb.walker.walksPending::stdev 0.342861
+system.cpu0.itb.walker.walksPending::0 2986480000 13.55% 13.55%
+system.cpu0.itb.walker.walksPending::1 19054637212 86.43% 99.98%
+system.cpu0.itb.walker.walksPending::2 4434000 0.02% 100.00%
+system.cpu0.itb.walker.walksPending::3 772000 0.00% 100.00%
+system.cpu0.itb.walker.walksPending::4 59000 0.00% 100.00%
+system.cpu0.itb.walker.walksPending::total 22046382212
+system.cpu0.itb.walker.walkPageSizes::4K 2275 87.27% 87.27%
+system.cpu0.itb.walker.walkPageSizes::1M 332 12.73% 100.00%
+system.cpu0.itb.walker.walkPageSizes::total 2607
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11718
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11718
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2607
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2607
+system.cpu0.itb.walker.walkRequestOrigin::total 14325
+system.cpu0.itb.inst_hits 37441602
+system.cpu0.itb.inst_misses 11718
+system.cpu0.itb.read_hits 0
+system.cpu0.itb.read_misses 0
+system.cpu0.itb.write_hits 0
+system.cpu0.itb.write_misses 0
+system.cpu0.itb.flush_tlb 66
+system.cpu0.itb.flush_tlb_mva 917
+system.cpu0.itb.flush_tlb_mva_asid 0
+system.cpu0.itb.flush_tlb_asid 0
+system.cpu0.itb.flush_entries 2316
+system.cpu0.itb.align_faults 0
+system.cpu0.itb.prefetch_faults 0
+system.cpu0.itb.domain_faults 0
+system.cpu0.itb.perms_faults 2435
+system.cpu0.itb.read_accesses 0
+system.cpu0.itb.write_accesses 0
+system.cpu0.itb.inst_accesses 37453320
+system.cpu0.itb.hits 37441602
+system.cpu0.itb.misses 11718
+system.cpu0.itb.accesses 37453320
+system.cpu0.numPwrStateTransitions 3670
+system.cpu0.pwrStateClkGateDist::samples 1835
+system.cpu0.pwrStateClkGateDist::mean 1504005769.241417
+system.cpu0.pwrStateClkGateDist::stdev 24031514703.397018
+system.cpu0.pwrStateClkGateDist::underflows 1058 57.66% 57.66%
+system.cpu0.pwrStateClkGateDist::1000-5e+10 770 41.96% 99.62%
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73%
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78%
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00%
+system.cpu0.pwrStateClkGateDist::min_value 501
+system.cpu0.pwrStateClkGateDist::max_value 499971670448
+system.cpu0.pwrStateClkGateDist::total 1835
+system.cpu0.pwrStateResidencyTicks::ON 66811235942
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2759850586558
+system.cpu0.numCycles 133623938
+system.cpu0.numWorkItemsStarted 0
+system.cpu0.numWorkItemsCompleted 0
+system.cpu0.fetch.icacheStallCycles 19309716
+system.cpu0.fetch.Insts 111825489
+system.cpu0.fetch.Branches 23883617
+system.cpu0.fetch.predictedBranches 14568879
+system.cpu0.fetch.Cycles 107363215
+system.cpu0.fetch.SquashCycles 2746944
+system.cpu0.fetch.TlbCycles 153949
+system.cpu0.fetch.MiscStallCycles 56808
+system.cpu0.fetch.PendingTrapStallCycles 430429
+system.cpu0.fetch.PendingQuiesceStallCycles 423849
+system.cpu0.fetch.IcacheWaitRetryStallCycles 97847
+system.cpu0.fetch.CacheLines 37440816
+system.cpu0.fetch.IcacheSquashes 257322
+system.cpu0.fetch.ItlbSquashes 6077
+system.cpu0.fetch.rateDist::samples 129209285
+system.cpu0.fetch.rateDist::mean 1.043124
+system.cpu0.fetch.rateDist::stdev 1.255712
+system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00%
+system.cpu0.fetch.rateDist::0 67184631 52.00% 52.00%
+system.cpu0.fetch.rateDist::1 21286921 16.47% 68.47%
+system.cpu0.fetch.rateDist::2 8718865 6.75% 75.22%
+system.cpu0.fetch.rateDist::3 32018868 24.78% 100.00%
+system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00%
+system.cpu0.fetch.rateDist::min_value 0
+system.cpu0.fetch.rateDist::max_value 3
+system.cpu0.fetch.rateDist::total 129209285
+system.cpu0.fetch.branchRate 0.178738
+system.cpu0.fetch.rate 0.836867
+system.cpu0.decode.IdleCycles 19894191
+system.cpu0.decode.BlockedCycles 62312905
+system.cpu0.decode.RunCycles 40998047
+system.cpu0.decode.UnblockCycles 4962143
+system.cpu0.decode.SquashCycles 1041999
+system.cpu0.decode.BranchResolved 8668231
+system.cpu0.decode.BranchMispred 335640
+system.cpu0.decode.DecodedInsts 109929384
+system.cpu0.decode.SquashedInsts 3777106
+system.cpu0.rename.SquashCycles 1041999
+system.cpu0.rename.IdleCycles 25543977
+system.cpu0.rename.BlockCycles 12855168
+system.cpu0.rename.serializeStallCycles 37713858
+system.cpu0.rename.RunCycles 40174100
+system.cpu0.rename.UnblockCycles 11880183
+system.cpu0.rename.RenamedInsts 104965516
+system.cpu0.rename.SquashedInsts 1005523
+system.cpu0.rename.ROBFullEvents 1488138
+system.cpu0.rename.IQFullEvents 163506
+system.cpu0.rename.LQFullEvents 56292
+system.cpu0.rename.SQFullEvents 7677533
+system.cpu0.rename.RenamedOperands 109140762
+system.cpu0.rename.RenameLookups 479136363
+system.cpu0.rename.int_rename_lookups 119999583
+system.cpu0.rename.fp_rename_lookups 9456
+system.cpu0.rename.CommittedMaps 98086088
+system.cpu0.rename.UndoneMaps 11054663
+system.cpu0.rename.serializingInsts 1226708
+system.cpu0.rename.tempSerializingInsts 1083966
+system.cpu0.rename.skidInsts 12371386
+system.cpu0.memDep0.insertedLoads 18620664
+system.cpu0.memDep0.insertedStores 16044511
+system.cpu0.memDep0.conflictingLoads 1690108
+system.cpu0.memDep0.conflictingStores 2200098
+system.cpu0.iq.iqInstsAdded 102082946
+system.cpu0.iq.iqNonSpecInstsAdded 1690829
+system.cpu0.iq.iqInstsIssued 100263539
+system.cpu0.iq.iqSquashedInstsIssued 450385
+system.cpu0.iq.iqSquashedInstsExamined 9006249
+system.cpu0.iq.iqSquashedOperandsExamined 21271119
+system.cpu0.iq.iqSquashedNonSpecRemoved 120484
+system.cpu0.iq.issued_per_cycle::samples 129209285
+system.cpu0.iq.issued_per_cycle::mean 0.775978
+system.cpu0.iq.issued_per_cycle::stdev 1.026117
+system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00%
+system.cpu0.iq.issued_per_cycle::0 73182856 56.64% 56.64%
+system.cpu0.iq.issued_per_cycle::1 23242172 17.99% 74.63%
+system.cpu0.iq.issued_per_cycle::2 22434047 17.36% 91.99%
+system.cpu0.iq.issued_per_cycle::3 9247618 7.16% 99.15%
+system.cpu0.iq.issued_per_cycle::4 1102541 0.85% 100.00%
+system.cpu0.iq.issued_per_cycle::5 51 0.00% 100.00%
+system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00%
+system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00%
+system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00%
+system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00%
+system.cpu0.iq.issued_per_cycle::min_value 0
+system.cpu0.iq.issued_per_cycle::max_value 5
+system.cpu0.iq.issued_per_cycle::total 129209285
+system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00%
+system.cpu0.iq.fu_full::IntAlu 9305149 40.59% 40.59%
+system.cpu0.iq.fu_full::IntMult 67 0.00% 40.59%
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.59%
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.59%
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.59%
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.59%
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.59%
+system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 40.59%
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.59%
+system.cpu0.iq.fu_full::FloatMisc 0 0.00% 40.59%
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.59%
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.59%
+system.cpu0.iq.fu_full::MemRead 5563437 24.27% 64.86%
+system.cpu0.iq.fu_full::MemWrite 8045304 35.10% 99.96%
+system.cpu0.iq.fu_full::FloatMemRead 2849 0.01% 99.97%
+system.cpu0.iq.fu_full::FloatMemWrite 7035 0.03% 100.00%
+system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00%
+system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00%
+system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00%
+system.cpu0.iq.FU_type_0::IntAlu 66159697 65.99% 65.99%
+system.cpu0.iq.FU_type_0::IntMult 92257 0.09% 66.08%
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.08%
+system.cpu0.iq.FU_type_0::SimdFloatMisc 8062 0.01% 66.09%
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09%
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09%
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09%
+system.cpu0.iq.FU_type_0::MemRead 18372464 18.32% 84.41%
+system.cpu0.iq.FU_type_0::MemWrite 15617502 15.58% 99.99%
+system.cpu0.iq.FU_type_0::FloatMemRead 3106 0.00% 99.99%
+system.cpu0.iq.FU_type_0::FloatMemWrite 8177 0.01% 100.00%
+system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00%
+system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00%
+system.cpu0.iq.FU_type_0::total 100263539
+system.cpu0.iq.rate 0.750341
+system.cpu0.iq.fu_busy_cnt 22923841
+system.cpu0.iq.fu_busy_rate 0.228636
+system.cpu0.iq.int_inst_queue_reads 353078102
+system.cpu0.iq.int_inst_queue_writes 112787493
+system.cpu0.iq.int_inst_queue_wakeup_accesses 98245644
+system.cpu0.iq.fp_inst_queue_reads 32486
+system.cpu0.iq.fp_inst_queue_writes 11310
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 9716
+system.cpu0.iq.int_alu_accesses 123163934
+system.cpu0.iq.fp_alu_accesses 21173
+system.cpu0.iew.lsq.thread0.forwLoads 364671
+system.cpu0.iew.lsq.thread0.invAddrLoads 0
+system.cpu0.iew.lsq.thread0.squashedLoads 1892754
+system.cpu0.iew.lsq.thread0.ignoredResponses 2476
+system.cpu0.iew.lsq.thread0.memOrderViolation 18857
+system.cpu0.iew.lsq.thread0.squashedStores 880777
+system.cpu0.iew.lsq.thread0.invAddrSwpfs 0
+system.cpu0.iew.lsq.thread0.blockedLoads 0
+system.cpu0.iew.lsq.thread0.rescheduledLoads 109512
+system.cpu0.iew.lsq.thread0.cacheBlocked 359340
+system.cpu0.iew.iewIdleCycles 0
+system.cpu0.iew.iewSquashCycles 1041999
+system.cpu0.iew.iewBlockCycles 1649819
+system.cpu0.iew.iewUnblockCycles 245592
+system.cpu0.iew.iewDispatchedInsts 103926397
+system.cpu0.iew.iewDispSquashedInsts 0
+system.cpu0.iew.iewDispLoadInsts 18620664
+system.cpu0.iew.iewDispStoreInsts 16044511
+system.cpu0.iew.iewDispNonSpecInsts 874753
+system.cpu0.iew.iewIQFullEvents 27890
+system.cpu0.iew.iewLSQFullEvents 193744
+system.cpu0.iew.memOrderViolationEvents 18857
+system.cpu0.iew.predictedTakenIncorrect 252700
+system.cpu0.iew.predictedNotTakenIncorrect 404109
+system.cpu0.iew.branchMispredicts 656809
+system.cpu0.iew.iewExecutedInsts 99249738
+system.cpu0.iew.iewExecLoadInsts 17937137
+system.cpu0.iew.iewExecSquashedInsts 947695
+system.cpu0.iew.exec_swp 0
+system.cpu0.iew.exec_nop 152622
+system.cpu0.iew.exec_refs 33402263
+system.cpu0.iew.exec_branches 16813516
+system.cpu0.iew.exec_stores 15465126
+system.cpu0.iew.exec_rate 0.742754
+system.cpu0.iew.wb_sent 98705736
+system.cpu0.iew.wb_count 98255360
+system.cpu0.iew.wb_producers 51181309
+system.cpu0.iew.wb_consumers 84541658
+system.cpu0.iew.wb_rate 0.735313
+system.cpu0.iew.wb_fanout 0.605398
+system.cpu0.commit.commitSquashedInsts 8009256
+system.cpu0.commit.commitNonSpecStalls 1570345
+system.cpu0.commit.branchMispredicts 599789
+system.cpu0.commit.committed_per_cycle::samples 127525044
+system.cpu0.commit.committed_per_cycle::mean 0.744086
+system.cpu0.commit.committed_per_cycle::stdev 1.463999
+system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00%
+system.cpu0.commit.committed_per_cycle::0 83229473 65.27% 65.27%
+system.cpu0.commit.committed_per_cycle::1 24686876 19.36% 84.62%
+system.cpu0.commit.committed_per_cycle::2 8241292 6.46% 91.09%
+system.cpu0.commit.committed_per_cycle::3 3224763 2.53% 93.61%
+system.cpu0.commit.committed_per_cycle::4 3449463 2.70% 96.32%
+system.cpu0.commit.committed_per_cycle::5 1471455 1.15% 97.47%
+system.cpu0.commit.committed_per_cycle::6 1166517 0.91% 98.39%
+system.cpu0.commit.committed_per_cycle::7 550049 0.43% 98.82%
+system.cpu0.commit.committed_per_cycle::8 1505156 1.18% 100.00%
+system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00%
+system.cpu0.commit.committed_per_cycle::min_value 0
+system.cpu0.commit.committed_per_cycle::max_value 8
+system.cpu0.commit.committed_per_cycle::total 127525044
+system.cpu0.commit.committedInsts 78876278
+system.cpu0.commit.committedOps 94889569
+system.cpu0.commit.swp_count 0
+system.cpu0.commit.refs 31891643
+system.cpu0.commit.loads 16727909
+system.cpu0.commit.membars 646468
+system.cpu0.commit.branches 16211438
+system.cpu0.commit.fp_insts 9708
+system.cpu0.commit.int_insts 81828033
+system.cpu0.commit.function_calls 1926976
+system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00%
+system.cpu0.commit.op_class_0::IntAlu 62899934 66.29% 66.29%
+system.cpu0.commit.op_class_0::IntMult 89931 0.09% 66.38%
+system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38%
+system.cpu0.commit.op_class_0::SimdFloatMisc 8061 0.01% 66.39%
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39%
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39%
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39%
+system.cpu0.commit.op_class_0::MemRead 16725653 17.63% 84.02%
+system.cpu0.commit.op_class_0::MemWrite 15156286 15.97% 99.99%
+system.cpu0.commit.op_class_0::FloatMemRead 2256 0.00% 99.99%
+system.cpu0.commit.op_class_0::FloatMemWrite 7448 0.01% 100.00%
+system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00%
+system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
+system.cpu0.commit.op_class_0::total 94889569
+system.cpu0.commit.bw_lim_events 1505156
+system.cpu0.rob.rob_reads 224729063
+system.cpu0.rob.rob_writes 207472797
+system.cpu0.timesIdled 136658
+system.cpu0.idleCycles 4414653
+system.cpu0.quiesceCycles 5519700408
+system.cpu0.committedInsts 78754226
+system.cpu0.committedOps 94767517
+system.cpu0.cpi 1.696721
+system.cpu0.cpi_total 1.696721
+system.cpu0.ipc 0.589372
+system.cpu0.ipc_total 0.589372
+system.cpu0.int_regfile_reads 110210150
+system.cpu0.int_regfile_writes 59480057
+system.cpu0.fp_regfile_reads 8170
+system.cpu0.fp_regfile_writes 2264
+system.cpu0.cc_regfile_reads 349670567
+system.cpu0.cc_regfile_writes 40998554
+system.cpu0.misc_regfile_reads 254890364
+system.cpu0.misc_regfile_writes 1223225
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu0.dcache.tags.replacements 712505
+system.cpu0.dcache.tags.tagsinuse 498.036747
+system.cpu0.dcache.tags.total_refs 28737672
+system.cpu0.dcache.tags.sampled_refs 713017
+system.cpu0.dcache.tags.avg_refs 40.304329
+system.cpu0.dcache.tags.warmup_cycle 296154500
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.036747
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.972728
+system.cpu0.dcache.tags.occ_percent::total 0.972728
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 155
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 27
+system.cpu0.dcache.tags.occ_task_id_percent::1024 1
+system.cpu0.dcache.tags.tag_accesses 63337769
+system.cpu0.dcache.tags.data_accesses 63337769
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu0.dcache.ReadReq_hits::cpu0.data 15522425
+system.cpu0.dcache.ReadReq_hits::total 15522425
+system.cpu0.dcache.WriteReq_hits::cpu0.data 11993338
+system.cpu0.dcache.WriteReq_hits::total 11993338
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307306
+system.cpu0.dcache.SoftPFReq_hits::total 307306
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 362508
+system.cpu0.dcache.LoadLockedReq_hits::total 362508
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360703
+system.cpu0.dcache.StoreCondReq_hits::total 360703
+system.cpu0.dcache.demand_hits::cpu0.data 27515763
+system.cpu0.dcache.demand_hits::total 27515763
+system.cpu0.dcache.overall_hits::cpu0.data 27823069
+system.cpu0.dcache.overall_hits::total 27823069
+system.cpu0.dcache.ReadReq_misses::cpu0.data 649766
+system.cpu0.dcache.ReadReq_misses::total 649766
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1894936
+system.cpu0.dcache.WriteReq_misses::total 1894936
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148626
+system.cpu0.dcache.SoftPFReq_misses::total 148626
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25284
+system.cpu0.dcache.LoadLockedReq_misses::total 25284
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20287
+system.cpu0.dcache.StoreCondReq_misses::total 20287
+system.cpu0.dcache.demand_misses::cpu0.data 2544702
+system.cpu0.dcache.demand_misses::total 2544702
+system.cpu0.dcache.overall_misses::cpu0.data 2693328
+system.cpu0.dcache.overall_misses::total 2693328
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9376883500
+system.cpu0.dcache.ReadReq_miss_latency::total 9376883500
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33055409372
+system.cpu0.dcache.WriteReq_miss_latency::total 33055409372
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 411953000
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 411953000
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 480690000
+system.cpu0.dcache.StoreCondReq_miss_latency::total 480690000
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 523500
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total 523500
+system.cpu0.dcache.demand_miss_latency::cpu0.data 42432292872
+system.cpu0.dcache.demand_miss_latency::total 42432292872
+system.cpu0.dcache.overall_miss_latency::cpu0.data 42432292872
+system.cpu0.dcache.overall_miss_latency::total 42432292872
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 16172191
+system.cpu0.dcache.ReadReq_accesses::total 16172191
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 13888274
+system.cpu0.dcache.WriteReq_accesses::total 13888274
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 455932
+system.cpu0.dcache.SoftPFReq_accesses::total 455932
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387792
+system.cpu0.dcache.LoadLockedReq_accesses::total 387792
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 380990
+system.cpu0.dcache.StoreCondReq_accesses::total 380990
+system.cpu0.dcache.demand_accesses::cpu0.data 30060465
+system.cpu0.dcache.demand_accesses::total 30060465
+system.cpu0.dcache.overall_accesses::cpu0.data 30516397
+system.cpu0.dcache.overall_accesses::total 30516397
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040178
+system.cpu0.dcache.ReadReq_miss_rate::total 0.040178
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136441
+system.cpu0.dcache.WriteReq_miss_rate::total 0.136441
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325983
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325983
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065200
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065200
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053248
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053248
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084653
+system.cpu0.dcache.demand_miss_rate::total 0.084653
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088258
+system.cpu0.dcache.overall_miss_rate::total 0.088258
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14431.169837
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14431.169837
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17444.076936
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 17444.076936
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16293.031166
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16293.031166
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23694.484152
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23694.484152
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16674.759116
+system.cpu0.dcache.demand_avg_miss_latency::total 16674.759116
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15754.595382
+system.cpu0.dcache.overall_avg_miss_latency::total 15754.595382
+system.cpu0.dcache.blocked_cycles::no_mshrs 700
+system.cpu0.dcache.blocked_cycles::no_targets 4983307
+system.cpu0.dcache.blocked::no_mshrs 38
+system.cpu0.dcache.blocked::no_targets 201810
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.421053
+system.cpu0.dcache.avg_blocked_cycles::no_targets 24.693063
+system.cpu0.dcache.writebacks::writebacks 712508
+system.cpu0.dcache.writebacks::total 712508
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 261352
+system.cpu0.dcache.ReadReq_mshr_hits::total 261352
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1569354
+system.cpu0.dcache.WriteReq_mshr_hits::total 1569354
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18573
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18573
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830706
+system.cpu0.dcache.demand_mshr_hits::total 1830706
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 1830706
+system.cpu0.dcache.overall_mshr_hits::total 1830706
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388414
+system.cpu0.dcache.ReadReq_mshr_misses::total 388414
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325582
+system.cpu0.dcache.WriteReq_mshr_misses::total 325582
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102373
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 102373
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6711
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6711
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20287
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 20287
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 713996
+system.cpu0.dcache.demand_mshr_misses::total 713996
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 816369
+system.cpu0.dcache.overall_mshr_misses::total 816369
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20557
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20557
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19259
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19259
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39816
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39816
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5015968500
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5015968500
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6647606395
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6647606395
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1709431500
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1709431500
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 108112000
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 108112000
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 460417000
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 460417000
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 509500
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 509500
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11663574895
+system.cpu0.dcache.demand_mshr_miss_latency::total 11663574895
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13373006395
+system.cpu0.dcache.overall_mshr_miss_latency::total 13373006395
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4592412500
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4592412500
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4592412500
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4592412500
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024017
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024017
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023443
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023443
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224536
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224536
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017306
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017306
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053248
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053248
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023752
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.023752
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026752
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.026752
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12913.974522
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12913.974522
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20417.610295
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20417.610295
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16698.069804
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16698.069804
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16109.670690
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16109.670690
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22695.174250
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22695.174250
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16335.630585
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16335.630585
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16381.080608
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16381.080608
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223398.963857
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223398.963857
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115340.880551
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115340.880551
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu0.icache.tags.replacements 1246927
+system.cpu0.icache.tags.tagsinuse 511.757642
+system.cpu0.icache.tags.total_refs 36135740
+system.cpu0.icache.tags.sampled_refs 1247438
+system.cpu0.icache.tags.avg_refs 28.967965
+system.cpu0.icache.tags.warmup_cycle 6586723000
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757642
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527
+system.cpu0.icache.tags.occ_percent::total 0.999527
+system.cpu0.icache.tags.occ_task_id_blocks::1024 511
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 148
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 234
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 129
+system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047
+system.cpu0.icache.tags.tag_accesses 76121863
+system.cpu0.icache.tags.data_accesses 76121863
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu0.icache.ReadReq_hits::cpu0.inst 36135743
+system.cpu0.icache.ReadReq_hits::total 36135743
+system.cpu0.icache.demand_hits::cpu0.inst 36135743
+system.cpu0.icache.demand_hits::total 36135743
+system.cpu0.icache.overall_hits::cpu0.inst 36135743
+system.cpu0.icache.overall_hits::total 36135743
+system.cpu0.icache.ReadReq_misses::cpu0.inst 1301446
+system.cpu0.icache.ReadReq_misses::total 1301446
+system.cpu0.icache.demand_misses::cpu0.inst 1301446
+system.cpu0.icache.demand_misses::total 1301446
+system.cpu0.icache.overall_misses::cpu0.inst 1301446
+system.cpu0.icache.overall_misses::total 1301446
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14079162998
+system.cpu0.icache.ReadReq_miss_latency::total 14079162998
+system.cpu0.icache.demand_miss_latency::cpu0.inst 14079162998
+system.cpu0.icache.demand_miss_latency::total 14079162998
+system.cpu0.icache.overall_miss_latency::cpu0.inst 14079162998
+system.cpu0.icache.overall_miss_latency::total 14079162998
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 37437189
+system.cpu0.icache.ReadReq_accesses::total 37437189
+system.cpu0.icache.demand_accesses::cpu0.inst 37437189
+system.cpu0.icache.demand_accesses::total 37437189
+system.cpu0.icache.overall_accesses::cpu0.inst 37437189
+system.cpu0.icache.overall_accesses::total 37437189
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034763
+system.cpu0.icache.ReadReq_miss_rate::total 0.034763
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034763
+system.cpu0.icache.demand_miss_rate::total 0.034763
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034763
+system.cpu0.icache.overall_miss_rate::total 0.034763
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10818.092336
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10818.092336
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10818.092336
+system.cpu0.icache.demand_avg_miss_latency::total 10818.092336
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10818.092336
+system.cpu0.icache.overall_avg_miss_latency::total 10818.092336
+system.cpu0.icache.blocked_cycles::no_mshrs 1744158
+system.cpu0.icache.blocked_cycles::no_targets 1649
+system.cpu0.icache.blocked::no_mshrs 114378
+system.cpu0.icache.blocked::no_targets 13
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.249069
+system.cpu0.icache.avg_blocked_cycles::no_targets 126.846154
+system.cpu0.icache.writebacks::writebacks 1246927
+system.cpu0.icache.writebacks::total 1246927
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53960
+system.cpu0.icache.ReadReq_mshr_hits::total 53960
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 53960
+system.cpu0.icache.demand_mshr_hits::total 53960
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 53960
+system.cpu0.icache.overall_mshr_hits::total 53960
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1247486
+system.cpu0.icache.ReadReq_mshr_misses::total 1247486
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 1247486
+system.cpu0.icache.demand_mshr_misses::total 1247486
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 1247486
+system.cpu0.icache.overall_mshr_misses::total 1247486
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3008
+system.cpu0.icache.ReadReq_mshr_uncacheable::total 3008
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3008
+system.cpu0.icache.overall_mshr_uncacheable_misses::total 3008
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12746003489
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 12746003489
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12746003489
+system.cpu0.icache.demand_mshr_miss_latency::total 12746003489
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12746003489
+system.cpu0.icache.overall_mshr_miss_latency::total 12746003489
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 287646998
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 287646998
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 287646998
+system.cpu0.icache.overall_mshr_uncacheable_latency::total 287646998
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033322
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033322
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033322
+system.cpu0.icache.demand_mshr_miss_rate::total 0.033322
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033322
+system.cpu0.icache.overall_mshr_miss_rate::total 0.033322
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10217.351929
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10217.351929
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10217.351929
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10217.351929
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10217.351929
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10217.351929
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95627.326463
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95627.326463
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu0.l2cache.prefetcher.num_hwpf_issued 1845537
+system.cpu0.l2cache.prefetcher.pfIdentified 1848075
+system.cpu0.l2cache.prefetcher.pfBufferHit 2302
+system.cpu0.l2cache.prefetcher.pfInCache 0
+system.cpu0.l2cache.prefetcher.pfRemovedFull 0
+system.cpu0.l2cache.prefetcher.pfSpanPage 235117
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu0.l2cache.tags.replacements 270900
+system.cpu0.l2cache.tags.tagsinuse 15647.306576
+system.cpu0.l2cache.tags.total_refs 1885880
+system.cpu0.l2cache.tags.sampled_refs 286544
+system.cpu0.l2cache.tags.avg_refs 6.581467
+system.cpu0.l2cache.tags.warmup_cycle 0
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14497.138186
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 13.918104
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.957163
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1135.293123
+system.cpu0.l2cache.tags.occ_percent::writebacks 0.884835
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000849
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000058
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.069293
+system.cpu0.l2cache.tags.occ_percent::total 0.955036
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022 296
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15336
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 76
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 132
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 85
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 310
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1419
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7585
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4689
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1333
+system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018066
+system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732
+system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936035
+system.cpu0.l2cache.tags.tag_accesses 67543020
+system.cpu0.l2cache.tags.data_accesses 67543020
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55300
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 14597
+system.cpu0.l2cache.ReadReq_hits::total 69897
+system.cpu0.l2cache.WritebackDirty_hits::writebacks 482947
+system.cpu0.l2cache.WritebackDirty_hits::total 482947
+system.cpu0.l2cache.WritebackClean_hits::writebacks 1445214
+system.cpu0.l2cache.WritebackClean_hits::total 1445214
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1
+system.cpu0.l2cache.UpgradeReq_hits::total 1
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221007
+system.cpu0.l2cache.ReadExReq_hits::total 221007
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1177017
+system.cpu0.l2cache.ReadCleanReq_hits::total 1177017
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 389848
+system.cpu0.l2cache.ReadSharedReq_hits::total 389848
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55300
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker 14597
+system.cpu0.l2cache.demand_hits::cpu0.inst 1177017
+system.cpu0.l2cache.demand_hits::cpu0.data 610855
+system.cpu0.l2cache.demand_hits::total 1857769
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55300
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker 14597
+system.cpu0.l2cache.overall_hits::cpu0.inst 1177017
+system.cpu0.l2cache.overall_hits::cpu0.data 610855
+system.cpu0.l2cache.overall_hits::total 1857769
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 479
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 203
+system.cpu0.l2cache.ReadReq_misses::total 682
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55744
+system.cpu0.l2cache.UpgradeReq_misses::total 55744
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20286
+system.cpu0.l2cache.SCUpgradeReq_misses::total 20286
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data 49013
+system.cpu0.l2cache.ReadExReq_misses::total 49013
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 70426
+system.cpu0.l2cache.ReadCleanReq_misses::total 70426
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 107530
+system.cpu0.l2cache.ReadSharedReq_misses::total 107530
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 479
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker 203
+system.cpu0.l2cache.demand_misses::cpu0.inst 70426
+system.cpu0.l2cache.demand_misses::cpu0.data 156543
+system.cpu0.l2cache.demand_misses::total 227651
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 479
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker 203
+system.cpu0.l2cache.overall_misses::cpu0.inst 70426
+system.cpu0.l2cache.overall_misses::cpu0.data 156543
+system.cpu0.l2cache.overall_misses::total 227651
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 15373500
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4653500
+system.cpu0.l2cache.ReadReq_miss_latency::total 20027000
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 38174500
+system.cpu0.l2cache.UpgradeReq_miss_latency::total 38174500
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9811000
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9811000
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 488500
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 488500
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3399350500
+system.cpu0.l2cache.ReadExReq_miss_latency::total 3399350500
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3720671500
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3720671500
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3500442499
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3500442499
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 15373500
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4653500
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3720671500
+system.cpu0.l2cache.demand_miss_latency::cpu0.data 6899792999
+system.cpu0.l2cache.demand_miss_latency::total 10640491499
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 15373500
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4653500
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3720671500
+system.cpu0.l2cache.overall_miss_latency::cpu0.data 6899792999
+system.cpu0.l2cache.overall_miss_latency::total 10640491499
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55779
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 14800
+system.cpu0.l2cache.ReadReq_accesses::total 70579
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks 482947
+system.cpu0.l2cache.WritebackDirty_accesses::total 482947
+system.cpu0.l2cache.WritebackClean_accesses::writebacks 1445214
+system.cpu0.l2cache.WritebackClean_accesses::total 1445214
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55745
+system.cpu0.l2cache.UpgradeReq_accesses::total 55745
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20286
+system.cpu0.l2cache.SCUpgradeReq_accesses::total 20286
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270020
+system.cpu0.l2cache.ReadExReq_accesses::total 270020
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1247443
+system.cpu0.l2cache.ReadCleanReq_accesses::total 1247443
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 497378
+system.cpu0.l2cache.ReadSharedReq_accesses::total 497378
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55779
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 14800
+system.cpu0.l2cache.demand_accesses::cpu0.inst 1247443
+system.cpu0.l2cache.demand_accesses::cpu0.data 767398
+system.cpu0.l2cache.demand_accesses::total 2085420
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55779
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 14800
+system.cpu0.l2cache.overall_accesses::cpu0.inst 1247443
+system.cpu0.l2cache.overall_accesses::cpu0.data 767398
+system.cpu0.l2cache.overall_accesses::total 2085420
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008587
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.013716
+system.cpu0.l2cache.ReadReq_miss_rate::total 0.009663
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982
+system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1
+system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1
+system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.181516
+system.cpu0.l2cache.ReadExReq_miss_rate::total 0.181516
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056456
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056456
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.216194
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.216194
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008587
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.013716
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056456
+system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.203992
+system.cpu0.l2cache.demand_miss_rate::total 0.109163
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008587
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.013716
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056456
+system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.203992
+system.cpu0.l2cache.overall_miss_rate::total 0.109163
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32094.989562
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22923.645320
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29365.102639
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 684.818097
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 684.818097
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 483.634033
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 483.634033
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 488500
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 488500
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69356.099402
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69356.099402
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 52830.936018
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 52830.936018
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32553.171199
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32553.171199
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32094.989562
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22923.645320
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 52830.936018
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44076.023834
+system.cpu0.l2cache.demand_avg_miss_latency::total 46740.367927
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32094.989562
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22923.645320
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 52830.936018
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44076.023834
+system.cpu0.l2cache.overall_avg_miss_latency::total 46740.367927
+system.cpu0.l2cache.blocked_cycles::no_mshrs 65
+system.cpu0.l2cache.blocked_cycles::no_targets 0
+system.cpu0.l2cache.blocked::no_mshrs 2
+system.cpu0.l2cache.blocked::no_targets 0
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32.500000
+system.cpu0.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu0.l2cache.unused_prefetches 10571
+system.cpu0.l2cache.writebacks::writebacks 229619
+system.cpu0.l2cache.writebacks::total 229619
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2
+system.cpu0.l2cache.ReadReq_mshr_hits::total 3
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5914
+system.cpu0.l2cache.ReadExReq_mshr_hits::total 5914
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 35
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 35
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 783
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 783
+system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 35
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6697
+system.cpu0.l2cache.demand_mshr_hits::total 6735
+system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1
+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 35
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6697
+system.cpu0.l2cache.overall_mshr_hits::total 6735
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 478
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 201
+system.cpu0.l2cache.ReadReq_mshr_misses::total 679
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262504
+system.cpu0.l2cache.HardPFReq_mshr_misses::total 262504
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55744
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55744
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20286
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20286
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43099
+system.cpu0.l2cache.ReadExReq_mshr_misses::total 43099
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 70391
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 70391
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 106747
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 106747
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 478
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 201
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 70391
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data 149846
+system.cpu0.l2cache.demand_mshr_misses::total 220916
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 478
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 201
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 70391
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data 149846
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262504
+system.cpu0.l2cache.overall_mshr_misses::total 483420
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3008
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20557
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23565
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19259
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19259
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3008
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39816
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 42824
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 12487000
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3401500
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 15888500
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17362100115
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17362100115
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 963211500
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 963211500
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 307148999
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 307148999
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 404500
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 404500
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2235923000
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2235923000
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3297042000
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3297042000
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2814483999
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2814483999
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 12487000
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3401500
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3297042000
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5050406999
+system.cpu0.l2cache.demand_mshr_miss_latency::total 8363337499
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 12487000
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3401500
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3297042000
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5050406999
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17362100115
+system.cpu0.l2cache.overall_mshr_miss_latency::total 25725437614
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265086000
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4427632000
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4692718000
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 265086000
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4427632000
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4692718000
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008570
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013581
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009620
+system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf
+system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159614
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159614
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056428
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056428
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.214619
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.214619
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008570
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013581
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056428
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.195265
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.105934
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008570
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013581
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056428
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.195265
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231809
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26123.430962
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16922.885572
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23399.852725
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66140.325919
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 66140.325919
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17279.195967
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17279.195967
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15140.934585
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15140.934585
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 404500
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 404500
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 51878.767489
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 51878.767489
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46838.970891
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46838.970891
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26365.930649
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26365.930649
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26123.430962
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16922.885572
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46838.970891
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33703.982749
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37857.545397
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26123.430962
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16922.885572
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46838.970891
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33703.982749
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66140.325919
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53215.501249
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215383.178479
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 199139.316783
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111202.330721
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109581.496357
+system.cpu0.toL2Bus.snoop_filter.tot_requests 4070731
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2055789
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32513
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 214677
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212795
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1882
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu0.toL2Bus.trans_dist::ReadReq 104500
+system.cpu0.toL2Bus.trans_dist::ReadResp 1898226
+system.cpu0.toL2Bus.trans_dist::WriteReq 19259
+system.cpu0.toL2Bus.trans_dist::WriteResp 19259
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 712933
+system.cpu0.toL2Bus.trans_dist::WritebackClean 1476484
+system.cpu0.toL2Bus.trans_dist::CleanEvict 89217
+system.cpu0.toL2Bus.trans_dist::HardPFReq 330345
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 87736
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42858
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 113767
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23
+system.cpu0.toL2Bus.trans_dist::ReadExReq 288515
+system.cpu0.toL2Bus.trans_dist::ReadExResp 284911
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1247486
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 587670
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 3214
+system.cpu0.toL2Bus.trans_dist::InvalidateResp 16
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3747871
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2580540
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 32252
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119246
+system.cpu0.toL2Bus.pkt_count::total 6479909
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 159687744
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98905498
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 59200
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223116
+system.cpu0.toL2Bus.pkt_size::total 258875558
+system.cpu0.toL2Bus.snoops 928064
+system.cpu0.toL2Bus.snoopTraffic 18844764
+system.cpu0.toL2Bus.snoop_fanout::samples 3030798
+system.cpu0.toL2Bus.snoop_fanout::mean 0.088914
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.286792
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu0.toL2Bus.snoop_fanout::0 2763201 91.17% 91.17%
+system.cpu0.toL2Bus.snoop_fanout::1 265715 8.77% 99.94%
+system.cpu0.toL2Bus.snoop_fanout::2 1882 0.06% 100.00%
+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu0.toL2Bus.snoop_fanout::min_value 0
+system.cpu0.toL2Bus.snoop_fanout::max_value 2
+system.cpu0.toL2Bus.snoop_fanout::total 3030798
+system.cpu0.toL2Bus.reqLayer0.occupancy 4056109993
+system.cpu0.toL2Bus.reqLayer0.utilization 0.1
+system.cpu0.toL2Bus.snoopLayer0.occupancy 114607687
+system.cpu0.toL2Bus.snoopLayer0.utilization 0.0
+system.cpu0.toL2Bus.respLayer0.occupancy 1874701563
+system.cpu0.toL2Bus.respLayer0.utilization 0.1
+system.cpu0.toL2Bus.respLayer1.occupancy 1221063495
+system.cpu0.toL2Bus.respLayer1.utilization 0.0
+system.cpu0.toL2Bus.respLayer2.occupancy 17457988
+system.cpu0.toL2Bus.respLayer2.utilization 0.0
+system.cpu0.toL2Bus.respLayer3.occupancy 63497437
+system.cpu0.toL2Bus.respLayer3.utilization 0.0
+system.cpu1.branchPred.lookups 33856536
+system.cpu1.branchPred.condPredicted 11499926
+system.cpu1.branchPred.condIncorrect 284675
+system.cpu1.branchPred.BTBLookups 18698706
+system.cpu1.branchPred.BTBHits 5964801
+system.cpu1.branchPred.BTBCorrect 0
+system.cpu1.branchPred.BTBHitPct 31.899539
+system.cpu1.branchPred.usedRAS 12503485
+system.cpu1.branchPred.RASInCorrect 7773
+system.cpu1.branchPred.indirectLookups 9009930
+system.cpu1.branchPred.indirectHits 8973964
+system.cpu1.branchPred.indirectMisses 35966
+system.cpu1.branchPredindirectMispredicted 10796
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu1.dtb.walker.walks 21849
+system.cpu1.dtb.walker.walksShort 21849
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8829
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5889
+system.cpu1.dtb.walker.walksSquashedBefore 7131
+system.cpu1.dtb.walker.walkWaitTime::samples 14718
+system.cpu1.dtb.walker.walkWaitTime::mean 622.197309
+system.cpu1.dtb.walker.walkWaitTime::stdev 3420.964053
+system.cpu1.dtb.walker.walkWaitTime::0-4095 14045 95.43% 95.43%
+system.cpu1.dtb.walker.walkWaitTime::4096-8191 198 1.35% 96.77%
+system.cpu1.dtb.walker.walkWaitTime::8192-12287 226 1.54% 98.31%
+system.cpu1.dtb.walker.walkWaitTime::12288-16383 117 0.79% 99.10%
+system.cpu1.dtb.walker.walkWaitTime::16384-20479 18 0.12% 99.23%
+system.cpu1.dtb.walker.walkWaitTime::20480-24575 24 0.16% 99.39%
+system.cpu1.dtb.walker.walkWaitTime::24576-28671 7 0.05% 99.44%
+system.cpu1.dtb.walker.walkWaitTime::28672-32767 60 0.41% 99.84%
+system.cpu1.dtb.walker.walkWaitTime::32768-36863 9 0.06% 99.90%
+system.cpu1.dtb.walker.walkWaitTime::36864-40959 2 0.01% 99.92%
+system.cpu1.dtb.walker.walkWaitTime::40960-45055 7 0.05% 99.97%
+system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.97%
+system.cpu1.dtb.walker.walkWaitTime::57344-61439 4 0.03% 100.00%
+system.cpu1.dtb.walker.walkWaitTime::total 14718
+system.cpu1.dtb.walker.walkCompletionTime::samples 5502
+system.cpu1.dtb.walker.walkCompletionTime::mean 11145.856052
+system.cpu1.dtb.walker.walkCompletionTime::gmean 9651.411274
+system.cpu1.dtb.walker.walkCompletionTime::stdev 6265.989552
+system.cpu1.dtb.walker.walkCompletionTime::0-8191 1976 35.91% 35.91%
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2868 52.13% 88.04%
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575 470 8.54% 96.58%
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767 141 2.56% 99.15%
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959 21 0.38% 99.53%
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151 21 0.38% 99.91%
+system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.04% 99.95%
+system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.04% 99.98%
+system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 100.00%
+system.cpu1.dtb.walker.walkCompletionTime::total 5502
+system.cpu1.dtb.walker.walksPending::samples 77599950560
+system.cpu1.dtb.walker.walksPending::mean 0.191953
+system.cpu1.dtb.walker.walksPending::stdev 0.397564
+system.cpu1.dtb.walker.walksPending::0 62749526316 80.86% 80.86%
+system.cpu1.dtb.walker.walksPending::1 14828771744 19.11% 99.97%
+system.cpu1.dtb.walker.walksPending::2 12939000 0.02% 99.99%
+system.cpu1.dtb.walker.walksPending::3 4122000 0.01% 99.99%
+system.cpu1.dtb.walker.walksPending::4 1248000 0.00% 100.00%
+system.cpu1.dtb.walker.walksPending::5 878000 0.00% 100.00%
+system.cpu1.dtb.walker.walksPending::6 1208000 0.00% 100.00%
+system.cpu1.dtb.walker.walksPending::7 409500 0.00% 100.00%
+system.cpu1.dtb.walker.walksPending::8 186500 0.00% 100.00%
+system.cpu1.dtb.walker.walksPending::9 171500 0.00% 100.00%
+system.cpu1.dtb.walker.walksPending::10 140500 0.00% 100.00%
+system.cpu1.dtb.walker.walksPending::11 26500 0.00% 100.00%
+system.cpu1.dtb.walker.walksPending::12 158000 0.00% 100.00%
+system.cpu1.dtb.walker.walksPending::13 24500 0.00% 100.00%
+system.cpu1.dtb.walker.walksPending::14 7000 0.00% 100.00%
+system.cpu1.dtb.walker.walksPending::15 133500 0.00% 100.00%
+system.cpu1.dtb.walker.walksPending::total 77599950560
+system.cpu1.dtb.walker.walkPageSizes::4K 1910 75.32% 75.32%
+system.cpu1.dtb.walker.walkPageSizes::1M 626 24.68% 100.00%
+system.cpu1.dtb.walker.walkPageSizes::total 2536
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21849
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21849
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2536
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2536
+system.cpu1.dtb.walker.walkRequestOrigin::total 24385
+system.cpu1.dtb.inst_hits 0
+system.cpu1.dtb.inst_misses 0
+system.cpu1.dtb.read_hits 10130364
+system.cpu1.dtb.read_misses 18903
+system.cpu1.dtb.write_hits 6493071
+system.cpu1.dtb.write_misses 2946
+system.cpu1.dtb.flush_tlb 66
+system.cpu1.dtb.flush_tlb_mva 917
+system.cpu1.dtb.flush_tlb_mva_asid 0
+system.cpu1.dtb.flush_tlb_asid 0
+system.cpu1.dtb.flush_entries 1945
+system.cpu1.dtb.align_faults 56
+system.cpu1.dtb.prefetch_faults 419
+system.cpu1.dtb.domain_faults 0
+system.cpu1.dtb.perms_faults 404
+system.cpu1.dtb.read_accesses 10149267
+system.cpu1.dtb.write_accesses 6496017
+system.cpu1.dtb.inst_accesses 0
+system.cpu1.dtb.hits 16623435
+system.cpu1.dtb.misses 21849
+system.cpu1.dtb.accesses 16645284
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu1.istage2_mmu.stage2_tlb.hits 0
+system.cpu1.istage2_mmu.stage2_tlb.misses 0
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu1.itb.walker.walks 6540
+system.cpu1.itb.walker.walksShort 6540
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2898
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 3004
+system.cpu1.itb.walker.walksSquashedBefore 638
+system.cpu1.itb.walker.walkWaitTime::samples 5902
+system.cpu1.itb.walker.walkWaitTime::mean 572.602508
+system.cpu1.itb.walker.walkWaitTime::stdev 2755.073883
+system.cpu1.itb.walker.walkWaitTime::0-4095 5624 95.29% 95.29%
+system.cpu1.itb.walker.walkWaitTime::4096-8191 107 1.81% 97.10%
+system.cpu1.itb.walker.walkWaitTime::8192-12287 84 1.42% 98.53%
+system.cpu1.itb.walker.walkWaitTime::12288-16383 46 0.78% 99.31%
+system.cpu1.itb.walker.walkWaitTime::16384-20479 11 0.19% 99.49%
+system.cpu1.itb.walker.walkWaitTime::20480-24575 11 0.19% 99.68%
+system.cpu1.itb.walker.walkWaitTime::24576-28671 14 0.24% 99.92%
+system.cpu1.itb.walker.walkWaitTime::28672-32767 3 0.05% 99.97%
+system.cpu1.itb.walker.walkWaitTime::32768-36863 2 0.03% 100.00%
+system.cpu1.itb.walker.walkWaitTime::total 5902
+system.cpu1.itb.walker.walkCompletionTime::samples 1793
+system.cpu1.itb.walker.walkCompletionTime::mean 11951.756832
+system.cpu1.itb.walker.walkCompletionTime::gmean 10812.152888
+system.cpu1.itb.walker.walkCompletionTime::stdev 5747.285703
+system.cpu1.itb.walker.walkCompletionTime::0-8191 335 18.68% 18.68%
+system.cpu1.itb.walker.walkCompletionTime::8192-16383 1270 70.83% 89.51%
+system.cpu1.itb.walker.walkCompletionTime::16384-24575 103 5.74% 95.26%
+system.cpu1.itb.walker.walkCompletionTime::24576-32767 68 3.79% 99.05%
+system.cpu1.itb.walker.walkCompletionTime::32768-40959 7 0.39% 99.44%
+system.cpu1.itb.walker.walkCompletionTime::40960-49151 5 0.28% 99.72%
+system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.22% 99.94%
+system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00%
+system.cpu1.itb.walker.walkCompletionTime::total 1793
+system.cpu1.itb.walker.walksPending::samples 17450701916
+system.cpu1.itb.walker.walksPending::mean 0.923862
+system.cpu1.itb.walker.walksPending::stdev 0.265476
+system.cpu1.itb.walker.walksPending::0 1329821264 7.62% 7.62%
+system.cpu1.itb.walker.walksPending::1 16119757152 92.37% 99.99%
+system.cpu1.itb.walker.walksPending::2 1089500 0.01% 100.00%
+system.cpu1.itb.walker.walksPending::3 34000 0.00% 100.00%
+system.cpu1.itb.walker.walksPending::total 17450701916
+system.cpu1.itb.walker.walkPageSizes::4K 986 85.37% 85.37%
+system.cpu1.itb.walker.walkPageSizes::1M 169 14.63% 100.00%
+system.cpu1.itb.walker.walkPageSizes::total 1155
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6540
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6540
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1155
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1155
+system.cpu1.itb.walker.walkRequestOrigin::total 7695
+system.cpu1.itb.inst_hits 43481222
+system.cpu1.itb.inst_misses 6540
+system.cpu1.itb.read_hits 0
+system.cpu1.itb.read_misses 0
+system.cpu1.itb.write_hits 0
+system.cpu1.itb.write_misses 0
+system.cpu1.itb.flush_tlb 66
+system.cpu1.itb.flush_tlb_mva 917
+system.cpu1.itb.flush_tlb_mva_asid 0
+system.cpu1.itb.flush_tlb_asid 0
+system.cpu1.itb.flush_entries 1124
+system.cpu1.itb.align_faults 0
+system.cpu1.itb.prefetch_faults 0
+system.cpu1.itb.domain_faults 0
+system.cpu1.itb.perms_faults 576
+system.cpu1.itb.read_accesses 0
+system.cpu1.itb.write_accesses 0
+system.cpu1.itb.inst_accesses 43487762
+system.cpu1.itb.hits 43481222
+system.cpu1.itb.misses 6540
+system.cpu1.itb.accesses 43487762
+system.cpu1.numPwrStateTransitions 5559
+system.cpu1.pwrStateClkGateDist::samples 2780
+system.cpu1.pwrStateClkGateDist::mean 997664480.423022
+system.cpu1.pwrStateClkGateDist::stdev 25656911693.146706
+system.cpu1.pwrStateClkGateDist::underflows 1973 70.97% 70.97%
+system.cpu1.pwrStateClkGateDist::1000-5e+10 803 28.88% 99.86%
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89%
+system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93%
+system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96%
+system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00%
+system.cpu1.pwrStateClkGateDist::min_value 500
+system.cpu1.pwrStateClkGateDist::max_value 959983178648
+system.cpu1.pwrStateClkGateDist::total 2780
+system.cpu1.pwrStateResidencyTicks::ON 53154566924
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 2773507255576
+system.cpu1.numCycles 106309927
+system.cpu1.numWorkItemsStarted 0
+system.cpu1.numWorkItemsCompleted 0
+system.cpu1.fetch.icacheStallCycles 10498097
+system.cpu1.fetch.Insts 108666404
+system.cpu1.fetch.Branches 33856536
+system.cpu1.fetch.predictedBranches 27442250
+system.cpu1.fetch.Cycles 92289680
+system.cpu1.fetch.SquashCycles 3749118
+system.cpu1.fetch.TlbCycles 85770
+system.cpu1.fetch.MiscStallCycles 31095
+system.cpu1.fetch.PendingTrapStallCycles 184063
+system.cpu1.fetch.PendingQuiesceStallCycles 297655
+system.cpu1.fetch.IcacheWaitRetryStallCycles 23954
+system.cpu1.fetch.CacheLines 43480025
+system.cpu1.fetch.IcacheSquashes 112889
+system.cpu1.fetch.ItlbSquashes 2564
+system.cpu1.fetch.rateDist::samples 105284873
+system.cpu1.fetch.rateDist::mean 1.278950
+system.cpu1.fetch.rateDist::stdev 1.339501
+system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00%
+system.cpu1.fetch.rateDist::0 48620213 46.18% 46.18%
+system.cpu1.fetch.rateDist::1 13920994 13.22% 59.40%
+system.cpu1.fetch.rateDist::2 7497861 7.12% 66.52%
+system.cpu1.fetch.rateDist::3 35245805 33.48% 100.00%
+system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00%
+system.cpu1.fetch.rateDist::min_value 0
+system.cpu1.fetch.rateDist::max_value 3
+system.cpu1.fetch.rateDist::total 105284873
+system.cpu1.fetch.branchRate 0.318470
+system.cpu1.fetch.rate 1.022166
+system.cpu1.decode.IdleCycles 13319276
+system.cpu1.decode.BlockedCycles 62561551
+system.cpu1.decode.RunCycles 26582397
+system.cpu1.decode.UnblockCycles 1076287
+system.cpu1.decode.SquashCycles 1745362
+system.cpu1.decode.BranchResolved 4334662
+system.cpu1.decode.BranchMispred 132057
+system.cpu1.decode.DecodedInsts 67654617
+system.cpu1.decode.SquashedInsts 1099442
+system.cpu1.rename.SquashCycles 1745362
+system.cpu1.rename.IdleCycles 17699430
+system.cpu1.rename.BlockCycles 2382376
+system.cpu1.rename.serializeStallCycles 57513999
+system.cpu1.rename.RunCycles 23257908
+system.cpu1.rename.UnblockCycles 2685798
+system.cpu1.rename.RenamedInsts 54781694
+system.cpu1.rename.SquashedInsts 215020
+system.cpu1.rename.ROBFullEvents 263421
+system.cpu1.rename.IQFullEvents 37150
+system.cpu1.rename.LQFullEvents 16104
+system.cpu1.rename.SQFullEvents 1685151
+system.cpu1.rename.RenamedOperands 54669138
+system.cpu1.rename.RenameLookups 258824837
+system.cpu1.rename.int_rename_lookups 58242374
+system.cpu1.rename.fp_rename_lookups 1684
+system.cpu1.rename.CommittedMaps 52176870
+system.cpu1.rename.UndoneMaps 2492268
+system.cpu1.rename.serializingInsts 1869282
+system.cpu1.rename.tempSerializingInsts 1798188
+system.cpu1.rename.skidInsts 13053444
+system.cpu1.memDep0.insertedLoads 10385740
+system.cpu1.memDep0.insertedStores 6834302
+system.cpu1.memDep0.conflictingLoads 620040
+system.cpu1.memDep0.conflictingStores 744423
+system.cpu1.iq.iqInstsAdded 53920859
+system.cpu1.iq.iqNonSpecInstsAdded 577650
+system.cpu1.iq.iqInstsIssued 53700905
+system.cpu1.iq.iqSquashedInstsIssued 93975
+system.cpu1.iq.iqSquashedInstsExamined 3580325
+system.cpu1.iq.iqSquashedOperandsExamined 5050302
+system.cpu1.iq.iqSquashedNonSpecRemoved 42951
+system.cpu1.iq.issued_per_cycle::samples 105284873
+system.cpu1.iq.issued_per_cycle::mean 0.510053
+system.cpu1.iq.issued_per_cycle::stdev 0.848282
+system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00%
+system.cpu1.iq.issued_per_cycle::0 72131648 68.51% 68.51%
+system.cpu1.iq.issued_per_cycle::1 16498867 15.67% 84.18%
+system.cpu1.iq.issued_per_cycle::2 13045302 12.39% 96.57%
+system.cpu1.iq.issued_per_cycle::3 3324804 3.16% 99.73%
+system.cpu1.iq.issued_per_cycle::4 284238 0.27% 100.00%
+system.cpu1.iq.issued_per_cycle::5 14 0.00% 100.00%
+system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00%
+system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00%
+system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00%
+system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00%
+system.cpu1.iq.issued_per_cycle::min_value 0
+system.cpu1.iq.issued_per_cycle::max_value 5
+system.cpu1.iq.issued_per_cycle::total 105284873
+system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00%
+system.cpu1.iq.fu_full::IntAlu 2892150 45.27% 45.27%
+system.cpu1.iq.fu_full::IntMult 675 0.01% 45.28%
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.28%
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.28%
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.28%
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.28%
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.28%
+system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 45.28%
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.28%
+system.cpu1.iq.fu_full::FloatMisc 0 0.00% 45.28%
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.28%
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.28%
+system.cpu1.iq.fu_full::MemRead 1660115 25.98% 71.26%
+system.cpu1.iq.fu_full::MemWrite 1834595 28.71% 99.97%
+system.cpu1.iq.fu_full::FloatMemRead 657 0.01% 99.98%
+system.cpu1.iq.fu_full::FloatMemWrite 1063 0.02% 100.00%
+system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00%
+system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00%
+system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00%
+system.cpu1.iq.FU_type_0::IntAlu 36615210 68.18% 68.18%
+system.cpu1.iq.FU_type_0::IntMult 46387 0.09% 68.27%
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.27%
+system.cpu1.iq.FU_type_0::SimdFloatMisc 3321 0.01% 68.28%
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.28%
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.28%
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.28%
+system.cpu1.iq.FU_type_0::MemRead 10339677 19.25% 87.53%
+system.cpu1.iq.FU_type_0::MemWrite 6694137 12.47% 100.00%
+system.cpu1.iq.FU_type_0::FloatMemRead 718 0.00% 100.00%
+system.cpu1.iq.FU_type_0::FloatMemWrite 1389 0.00% 100.00%
+system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00%
+system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00%
+system.cpu1.iq.FU_type_0::total 53700905
+system.cpu1.iq.rate 0.505135
+system.cpu1.iq.fu_busy_cnt 6389255
+system.cpu1.iq.fu_busy_rate 0.118979
+system.cpu1.iq.int_inst_queue_reads 219163970
+system.cpu1.iq.int_inst_queue_writes 58086308
+system.cpu1.iq.int_inst_queue_wakeup_accesses 51738233
+system.cpu1.iq.fp_inst_queue_reads 5943
+system.cpu1.iq.fp_inst_queue_writes 2076
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 1788
+system.cpu1.iq.int_alu_accesses 60086267
+system.cpu1.iq.fp_alu_accesses 3827
+system.cpu1.iew.lsq.thread0.forwLoads 90396
+system.cpu1.iew.lsq.thread0.invAddrLoads 0
+system.cpu1.iew.lsq.thread0.squashedLoads 431306
+system.cpu1.iew.lsq.thread0.ignoredResponses 733
+system.cpu1.iew.lsq.thread0.memOrderViolation 9583
+system.cpu1.iew.lsq.thread0.squashedStores 270799
+system.cpu1.iew.lsq.thread0.invAddrSwpfs 0
+system.cpu1.iew.lsq.thread0.blockedLoads 0
+system.cpu1.iew.lsq.thread0.rescheduledLoads 51919
+system.cpu1.iew.lsq.thread0.cacheBlocked 76103
+system.cpu1.iew.iewIdleCycles 0
+system.cpu1.iew.iewSquashCycles 1745362
+system.cpu1.iew.iewBlockCycles 527630
+system.cpu1.iew.iewUnblockCycles 106857
+system.cpu1.iew.iewDispatchedInsts 54539543
+system.cpu1.iew.iewDispSquashedInsts 0
+system.cpu1.iew.iewDispLoadInsts 10385740
+system.cpu1.iew.iewDispStoreInsts 6834302
+system.cpu1.iew.iewDispNonSpecInsts 292191
+system.cpu1.iew.iewIQFullEvents 7794
+system.cpu1.iew.iewLSQFullEvents 92221
+system.cpu1.iew.memOrderViolationEvents 9583
+system.cpu1.iew.predictedTakenIncorrect 43494
+system.cpu1.iew.predictedNotTakenIncorrect 122854
+system.cpu1.iew.branchMispredicts 166348
+system.cpu1.iew.iewExecutedInsts 53458213
+system.cpu1.iew.iewExecLoadInsts 10243150
+system.cpu1.iew.iewExecSquashedInsts 220859
+system.cpu1.iew.exec_swp 0
+system.cpu1.iew.exec_nop 41034
+system.cpu1.iew.exec_refs 16887483
+system.cpu1.iew.exec_branches 11797547
+system.cpu1.iew.exec_stores 6644333
+system.cpu1.iew.exec_rate 0.502853
+system.cpu1.iew.wb_sent 53318582
+system.cpu1.iew.wb_count 51740021
+system.cpu1.iew.wb_producers 25143643
+system.cpu1.iew.wb_consumers 38375721
+system.cpu1.iew.wb_rate 0.486690
+system.cpu1.iew.wb_fanout 0.655197
+system.cpu1.commit.commitSquashedInsts 3338438
+system.cpu1.commit.commitNonSpecStalls 534699
+system.cpu1.commit.branchMispredicts 155478
+system.cpu1.commit.committed_per_cycle::samples 103395988
+system.cpu1.commit.committed_per_cycle::mean 0.492776
+system.cpu1.commit.committed_per_cycle::stdev 1.151561
+system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00%
+system.cpu1.commit.committed_per_cycle::0 77768989 75.21% 75.21%
+system.cpu1.commit.committed_per_cycle::1 14343522 13.87% 89.09%
+system.cpu1.commit.committed_per_cycle::2 6076298 5.88% 94.96%
+system.cpu1.commit.committed_per_cycle::3 698011 0.68% 95.64%
+system.cpu1.commit.committed_per_cycle::4 1980741 1.92% 97.55%
+system.cpu1.commit.committed_per_cycle::5 1651447 1.60% 99.15%
+system.cpu1.commit.committed_per_cycle::6 355898 0.34% 99.50%
+system.cpu1.commit.committed_per_cycle::7 123355 0.12% 99.62%
+system.cpu1.commit.committed_per_cycle::8 397727 0.38% 100.00%
+system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00%
+system.cpu1.commit.committed_per_cycle::min_value 0
+system.cpu1.commit.committed_per_cycle::max_value 8
+system.cpu1.commit.committed_per_cycle::total 103395988
+system.cpu1.commit.committedInsts 41357309
+system.cpu1.commit.committedOps 50951039
+system.cpu1.commit.swp_count 0
+system.cpu1.commit.refs 16517937
+system.cpu1.commit.loads 9954434
+system.cpu1.commit.membars 209769
+system.cpu1.commit.branches 11645032
+system.cpu1.commit.fp_insts 1784
+system.cpu1.commit.int_insts 45808082
+system.cpu1.commit.function_calls 3371130
+system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00%
+system.cpu1.commit.op_class_0::IntAlu 34384494 67.49% 67.49%
+system.cpu1.commit.op_class_0::IntMult 45287 0.09% 67.57%
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.57%
+system.cpu1.commit.op_class_0::SimdFloatMisc 3321 0.01% 67.58%
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.58%
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.58%
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.58%
+system.cpu1.commit.op_class_0::MemRead 9953918 19.54% 87.12%
+system.cpu1.commit.op_class_0::MemWrite 6562235 12.88% 100.00%
+system.cpu1.commit.op_class_0::FloatMemRead 516 0.00% 100.00%
+system.cpu1.commit.op_class_0::FloatMemWrite 1268 0.00% 100.00%
+system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00%
+system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
+system.cpu1.commit.op_class_0::total 50951039
+system.cpu1.commit.bw_lim_events 397727
+system.cpu1.rob.rob_reads 137209768
+system.cpu1.rob.rob_writes 110459061
+system.cpu1.timesIdled 59330
+system.cpu1.idleCycles 1025054
+system.cpu1.quiesceCycles 5546449070
+system.cpu1.committedInsts 41324453
+system.cpu1.committedOps 50918183
+system.cpu1.cpi 2.572567
+system.cpu1.cpi_total 2.572567
+system.cpu1.ipc 0.388717
+system.cpu1.ipc_total 0.388717
+system.cpu1.int_regfile_reads 56077038
+system.cpu1.int_regfile_writes 35632420
+system.cpu1.fp_regfile_reads 1386
+system.cpu1.fp_regfile_writes 516
+system.cpu1.cc_regfile_reads 190520711
+system.cpu1.cc_regfile_writes 15513474
+system.cpu1.misc_regfile_reads 212139107
+system.cpu1.misc_regfile_writes 383820
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu1.dcache.tags.replacements 187628
+system.cpu1.dcache.tags.tagsinuse 471.600220
+system.cpu1.dcache.tags.total_refs 15706302
+system.cpu1.dcache.tags.sampled_refs 187984
+system.cpu1.dcache.tags.avg_refs 83.551270
+system.cpu1.dcache.tags.warmup_cycle 89314291000
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.600220
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.921094
+system.cpu1.dcache.tags.occ_percent::total 0.921094
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 356
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 343
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.695312
+system.cpu1.dcache.tags.tag_accesses 32901630
+system.cpu1.dcache.tags.data_accesses 32901630
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu1.dcache.ReadReq_hits::cpu1.data 9540576
+system.cpu1.dcache.ReadReq_hits::total 9540576
+system.cpu1.dcache.WriteReq_hits::cpu1.data 5911612
+system.cpu1.dcache.WriteReq_hits::total 5911612
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49749
+system.cpu1.dcache.SoftPFReq_hits::total 49749
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78978
+system.cpu1.dcache.LoadLockedReq_hits::total 78978
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71123
+system.cpu1.dcache.StoreCondReq_hits::total 71123
+system.cpu1.dcache.demand_hits::cpu1.data 15452188
+system.cpu1.dcache.demand_hits::total 15452188
+system.cpu1.dcache.overall_hits::cpu1.data 15501937
+system.cpu1.dcache.overall_hits::total 15501937
+system.cpu1.dcache.ReadReq_misses::cpu1.data 214839
+system.cpu1.dcache.ReadReq_misses::total 214839
+system.cpu1.dcache.WriteReq_misses::cpu1.data 395786
+system.cpu1.dcache.WriteReq_misses::total 395786
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30189
+system.cpu1.dcache.SoftPFReq_misses::total 30189
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18481
+system.cpu1.dcache.LoadLockedReq_misses::total 18481
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23621
+system.cpu1.dcache.StoreCondReq_misses::total 23621
+system.cpu1.dcache.demand_misses::cpu1.data 610625
+system.cpu1.dcache.demand_misses::total 610625
+system.cpu1.dcache.overall_misses::cpu1.data 640814
+system.cpu1.dcache.overall_misses::total 640814
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3580081500
+system.cpu1.dcache.ReadReq_miss_latency::total 3580081500
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10073915460
+system.cpu1.dcache.WriteReq_miss_latency::total 10073915460
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363169000
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 363169000
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 554398000
+system.cpu1.dcache.StoreCondReq_miss_latency::total 554398000
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 364000
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 364000
+system.cpu1.dcache.demand_miss_latency::cpu1.data 13653996960
+system.cpu1.dcache.demand_miss_latency::total 13653996960
+system.cpu1.dcache.overall_miss_latency::cpu1.data 13653996960
+system.cpu1.dcache.overall_miss_latency::total 13653996960
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 9755415
+system.cpu1.dcache.ReadReq_accesses::total 9755415
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 6307398
+system.cpu1.dcache.WriteReq_accesses::total 6307398
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79938
+system.cpu1.dcache.SoftPFReq_accesses::total 79938
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97459
+system.cpu1.dcache.LoadLockedReq_accesses::total 97459
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94744
+system.cpu1.dcache.StoreCondReq_accesses::total 94744
+system.cpu1.dcache.demand_accesses::cpu1.data 16062813
+system.cpu1.dcache.demand_accesses::total 16062813
+system.cpu1.dcache.overall_accesses::cpu1.data 16142751
+system.cpu1.dcache.overall_accesses::total 16142751
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022023
+system.cpu1.dcache.ReadReq_miss_rate::total 0.022023
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062749
+system.cpu1.dcache.WriteReq_miss_rate::total 0.062749
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377655
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377655
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.189628
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.189628
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249314
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249314
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038015
+system.cpu1.dcache.demand_miss_rate::total 0.038015
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039697
+system.cpu1.dcache.overall_miss_rate::total 0.039697
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16664.020499
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16664.020499
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25452.935324
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 25452.935324
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19650.938802
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19650.938802
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23470.555861
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23470.555861
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22360.691030
+system.cpu1.dcache.demand_avg_miss_latency::total 22360.691030
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21307.270066
+system.cpu1.dcache.overall_avg_miss_latency::total 21307.270066
+system.cpu1.dcache.blocked_cycles::no_mshrs 414
+system.cpu1.dcache.blocked_cycles::no_targets 1473739
+system.cpu1.dcache.blocked::no_mshrs 30
+system.cpu1.dcache.blocked::no_targets 39634
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.800000
+system.cpu1.dcache.avg_blocked_cycles::no_targets 37.183706
+system.cpu1.dcache.writebacks::writebacks 187628
+system.cpu1.dcache.writebacks::total 187628
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 78490
+system.cpu1.dcache.ReadReq_mshr_hits::total 78490
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 305589
+system.cpu1.dcache.WriteReq_mshr_hits::total 305589
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13156
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13156
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 384079
+system.cpu1.dcache.demand_mshr_hits::total 384079
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 384079
+system.cpu1.dcache.overall_mshr_hits::total 384079
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136349
+system.cpu1.dcache.ReadReq_mshr_misses::total 136349
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90197
+system.cpu1.dcache.WriteReq_mshr_misses::total 90197
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28878
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 28878
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5325
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5325
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23621
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 23621
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 226546
+system.cpu1.dcache.demand_mshr_misses::total 226546
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 255424
+system.cpu1.dcache.overall_mshr_misses::total 255424
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14314
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14314
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11649
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11649
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 25963
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total 25963
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1986218000
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1986218000
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2446603467
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2446603467
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 492540500
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 492540500
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93650000
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93650000
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 530786000
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 530786000
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 355000
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 355000
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4432821467
+system.cpu1.dcache.demand_mshr_miss_latency::total 4432821467
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4925361967
+system.cpu1.dcache.overall_mshr_miss_latency::total 4925361967
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2472668500
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2472668500
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2472668500
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2472668500
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013977
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013977
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014300
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014300
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361255
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361255
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054638
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054638
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249314
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249314
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014104
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.014104
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015823
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.015823
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14567.162209
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14567.162209
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27125.109117
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27125.109117
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17055.907611
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17055.907611
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17586.854460
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17586.854460
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22470.936878
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22470.936878
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19566.981836
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19566.981836
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19283.082118
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19283.082118
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172744.760374
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172744.760374
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95238.165851
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95238.165851
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu1.icache.tags.replacements 599198
+system.cpu1.icache.tags.tagsinuse 499.435924
+system.cpu1.icache.tags.total_refs 42856397
+system.cpu1.icache.tags.sampled_refs 599710
+system.cpu1.icache.tags.avg_refs 71.461868
+system.cpu1.icache.tags.warmup_cycle 79139515500
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.435924
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975461
+system.cpu1.icache.tags.occ_percent::total 0.975461
+system.cpu1.icache.tags.occ_task_id_blocks::1024 512
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 494
+system.cpu1.icache.tags.age_task_id_blocks_1024::3 18
+system.cpu1.icache.tags.occ_task_id_percent::1024 1
+system.cpu1.icache.tags.tag_accesses 87559206
+system.cpu1.icache.tags.data_accesses 87559206
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu1.icache.ReadReq_hits::cpu1.inst 42856397
+system.cpu1.icache.ReadReq_hits::total 42856397
+system.cpu1.icache.demand_hits::cpu1.inst 42856397
+system.cpu1.icache.demand_hits::total 42856397
+system.cpu1.icache.overall_hits::cpu1.inst 42856397
+system.cpu1.icache.overall_hits::total 42856397
+system.cpu1.icache.ReadReq_misses::cpu1.inst 623349
+system.cpu1.icache.ReadReq_misses::total 623349
+system.cpu1.icache.demand_misses::cpu1.inst 623349
+system.cpu1.icache.demand_misses::total 623349
+system.cpu1.icache.overall_misses::cpu1.inst 623349
+system.cpu1.icache.overall_misses::total 623349
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5906635489
+system.cpu1.icache.ReadReq_miss_latency::total 5906635489
+system.cpu1.icache.demand_miss_latency::cpu1.inst 5906635489
+system.cpu1.icache.demand_miss_latency::total 5906635489
+system.cpu1.icache.overall_miss_latency::cpu1.inst 5906635489
+system.cpu1.icache.overall_miss_latency::total 5906635489
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 43479746
+system.cpu1.icache.ReadReq_accesses::total 43479746
+system.cpu1.icache.demand_accesses::cpu1.inst 43479746
+system.cpu1.icache.demand_accesses::total 43479746
+system.cpu1.icache.overall_accesses::cpu1.inst 43479746
+system.cpu1.icache.overall_accesses::total 43479746
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014337
+system.cpu1.icache.ReadReq_miss_rate::total 0.014337
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014337
+system.cpu1.icache.demand_miss_rate::total 0.014337
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014337
+system.cpu1.icache.overall_miss_rate::total 0.014337
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9475.647653
+system.cpu1.icache.ReadReq_avg_miss_latency::total 9475.647653
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9475.647653
+system.cpu1.icache.demand_avg_miss_latency::total 9475.647653
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9475.647653
+system.cpu1.icache.overall_avg_miss_latency::total 9475.647653
+system.cpu1.icache.blocked_cycles::no_mshrs 537277
+system.cpu1.icache.blocked_cycles::no_targets 290
+system.cpu1.icache.blocked::no_mshrs 42160
+system.cpu1.icache.blocked::no_targets 1
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.743762
+system.cpu1.icache.avg_blocked_cycles::no_targets 290
+system.cpu1.icache.writebacks::writebacks 599198
+system.cpu1.icache.writebacks::total 599198
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 23635
+system.cpu1.icache.ReadReq_mshr_hits::total 23635
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 23635
+system.cpu1.icache.demand_mshr_hits::total 23635
+system.cpu1.icache.overall_mshr_hits::cpu1.inst 23635
+system.cpu1.icache.overall_mshr_hits::total 23635
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 599714
+system.cpu1.icache.ReadReq_mshr_misses::total 599714
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 599714
+system.cpu1.icache.demand_mshr_misses::total 599714
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 599714
+system.cpu1.icache.overall_mshr_misses::total 599714
+system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101
+system.cpu1.icache.ReadReq_mshr_uncacheable::total 101
+system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101
+system.cpu1.icache.overall_mshr_uncacheable_misses::total 101
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5406083268
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 5406083268
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5406083268
+system.cpu1.icache.demand_mshr_miss_latency::total 5406083268
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5406083268
+system.cpu1.icache.overall_mshr_miss_latency::total 5406083268
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9499999
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9499999
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9499999
+system.cpu1.icache.overall_mshr_uncacheable_latency::total 9499999
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013793
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013793
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013793
+system.cpu1.icache.demand_mshr_miss_rate::total 0.013793
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013793
+system.cpu1.icache.overall_mshr_miss_rate::total 0.013793
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9014.435661
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9014.435661
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9014.435661
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 9014.435661
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9014.435661
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 9014.435661
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94059.396040
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94059.396040
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94059.396040
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94059.396040
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu1.l2cache.prefetcher.num_hwpf_issued 194784
+system.cpu1.l2cache.prefetcher.pfIdentified 195407
+system.cpu1.l2cache.prefetcher.pfBufferHit 558
+system.cpu1.l2cache.prefetcher.pfInCache 0
+system.cpu1.l2cache.prefetcher.pfRemovedFull 0
+system.cpu1.l2cache.prefetcher.pfSpanPage 59729
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu1.l2cache.tags.replacements 44486
+system.cpu1.l2cache.tags.tagsinuse 14698.349014
+system.cpu1.l2cache.tags.total_refs 706307
+system.cpu1.l2cache.tags.sampled_refs 58660
+system.cpu1.l2cache.tags.avg_refs 12.040692
+system.cpu1.l2cache.tags.warmup_cycle 0
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14304.590016
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.876237
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.943800
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 379.938962
+system.cpu1.l2cache.tags.occ_percent::writebacks 0.873083
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000664
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000180
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023190
+system.cpu1.l2cache.tags.occ_percent::total 0.897116
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022 318
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023 32
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13824
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 203
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 107
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1792
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8665
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3367
+system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.019409
+system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953
+system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.843750
+system.cpu1.l2cache.tags.tag_accesses 27733555
+system.cpu1.l2cache.tags.data_accesses 27733555
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17104
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7053
+system.cpu1.l2cache.ReadReq_hits::total 24157
+system.cpu1.l2cache.WritebackDirty_hits::writebacks 114566
+system.cpu1.l2cache.WritebackDirty_hits::total 114566
+system.cpu1.l2cache.WritebackClean_hits::writebacks 659759
+system.cpu1.l2cache.WritebackClean_hits::total 659759
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27223
+system.cpu1.l2cache.ReadExReq_hits::total 27223
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 575192
+system.cpu1.l2cache.ReadCleanReq_hits::total 575192
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98691
+system.cpu1.l2cache.ReadSharedReq_hits::total 98691
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17104
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7053
+system.cpu1.l2cache.demand_hits::cpu1.inst 575192
+system.cpu1.l2cache.demand_hits::cpu1.data 125914
+system.cpu1.l2cache.demand_hits::total 725263
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17104
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7053
+system.cpu1.l2cache.overall_hits::cpu1.inst 575192
+system.cpu1.l2cache.overall_hits::cpu1.data 125914
+system.cpu1.l2cache.overall_hits::total 725263
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 516
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 298
+system.cpu1.l2cache.ReadReq_misses::total 814
+system.cpu1.l2cache.WritebackDirty_misses::writebacks 1
+system.cpu1.l2cache.WritebackDirty_misses::total 1
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29696
+system.cpu1.l2cache.UpgradeReq_misses::total 29696
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23619
+system.cpu1.l2cache.SCUpgradeReq_misses::total 23619
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33958
+system.cpu1.l2cache.ReadExReq_misses::total 33958
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 24519
+system.cpu1.l2cache.ReadCleanReq_misses::total 24519
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 71840
+system.cpu1.l2cache.ReadSharedReq_misses::total 71840
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 516
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker 298
+system.cpu1.l2cache.demand_misses::cpu1.inst 24519
+system.cpu1.l2cache.demand_misses::cpu1.data 105798
+system.cpu1.l2cache.demand_misses::total 131131
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 516
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker 298
+system.cpu1.l2cache.overall_misses::cpu1.inst 24519
+system.cpu1.l2cache.overall_misses::cpu1.data 105798
+system.cpu1.l2cache.overall_misses::total 131131
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10977500
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6112500
+system.cpu1.l2cache.ReadReq_miss_latency::total 17090000
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 12764500
+system.cpu1.l2cache.UpgradeReq_miss_latency::total 12764500
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 18511500
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 18511500
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 340498
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 340498
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1470183498
+system.cpu1.l2cache.ReadExReq_miss_latency::total 1470183498
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1005329500
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1005329500
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1655316999
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1655316999
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10977500
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6112500
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1005329500
+system.cpu1.l2cache.demand_miss_latency::cpu1.data 3125500497
+system.cpu1.l2cache.demand_miss_latency::total 4147919997
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10977500
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6112500
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1005329500
+system.cpu1.l2cache.overall_miss_latency::cpu1.data 3125500497
+system.cpu1.l2cache.overall_miss_latency::total 4147919997
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17620
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7351
+system.cpu1.l2cache.ReadReq_accesses::total 24971
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114567
+system.cpu1.l2cache.WritebackDirty_accesses::total 114567
+system.cpu1.l2cache.WritebackClean_accesses::writebacks 659759
+system.cpu1.l2cache.WritebackClean_accesses::total 659759
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29696
+system.cpu1.l2cache.UpgradeReq_accesses::total 29696
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23619
+system.cpu1.l2cache.SCUpgradeReq_accesses::total 23619
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61181
+system.cpu1.l2cache.ReadExReq_accesses::total 61181
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 599711
+system.cpu1.l2cache.ReadCleanReq_accesses::total 599711
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 170531
+system.cpu1.l2cache.ReadSharedReq_accesses::total 170531
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17620
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7351
+system.cpu1.l2cache.demand_accesses::cpu1.inst 599711
+system.cpu1.l2cache.demand_accesses::cpu1.data 231712
+system.cpu1.l2cache.demand_accesses::total 856394
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17620
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7351
+system.cpu1.l2cache.overall_accesses::cpu1.inst 599711
+system.cpu1.l2cache.overall_accesses::cpu1.data 231712
+system.cpu1.l2cache.overall_accesses::total 856394
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.029285
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.040539
+system.cpu1.l2cache.ReadReq_miss_rate::total 0.032598
+system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000009
+system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000009
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1
+system.cpu1.l2cache.UpgradeReq_miss_rate::total 1
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555042
+system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555042
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040885
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040885
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.421272
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.421272
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.029285
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.040539
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040885
+system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.456593
+system.cpu1.l2cache.demand_miss_rate::total 0.153120
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.029285
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.040539
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040885
+system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.456593
+system.cpu1.l2cache.overall_miss_rate::total 0.153120
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21274.224806
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20511.744966
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20995.085995
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 429.839036
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 429.839036
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 783.754604
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 783.754604
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 170249
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 170249
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43294.172154
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43294.172154
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 41002.059627
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 41002.059627
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23041.717692
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23041.717692
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21274.224806
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20511.744966
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41002.059627
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29542.151052
+system.cpu1.l2cache.demand_avg_miss_latency::total 31631.879548
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21274.224806
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20511.744966
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41002.059627
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29542.151052
+system.cpu1.l2cache.overall_avg_miss_latency::total 31631.879548
+system.cpu1.l2cache.blocked_cycles::no_mshrs 124
+system.cpu1.l2cache.blocked_cycles::no_targets 0
+system.cpu1.l2cache.blocked::no_mshrs 4
+system.cpu1.l2cache.blocked::no_targets 0
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 31
+system.cpu1.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu1.l2cache.unused_prefetches 837
+system.cpu1.l2cache.writebacks::writebacks 31737
+system.cpu1.l2cache.writebacks::total 31737
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1
+system.cpu1.l2cache.ReadReq_mshr_hits::total 2
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 425
+system.cpu1.l2cache.ReadExReq_mshr_hits::total 425
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 5
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 5
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 78
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 78
+system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data 503
+system.cpu1.l2cache.demand_mshr_hits::total 510
+system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1
+system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data 503
+system.cpu1.l2cache.overall_mshr_hits::total 510
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 515
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 297
+system.cpu1.l2cache.ReadReq_mshr_misses::total 812
+system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1
+system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25135
+system.cpu1.l2cache.HardPFReq_mshr_misses::total 25135
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29696
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29696
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23619
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23619
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33533
+system.cpu1.l2cache.ReadExReq_mshr_misses::total 33533
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 24514
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 24514
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 71762
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 71762
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 515
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 297
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 24514
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data 105295
+system.cpu1.l2cache.demand_mshr_misses::total 130621
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 515
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 297
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 24514
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data 105295
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25135
+system.cpu1.l2cache.overall_mshr_misses::total 155756
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 101
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14314
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14415
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11649
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11649
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 101
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 25963
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26064
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7869500
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4323000
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 12192500
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1088203479
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1088203479
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 457505000
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 457505000
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 353329500
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 353329500
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 286498
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 286498
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1213372500
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1213372500
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 858150000
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 858150000
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1222251499
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1222251499
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7869500
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4323000
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 858150000
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2435623999
+system.cpu1.l2cache.demand_mshr_miss_latency::total 3305966499
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7869500
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4323000
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 858150000
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2435623999
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1088203479
+system.cpu1.l2cache.overall_mshr_miss_latency::total 4394169978
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8742000
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2358111500
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2366853500
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8742000
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2358111500
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2366853500
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.029228
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.040403
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032518
+system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000009
+system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000009
+system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf
+system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548095
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548095
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.040876
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040876
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.420815
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.420815
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.029228
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.040403
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.040876
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454422
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152524
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.029228
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.040403
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.040876
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454422
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181874
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15280.582524
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14555.555556
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15015.394089
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43294.349672
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43294.349672
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15406.283675
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15406.283675
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14959.545281
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14959.545281
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 143249
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 143249
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36184.430263
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36184.430263
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35006.526883
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35006.526883
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17032.015537
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17032.015537
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15280.582524
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14555.555556
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35006.526883
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23131.430733
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25309.609473
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15280.582524
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14555.555556
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35006.526883
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23131.430733
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43294.349672
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28211.882547
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86554.455446
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164741.616599
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164193.791190
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86554.455446
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90825.848323
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90809.296347
+system.cpu1.toL2Bus.snoop_filter.tot_requests 1681560
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 850148
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12507
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 115194
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106428
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8766
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.cpu1.toL2Bus.trans_dist::ReadReq 43928
+system.cpu1.toL2Bus.trans_dist::ReadResp 852508
+system.cpu1.toL2Bus.trans_dist::WriteReq 11649
+system.cpu1.toL2Bus.trans_dist::WriteResp 11649
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 147702
+system.cpu1.toL2Bus.trans_dist::WritebackClean 672258
+system.cpu1.toL2Bus.trans_dist::CleanEvict 29967
+system.cpu1.toL2Bus.trans_dist::HardPFReq 30289
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 73276
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42024
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 86111
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 16
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23
+system.cpu1.toL2Bus.trans_dist::ReadExReq 68535
+system.cpu1.toL2Bus.trans_dist::ReadExResp 65708
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 599714
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 275003
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 370
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1798825
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 885290
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 16257
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38227
+system.cpu1.toL2Bus.pkt_count::total 2738599
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 76731792
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29683362
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29404
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70480
+system.cpu1.toL2Bus.pkt_size::total 106515038
+system.cpu1.toL2Bus.snoops 347810
+system.cpu1.toL2Bus.snoopTraffic 4883000
+system.cpu1.toL2Bus.snoop_fanout::samples 1207909
+system.cpu1.toL2Bus.snoop_fanout::mean 0.121252
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.347943
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu1.toL2Bus.snoop_fanout::0 1070214 88.60% 88.60%
+system.cpu1.toL2Bus.snoop_fanout::1 128929 10.67% 99.27%
+system.cpu1.toL2Bus.snoop_fanout::2 8766 0.73% 100.00%
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu1.toL2Bus.snoop_fanout::min_value 0
+system.cpu1.toL2Bus.snoop_fanout::max_value 2
+system.cpu1.toL2Bus.snoop_fanout::total 1207909
+system.cpu1.toL2Bus.reqLayer0.occupancy 1656226494
+system.cpu1.toL2Bus.reqLayer0.utilization 0.1
+system.cpu1.toL2Bus.snoopLayer0.occupancy 80749811
+system.cpu1.toL2Bus.snoopLayer0.utilization 0.0
+system.cpu1.toL2Bus.respLayer0.occupancy 899776788
+system.cpu1.toL2Bus.respLayer0.utilization 0.0
+system.cpu1.toL2Bus.respLayer1.occupancy 396056629
+system.cpu1.toL2Bus.respLayer1.utilization 0.0
+system.cpu1.toL2Bus.respLayer2.occupancy 8916479
+system.cpu1.toL2Bus.respLayer2.utilization 0.0
+system.cpu1.toL2Bus.respLayer3.occupancy 20619475
+system.cpu1.toL2Bus.respLayer3.utilization 0.0
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.iobus.trans_dist::ReadReq 31002
+system.iobus.trans_dist::ReadResp 31002
+system.iobus.trans_dist::WriteReq 59421
+system.iobus.trans_dist::WriteResp 59421
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268
+system.iobus.pkt_count_system.bridge.master::total 107894
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952
+system.iobus.pkt_count_system.realview.ide.dma::total 72952
+system.iobus.pkt_count::total 180846
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536
+system.iobus.pkt_size_system.bridge.master::total 162784
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248
+system.iobus.pkt_size_system.realview.ide.dma::total 2321248
+system.iobus.pkt_size::total 2484032
+system.iobus.reqLayer0.occupancy 40389001
+system.iobus.reqLayer0.utilization 0.0
+system.iobus.reqLayer1.occupancy 112500
+system.iobus.reqLayer1.utilization 0.0
+system.iobus.reqLayer2.occupancy 329500
+system.iobus.reqLayer2.utilization 0.0
+system.iobus.reqLayer3.occupancy 32000
+system.iobus.reqLayer3.utilization 0.0
+system.iobus.reqLayer4.occupancy 16000
+system.iobus.reqLayer4.utilization 0.0
+system.iobus.reqLayer7.occupancy 87000
+system.iobus.reqLayer7.utilization 0.0
+system.iobus.reqLayer8.occupancy 567000
+system.iobus.reqLayer8.utilization 0.0
+system.iobus.reqLayer10.occupancy 22500
+system.iobus.reqLayer10.utilization 0.0
+system.iobus.reqLayer13.occupancy 11500
+system.iobus.reqLayer13.utilization 0.0
+system.iobus.reqLayer14.occupancy 12000
+system.iobus.reqLayer14.utilization 0.0
+system.iobus.reqLayer15.occupancy 12000
+system.iobus.reqLayer15.utilization 0.0
+system.iobus.reqLayer16.occupancy 53000
+system.iobus.reqLayer16.utilization 0.0
+system.iobus.reqLayer17.occupancy 11500
+system.iobus.reqLayer17.utilization 0.0
+system.iobus.reqLayer18.occupancy 10000
+system.iobus.reqLayer18.utilization 0.0
+system.iobus.reqLayer19.occupancy 2500
+system.iobus.reqLayer19.utilization 0.0
+system.iobus.reqLayer20.occupancy 9000
+system.iobus.reqLayer20.utilization 0.0
+system.iobus.reqLayer21.occupancy 11500
+system.iobus.reqLayer21.utilization 0.0
+system.iobus.reqLayer23.occupancy 6111500
+system.iobus.reqLayer23.utilization 0.0
+system.iobus.reqLayer24.occupancy 33791000
+system.iobus.reqLayer24.utilization 0.0
+system.iobus.reqLayer25.occupancy 187815532
+system.iobus.reqLayer25.utilization 0.0
+system.iobus.respLayer0.occupancy 84697000
+system.iobus.respLayer0.utilization 0.0
+system.iobus.respLayer3.occupancy 36776000
+system.iobus.respLayer3.utilization 0.0
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.iocache.tags.replacements 36458
+system.iocache.tags.tagsinuse 14.554354
+system.iocache.tags.total_refs 0
+system.iocache.tags.sampled_refs 36474
+system.iocache.tags.avg_refs 0
+system.iocache.tags.warmup_cycle 255387586000
+system.iocache.tags.occ_blocks::realview.ide 14.554354
+system.iocache.tags.occ_percent::realview.ide 0.909647
+system.iocache.tags.occ_percent::total 0.909647
+system.iocache.tags.occ_task_id_blocks::1023 16
+system.iocache.tags.age_task_id_blocks_1023::3 16
+system.iocache.tags.occ_task_id_percent::1023 1
+system.iocache.tags.tag_accesses 328284
+system.iocache.tags.data_accesses 328284
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.iocache.ReadReq_misses::realview.ide 252
+system.iocache.ReadReq_misses::total 252
+system.iocache.WriteLineReq_misses::realview.ide 36224
+system.iocache.WriteLineReq_misses::total 36224
+system.iocache.demand_misses::realview.ide 36476
+system.iocache.demand_misses::total 36476
+system.iocache.overall_misses::realview.ide 36476
+system.iocache.overall_misses::total 36476
+system.iocache.ReadReq_miss_latency::realview.ide 40648874
+system.iocache.ReadReq_miss_latency::total 40648874
+system.iocache.WriteLineReq_miss_latency::realview.ide 4362564658
+system.iocache.WriteLineReq_miss_latency::total 4362564658
+system.iocache.demand_miss_latency::realview.ide 4403213532
+system.iocache.demand_miss_latency::total 4403213532
+system.iocache.overall_miss_latency::realview.ide 4403213532
+system.iocache.overall_miss_latency::total 4403213532
+system.iocache.ReadReq_accesses::realview.ide 252
+system.iocache.ReadReq_accesses::total 252
+system.iocache.WriteLineReq_accesses::realview.ide 36224
+system.iocache.WriteLineReq_accesses::total 36224
+system.iocache.demand_accesses::realview.ide 36476
+system.iocache.demand_accesses::total 36476
+system.iocache.overall_accesses::realview.ide 36476
+system.iocache.overall_accesses::total 36476
+system.iocache.ReadReq_miss_rate::realview.ide 1
+system.iocache.ReadReq_miss_rate::total 1
+system.iocache.WriteLineReq_miss_rate::realview.ide 1
+system.iocache.WriteLineReq_miss_rate::total 1
+system.iocache.demand_miss_rate::realview.ide 1
+system.iocache.demand_miss_rate::total 1
+system.iocache.overall_miss_rate::realview.ide 1
+system.iocache.overall_miss_rate::total 1
+system.iocache.ReadReq_avg_miss_latency::realview.ide 161305.055556
+system.iocache.ReadReq_avg_miss_latency::total 161305.055556
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120432.990780
+system.iocache.WriteLineReq_avg_miss_latency::total 120432.990780
+system.iocache.demand_avg_miss_latency::realview.ide 120715.361662
+system.iocache.demand_avg_miss_latency::total 120715.361662
+system.iocache.overall_avg_miss_latency::realview.ide 120715.361662
+system.iocache.overall_avg_miss_latency::total 120715.361662
+system.iocache.blocked_cycles::no_mshrs 38
+system.iocache.blocked_cycles::no_targets 0
+system.iocache.blocked::no_mshrs 4
+system.iocache.blocked::no_targets 0
+system.iocache.avg_blocked_cycles::no_mshrs 9.500000
+system.iocache.avg_blocked_cycles::no_targets nan
+system.iocache.writebacks::writebacks 36206
+system.iocache.writebacks::total 36206
+system.iocache.ReadReq_mshr_misses::realview.ide 252
+system.iocache.ReadReq_mshr_misses::total 252
+system.iocache.WriteLineReq_mshr_misses::realview.ide 36224
+system.iocache.WriteLineReq_mshr_misses::total 36224
+system.iocache.demand_mshr_misses::realview.ide 36476
+system.iocache.demand_mshr_misses::total 36476
+system.iocache.overall_mshr_misses::realview.ide 36476
+system.iocache.overall_mshr_misses::total 36476
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 28048874
+system.iocache.ReadReq_mshr_miss_latency::total 28048874
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2549492754
+system.iocache.WriteLineReq_mshr_miss_latency::total 2549492754
+system.iocache.demand_mshr_miss_latency::realview.ide 2577541628
+system.iocache.demand_mshr_miss_latency::total 2577541628
+system.iocache.overall_mshr_miss_latency::realview.ide 2577541628
+system.iocache.overall_mshr_miss_latency::total 2577541628
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1
+system.iocache.ReadReq_mshr_miss_rate::total 1
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1
+system.iocache.WriteLineReq_mshr_miss_rate::total 1
+system.iocache.demand_mshr_miss_rate::realview.ide 1
+system.iocache.demand_mshr_miss_rate::total 1
+system.iocache.overall_mshr_miss_rate::realview.ide 1
+system.iocache.overall_mshr_miss_rate::total 1
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 111305.055556
+system.iocache.ReadReq_avg_mshr_miss_latency::total 111305.055556
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70381.314985
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70381.314985
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 70664.042878
+system.iocache.demand_avg_mshr_miss_latency::total 70664.042878
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 70664.042878
+system.iocache.overall_avg_mshr_miss_latency::total 70664.042878
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.l2c.tags.replacements 137538
+system.l2c.tags.tagsinuse 65136.999130
+system.l2c.tags.total_refs 548925
+system.l2c.tags.sampled_refs 202900
+system.l2c.tags.avg_refs 2.705397
+system.l2c.tags.warmup_cycle 87493786000
+system.l2c.tags.occ_blocks::writebacks 6083.094510
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.667582
+system.l2c.tags.occ_blocks::cpu0.itb.walker 1.052619
+system.l2c.tags.occ_blocks::cpu0.inst 7995.097461
+system.l2c.tags.occ_blocks::cpu0.data 6937.717156
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37101.162088
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 3.694761
+system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909744
+system.l2c.tags.occ_blocks::cpu1.inst 1893.535399
+system.l2c.tags.occ_blocks::cpu1.data 3108.654399
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1995.413410
+system.l2c.tags.occ_percent::writebacks 0.092821
+system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000254
+system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016
+system.l2c.tags.occ_percent::cpu0.inst 0.121996
+system.l2c.tags.occ_percent::cpu0.data 0.105861
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.566119
+system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000056
+system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014
+system.l2c.tags.occ_percent::cpu1.inst 0.028893
+system.l2c.tags.occ_percent::cpu1.data 0.047434
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030448
+system.l2c.tags.occ_percent::total 0.993912
+system.l2c.tags.occ_task_id_blocks::1022 33234
+system.l2c.tags.occ_task_id_blocks::1023 23
+system.l2c.tags.occ_task_id_blocks::1024 32105
+system.l2c.tags.age_task_id_blocks_1022::2 194
+system.l2c.tags.age_task_id_blocks_1022::3 6030
+system.l2c.tags.age_task_id_blocks_1022::4 27010
+system.l2c.tags.age_task_id_blocks_1023::4 23
+system.l2c.tags.age_task_id_blocks_1024::0 1
+system.l2c.tags.age_task_id_blocks_1024::1 1
+system.l2c.tags.age_task_id_blocks_1024::2 141
+system.l2c.tags.age_task_id_blocks_1024::3 4855
+system.l2c.tags.age_task_id_blocks_1024::4 27107
+system.l2c.tags.occ_task_id_percent::1022 0.507111
+system.l2c.tags.occ_task_id_percent::1023 0.000351
+system.l2c.tags.occ_task_id_percent::1024 0.489883
+system.l2c.tags.tag_accesses 6299006
+system.l2c.tags.data_accesses 6299006
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.l2c.WritebackDirty_hits::writebacks 261357
+system.l2c.WritebackDirty_hits::total 261357
+system.l2c.UpgradeReq_hits::cpu0.data 41476
+system.l2c.UpgradeReq_hits::cpu1.data 4855
+system.l2c.UpgradeReq_hits::total 46331
+system.l2c.SCUpgradeReq_hits::cpu0.data 2730
+system.l2c.SCUpgradeReq_hits::cpu1.data 2235
+system.l2c.SCUpgradeReq_hits::total 4965
+system.l2c.ReadExReq_hits::cpu0.data 4014
+system.l2c.ReadExReq_hits::cpu1.data 1526
+system.l2c.ReadExReq_hits::total 5540
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 219
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker 82
+system.l2c.ReadSharedReq_hits::cpu0.inst 50682
+system.l2c.ReadSharedReq_hits::cpu0.data 57324
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46514
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 48
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker 28
+system.l2c.ReadSharedReq_hits::cpu1.inst 21494
+system.l2c.ReadSharedReq_hits::cpu1.data 11668
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4890
+system.l2c.ReadSharedReq_hits::total 192949
+system.l2c.demand_hits::cpu0.dtb.walker 219
+system.l2c.demand_hits::cpu0.itb.walker 82
+system.l2c.demand_hits::cpu0.inst 50682
+system.l2c.demand_hits::cpu0.data 61338
+system.l2c.demand_hits::cpu0.l2cache.prefetcher 46514
+system.l2c.demand_hits::cpu1.dtb.walker 48
+system.l2c.demand_hits::cpu1.itb.walker 28
+system.l2c.demand_hits::cpu1.inst 21494
+system.l2c.demand_hits::cpu1.data 13194
+system.l2c.demand_hits::cpu1.l2cache.prefetcher 4890
+system.l2c.demand_hits::total 198489
+system.l2c.overall_hits::cpu0.dtb.walker 219
+system.l2c.overall_hits::cpu0.itb.walker 82
+system.l2c.overall_hits::cpu0.inst 50682
+system.l2c.overall_hits::cpu0.data 61338
+system.l2c.overall_hits::cpu0.l2cache.prefetcher 46514
+system.l2c.overall_hits::cpu1.dtb.walker 48
+system.l2c.overall_hits::cpu1.itb.walker 28
+system.l2c.overall_hits::cpu1.inst 21494
+system.l2c.overall_hits::cpu1.data 13194
+system.l2c.overall_hits::cpu1.l2cache.prefetcher 4890
+system.l2c.overall_hits::total 198489
+system.l2c.UpgradeReq_misses::cpu0.data 444
+system.l2c.UpgradeReq_misses::cpu1.data 302
+system.l2c.UpgradeReq_misses::total 746
+system.l2c.SCUpgradeReq_misses::cpu0.data 107
+system.l2c.SCUpgradeReq_misses::cpu1.data 90
+system.l2c.SCUpgradeReq_misses::total 197
+system.l2c.ReadExReq_misses::cpu0.data 11226
+system.l2c.ReadExReq_misses::cpu1.data 8277
+system.l2c.ReadExReq_misses::total 19503
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 30
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3
+system.l2c.ReadSharedReq_misses::cpu0.inst 19709
+system.l2c.ReadSharedReq_misses::cpu0.data 9355
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131267
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 5
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1
+system.l2c.ReadSharedReq_misses::cpu1.inst 3018
+system.l2c.ReadSharedReq_misses::cpu1.data 1020
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6750
+system.l2c.ReadSharedReq_misses::total 171158
+system.l2c.demand_misses::cpu0.dtb.walker 30
+system.l2c.demand_misses::cpu0.itb.walker 3
+system.l2c.demand_misses::cpu0.inst 19709
+system.l2c.demand_misses::cpu0.data 20581
+system.l2c.demand_misses::cpu0.l2cache.prefetcher 131267
+system.l2c.demand_misses::cpu1.dtb.walker 5
+system.l2c.demand_misses::cpu1.itb.walker 1
+system.l2c.demand_misses::cpu1.inst 3018
+system.l2c.demand_misses::cpu1.data 9297
+system.l2c.demand_misses::cpu1.l2cache.prefetcher 6750
+system.l2c.demand_misses::total 190661
+system.l2c.overall_misses::cpu0.dtb.walker 30
+system.l2c.overall_misses::cpu0.itb.walker 3
+system.l2c.overall_misses::cpu0.inst 19709
+system.l2c.overall_misses::cpu0.data 20581
+system.l2c.overall_misses::cpu0.l2cache.prefetcher 131267
+system.l2c.overall_misses::cpu1.dtb.walker 5
+system.l2c.overall_misses::cpu1.itb.walker 1
+system.l2c.overall_misses::cpu1.inst 3018
+system.l2c.overall_misses::cpu1.data 9297
+system.l2c.overall_misses::cpu1.l2cache.prefetcher 6750
+system.l2c.overall_misses::total 190661
+system.l2c.UpgradeReq_miss_latency::cpu0.data 9143000
+system.l2c.UpgradeReq_miss_latency::cpu1.data 720000
+system.l2c.UpgradeReq_miss_latency::total 9863000
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data 470000
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data 388000
+system.l2c.SCUpgradeReq_miss_latency::total 858000
+system.l2c.ReadExReq_miss_latency::cpu0.data 1641427500
+system.l2c.ReadExReq_miss_latency::cpu1.data 783374000
+system.l2c.ReadExReq_miss_latency::total 2424801500
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 4633500
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 249000
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2045758000
+system.l2c.ReadSharedReq_miss_latency::cpu0.data 1085501500
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16518080144
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 445500
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 89500
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst 342873500
+system.l2c.ReadSharedReq_miss_latency::cpu1.data 117342000
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 976431795
+system.l2c.ReadSharedReq_miss_latency::total 21091404439
+system.l2c.demand_miss_latency::cpu0.dtb.walker 4633500
+system.l2c.demand_miss_latency::cpu0.itb.walker 249000
+system.l2c.demand_miss_latency::cpu0.inst 2045758000
+system.l2c.demand_miss_latency::cpu0.data 2726929000
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16518080144
+system.l2c.demand_miss_latency::cpu1.dtb.walker 445500
+system.l2c.demand_miss_latency::cpu1.itb.walker 89500
+system.l2c.demand_miss_latency::cpu1.inst 342873500
+system.l2c.demand_miss_latency::cpu1.data 900716000
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 976431795
+system.l2c.demand_miss_latency::total 23516205939
+system.l2c.overall_miss_latency::cpu0.dtb.walker 4633500
+system.l2c.overall_miss_latency::cpu0.itb.walker 249000
+system.l2c.overall_miss_latency::cpu0.inst 2045758000
+system.l2c.overall_miss_latency::cpu0.data 2726929000
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16518080144
+system.l2c.overall_miss_latency::cpu1.dtb.walker 445500
+system.l2c.overall_miss_latency::cpu1.itb.walker 89500
+system.l2c.overall_miss_latency::cpu1.inst 342873500
+system.l2c.overall_miss_latency::cpu1.data 900716000
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 976431795
+system.l2c.overall_miss_latency::total 23516205939
+system.l2c.WritebackDirty_accesses::writebacks 261357
+system.l2c.WritebackDirty_accesses::total 261357
+system.l2c.UpgradeReq_accesses::cpu0.data 41920
+system.l2c.UpgradeReq_accesses::cpu1.data 5157
+system.l2c.UpgradeReq_accesses::total 47077
+system.l2c.SCUpgradeReq_accesses::cpu0.data 2837
+system.l2c.SCUpgradeReq_accesses::cpu1.data 2325
+system.l2c.SCUpgradeReq_accesses::total 5162
+system.l2c.ReadExReq_accesses::cpu0.data 15240
+system.l2c.ReadExReq_accesses::cpu1.data 9803
+system.l2c.ReadExReq_accesses::total 25043
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 249
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 85
+system.l2c.ReadSharedReq_accesses::cpu0.inst 70391
+system.l2c.ReadSharedReq_accesses::cpu0.data 66679
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177781
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 53
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 29
+system.l2c.ReadSharedReq_accesses::cpu1.inst 24512
+system.l2c.ReadSharedReq_accesses::cpu1.data 12688
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11640
+system.l2c.ReadSharedReq_accesses::total 364107
+system.l2c.demand_accesses::cpu0.dtb.walker 249
+system.l2c.demand_accesses::cpu0.itb.walker 85
+system.l2c.demand_accesses::cpu0.inst 70391
+system.l2c.demand_accesses::cpu0.data 81919
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177781
+system.l2c.demand_accesses::cpu1.dtb.walker 53
+system.l2c.demand_accesses::cpu1.itb.walker 29
+system.l2c.demand_accesses::cpu1.inst 24512
+system.l2c.demand_accesses::cpu1.data 22491
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11640
+system.l2c.demand_accesses::total 389150
+system.l2c.overall_accesses::cpu0.dtb.walker 249
+system.l2c.overall_accesses::cpu0.itb.walker 85
+system.l2c.overall_accesses::cpu0.inst 70391
+system.l2c.overall_accesses::cpu0.data 81919
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177781
+system.l2c.overall_accesses::cpu1.dtb.walker 53
+system.l2c.overall_accesses::cpu1.itb.walker 29
+system.l2c.overall_accesses::cpu1.inst 24512
+system.l2c.overall_accesses::cpu1.data 22491
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11640
+system.l2c.overall_accesses::total 389150
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.010592
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.058561
+system.l2c.UpgradeReq_miss_rate::total 0.015846
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.037716
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.038710
+system.l2c.SCUpgradeReq_miss_rate::total 0.038164
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.736614
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.844333
+system.l2c.ReadExReq_miss_rate::total 0.778780
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.120482
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.035294
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.279993
+system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.140299
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738363
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.094340
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.034483
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.123123
+system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.080391
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.579897
+system.l2c.ReadSharedReq_miss_rate::total 0.470076
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.120482
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.035294
+system.l2c.demand_miss_rate::cpu0.inst 0.279993
+system.l2c.demand_miss_rate::cpu0.data 0.251236
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738363
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.094340
+system.l2c.demand_miss_rate::cpu1.itb.walker 0.034483
+system.l2c.demand_miss_rate::cpu1.inst 0.123123
+system.l2c.demand_miss_rate::cpu1.data 0.413365
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.579897
+system.l2c.demand_miss_rate::total 0.489942
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.120482
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.035294
+system.l2c.overall_miss_rate::cpu0.inst 0.279993
+system.l2c.overall_miss_rate::cpu0.data 0.251236
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738363
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.094340
+system.l2c.overall_miss_rate::cpu1.itb.walker 0.034483
+system.l2c.overall_miss_rate::cpu1.inst 0.123123
+system.l2c.overall_miss_rate::cpu1.data 0.413365
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.579897
+system.l2c.overall_miss_rate::total 0.489942
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 20592.342342
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2384.105960
+system.l2c.UpgradeReq_avg_miss_latency::total 13221.179625
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4392.523364
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4311.111111
+system.l2c.SCUpgradeReq_avg_miss_latency::total 4355.329949
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 146216.595404
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 94644.678023
+system.l2c.ReadExReq_avg_miss_latency::total 124329.667231
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 154450
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 83000
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 103798.163276
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 116034.366649
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 125835.740468
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89100
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89500
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 113609.509609
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115041.176471
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 144656.562222
+system.l2c.ReadSharedReq_avg_miss_latency::total 123227.686927
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 154450
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000
+system.l2c.demand_avg_miss_latency::cpu0.inst 103798.163276
+system.l2c.demand_avg_miss_latency::cpu0.data 132497.400515
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 125835.740468
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89100
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89500
+system.l2c.demand_avg_miss_latency::cpu1.inst 113609.509609
+system.l2c.demand_avg_miss_latency::cpu1.data 96882.435194
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 144656.562222
+system.l2c.demand_avg_miss_latency::total 123340.410147
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 154450
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000
+system.l2c.overall_avg_miss_latency::cpu0.inst 103798.163276
+system.l2c.overall_avg_miss_latency::cpu0.data 132497.400515
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 125835.740468
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89100
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89500
+system.l2c.overall_avg_miss_latency::cpu1.inst 113609.509609
+system.l2c.overall_avg_miss_latency::cpu1.data 96882.435194
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 144656.562222
+system.l2c.overall_avg_miss_latency::total 123340.410147
+system.l2c.blocked_cycles::no_mshrs 0
+system.l2c.blocked_cycles::no_targets 0
+system.l2c.blocked::no_mshrs 0
+system.l2c.blocked::no_targets 0
+system.l2c.avg_blocked_cycles::no_mshrs nan
+system.l2c.avg_blocked_cycles::no_targets nan
+system.l2c.writebacks::writebacks 101163
+system.l2c.writebacks::total 101163
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 7
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 3
+system.l2c.ReadSharedReq_mshr_hits::total 10
+system.l2c.demand_mshr_hits::cpu0.inst 7
+system.l2c.demand_mshr_hits::cpu1.inst 3
+system.l2c.demand_mshr_hits::total 10
+system.l2c.overall_mshr_hits::cpu0.inst 7
+system.l2c.overall_mshr_hits::cpu1.inst 3
+system.l2c.overall_mshr_hits::total 10
+system.l2c.CleanEvict_mshr_misses::writebacks 4224
+system.l2c.CleanEvict_mshr_misses::total 4224
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 444
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 302
+system.l2c.UpgradeReq_mshr_misses::total 746
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 107
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 90
+system.l2c.SCUpgradeReq_mshr_misses::total 197
+system.l2c.ReadExReq_mshr_misses::cpu0.data 11226
+system.l2c.ReadExReq_mshr_misses::cpu1.data 8277
+system.l2c.ReadExReq_mshr_misses::total 19503
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 30
+system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19702
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9355
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 131267
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 5
+system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3015
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1020
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6750
+system.l2c.ReadSharedReq_mshr_misses::total 171148
+system.l2c.demand_mshr_misses::cpu0.dtb.walker 30
+system.l2c.demand_mshr_misses::cpu0.itb.walker 3
+system.l2c.demand_mshr_misses::cpu0.inst 19702
+system.l2c.demand_mshr_misses::cpu0.data 20581
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 131267
+system.l2c.demand_mshr_misses::cpu1.dtb.walker 5
+system.l2c.demand_mshr_misses::cpu1.itb.walker 1
+system.l2c.demand_mshr_misses::cpu1.inst 3015
+system.l2c.demand_mshr_misses::cpu1.data 9297
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6750
+system.l2c.demand_mshr_misses::total 190651
+system.l2c.overall_mshr_misses::cpu0.dtb.walker 30
+system.l2c.overall_mshr_misses::cpu0.itb.walker 3
+system.l2c.overall_mshr_misses::cpu0.inst 19702
+system.l2c.overall_mshr_misses::cpu0.data 20581
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 131267
+system.l2c.overall_mshr_misses::cpu1.dtb.walker 5
+system.l2c.overall_mshr_misses::cpu1.itb.walker 1
+system.l2c.overall_mshr_misses::cpu1.inst 3015
+system.l2c.overall_mshr_misses::cpu1.data 9297
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6750
+system.l2c.overall_mshr_misses::total 190651
+system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3008
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20557
+system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 101
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14311
+system.l2c.ReadReq_mshr_uncacheable::total 37977
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19259
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11649
+system.l2c.WriteReq_mshr_uncacheable::total 30908
+system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3008
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39816
+system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 101
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data 25960
+system.l2c.overall_mshr_uncacheable_misses::total 68885
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 10048500
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 7134500
+system.l2c.UpgradeReq_mshr_miss_latency::total 17183000
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2805000
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1985000
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 4790000
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1529167001
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 700604000
+system.l2c.ReadExReq_mshr_miss_latency::total 2229771001
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 4333500
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 219000
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1848274000
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 991951001
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15205404156
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 395500
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 79500
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 312624501
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 107142000
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 908931296
+system.l2c.ReadSharedReq_mshr_miss_latency::total 19379354454
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 4333500
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 219000
+system.l2c.demand_mshr_miss_latency::cpu0.inst 1848274000
+system.l2c.demand_mshr_miss_latency::cpu0.data 2521118002
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 15205404156
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 395500
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 79500
+system.l2c.demand_mshr_miss_latency::cpu1.inst 312624501
+system.l2c.demand_mshr_miss_latency::cpu1.data 807746000
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 908931296
+system.l2c.demand_mshr_miss_latency::total 21609125455
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 4333500
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 219000
+system.l2c.overall_mshr_miss_latency::cpu0.inst 1848274000
+system.l2c.overall_mshr_miss_latency::cpu0.data 2521118002
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15205404156
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 395500
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 79500
+system.l2c.overall_mshr_miss_latency::cpu1.inst 312624501
+system.l2c.overall_mshr_miss_latency::cpu1.data 807746000
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 908931296
+system.l2c.overall_mshr_miss_latency::total 21609125455
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 210941500
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4057565000
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6923000
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2100454500
+system.l2c.ReadReq_mshr_uncacheable_latency::total 6375884000
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 210941500
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4057565000
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6923000
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2100454500
+system.l2c.overall_mshr_uncacheable_latency::total 6375884000
+system.l2c.CleanEvict_mshr_miss_rate::writebacks inf
+system.l2c.CleanEvict_mshr_miss_rate::total inf
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.010592
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.058561
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.015846
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.037716
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.038710
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.038164
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.736614
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.844333
+system.l2c.ReadExReq_mshr_miss_rate::total 0.778780
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.120482
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.035294
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.279894
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.140299
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738363
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.094340
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.034483
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.123001
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.080391
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.579897
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.470049
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.120482
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.035294
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.279894
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.251236
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738363
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.094340
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.034483
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.123001
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.413365
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.579897
+system.l2c.demand_mshr_miss_rate::total 0.489916
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.120482
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.035294
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.279894
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.251236
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738363
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.094340
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.034483
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.123001
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.413365
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.579897
+system.l2c.overall_mshr_miss_rate::total 0.489916
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22631.756757
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23624.172185
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23033.512064
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26214.953271
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 22055.555556
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24314.720812
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 136216.550953
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84644.678023
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 114329.641645
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 144450
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 73000
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 93811.491219
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 106034.313308
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115835.694851
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79100
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79500
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 103689.718408
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105041.176471
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134656.488296
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113231.556629
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 144450
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73000
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 93811.491219
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 122497.352024
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115835.694851
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79100
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79500
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 103689.718408
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86882.435194
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134656.488296
+system.l2c.demand_avg_mshr_miss_latency::total 113343.887286
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 144450
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 93811.491219
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 122497.352024
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115835.694851
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79100
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79500
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 103689.718408
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86882.435194
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134656.488296
+system.l2c.overall_avg_mshr_miss_latency::total 113343.887286
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197381.184025
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 68544.554455
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146772.028510
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167888.037496
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101907.901346
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 68544.554455
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80911.190293
+system.l2c.overall_avg_mshr_uncacheable_latency::total 92558.379909
+system.membus.snoop_filter.tot_requests 505159
+system.membus.snoop_filter.hit_single_requests 284291
+system.membus.snoop_filter.hit_multi_requests 621
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.membus.trans_dist::ReadReq 37977
+system.membus.trans_dist::ReadResp 209376
+system.membus.trans_dist::WriteReq 30908
+system.membus.trans_dist::WriteResp 30908
+system.membus.trans_dist::WritebackDirty 137369
+system.membus.trans_dist::CleanEvict 16867
+system.membus.trans_dist::UpgradeReq 65189
+system.membus.trans_dist::SCUpgradeReq 38920
+system.membus.trans_dist::UpgradeResp 2
+system.membus.trans_dist::SCUpgradeFailReq 2
+system.membus.trans_dist::ReadExReq 39113
+system.membus.trans_dist::ReadExResp 19490
+system.membus.trans_dist::ReadSharedReq 171400
+system.membus.trans_dist::InvalidateReq 36224
+system.membus.trans_dist::InvalidateResp 4602
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107894
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13718
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638576
+system.membus.pkt_count_system.l2c.mem_side::total 760224
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949
+system.membus.pkt_count_system.iocache.mem_side::total 72949
+system.membus.pkt_count::total 833173
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162784
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27436
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18723336
+system.membus.pkt_size_system.l2c.mem_side::total 18913844
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144
+system.membus.pkt_size_system.iocache.mem_side::total 2318144
+system.membus.pkt_size::total 21231988
+system.membus.snoops 127952
+system.membus.snoopTraffic 36480
+system.membus.snoop_fanout::samples 419736
+system.membus.snoop_fanout::mean 0.012448
+system.membus.snoop_fanout::stdev 0.110875
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 414511 98.76% 98.76%
+system.membus.snoop_fanout::1 5225 1.24% 100.00%
+system.membus.snoop_fanout::2 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 1
+system.membus.snoop_fanout::total 419736
+system.membus.reqLayer0.occupancy 81591999
+system.membus.reqLayer0.utilization 0.0
+system.membus.reqLayer1.occupancy 24500
+system.membus.reqLayer1.utilization 0.0
+system.membus.reqLayer2.occupancy 11409500
+system.membus.reqLayer2.utilization 0.0
+system.membus.reqLayer5.occupancy 986227988
+system.membus.reqLayer5.utilization 0.0
+system.membus.respLayer2.occupancy 1099986359
+system.membus.respLayer2.utilization 0.0
+system.membus.respLayer3.occupancy 7210414
+system.membus.respLayer3.utilization 0.0
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.dcc.osc_cpu.clock 16667
+system.realview.dcc.osc_ddr.clock 25000
+system.realview.dcc.osc_hsbm.clock 25000
+system.realview.dcc.osc_pxl.clock 42105
+system.realview.dcc.osc_smb.clock 20000
+system.realview.dcc.osc_sys.clock 16667
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.ethernet.descDMAReads 0
+system.realview.ethernet.descDMAWrites 0
+system.realview.ethernet.descDmaReadBytes 0
+system.realview.ethernet.descDmaWriteBytes 0
+system.realview.ethernet.postedSwi 0
+system.realview.ethernet.coalescedSwi nan
+system.realview.ethernet.totalSwi 0
+system.realview.ethernet.postedRxIdle 0
+system.realview.ethernet.coalescedRxIdle nan
+system.realview.ethernet.totalRxIdle 0
+system.realview.ethernet.postedRxOk 0
+system.realview.ethernet.coalescedRxOk nan
+system.realview.ethernet.totalRxOk 0
+system.realview.ethernet.postedRxDesc 0
+system.realview.ethernet.coalescedRxDesc nan
+system.realview.ethernet.totalRxDesc 0
+system.realview.ethernet.postedTxOk 0
+system.realview.ethernet.coalescedTxOk nan
+system.realview.ethernet.totalTxOk 0
+system.realview.ethernet.postedTxIdle 0
+system.realview.ethernet.coalescedTxIdle nan
+system.realview.ethernet.totalTxIdle 0
+system.realview.ethernet.postedTxDesc 0
+system.realview.ethernet.coalescedTxDesc nan
+system.realview.ethernet.totalTxDesc 0
+system.realview.ethernet.postedRxOrn 0
+system.realview.ethernet.coalescedRxOrn nan
+system.realview.ethernet.totalRxOrn 0
+system.realview.ethernet.coalescedTotal nan
+system.realview.ethernet.postedInterrupts 0
+system.realview.ethernet.droppedPackets 0
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.mcc.osc_clcd.clock 42105
+system.realview.mcc.osc_mcc.clock 20000
+system.realview.mcc.osc_peripheral.clock 41667
+system.realview.mcc.osc_system_bus.clock 41667
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.toL2Bus.snoop_filter.tot_requests 1046819
+system.toL2Bus.snoop_filter.hit_single_requests 541974
+system.toL2Bus.snoop_filter.hit_multi_requests 201183
+system.toL2Bus.snoop_filter.tot_snoops 29464
+system.toL2Bus.snoop_filter.hit_single_snoops 28225
+system.toL2Bus.snoop_filter.hit_multi_snoops 1239
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826661822500
+system.toL2Bus.trans_dist::ReadReq 37980
+system.toL2Bus.trans_dist::ReadResp 523576
+system.toL2Bus.trans_dist::WriteReq 30908
+system.toL2Bus.trans_dist::WriteResp 30908
+system.toL2Bus.trans_dist::WritebackDirty 362520
+system.toL2Bus.trans_dist::CleanEvict 130460
+system.toL2Bus.trans_dist::UpgradeReq 111507
+system.toL2Bus.trans_dist::SCUpgradeReq 43885
+system.toL2Bus.trans_dist::UpgradeResp 155392
+system.toL2Bus.trans_dist::SCUpgradeFailReq 23
+system.toL2Bus.trans_dist::UpgradeFailResp 23
+system.toL2Bus.trans_dist::ReadExReq 50602
+system.toL2Bus.trans_dist::ReadExResp 50602
+system.toL2Bus.trans_dist::ReadSharedReq 485601
+system.toL2Bus.trans_dist::InvalidateReq 4649
+system.toL2Bus.trans_dist::InvalidateResp 3450
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1262886
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 366763
+system.toL2Bus.pkt_count::total 1629649
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36014414
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5893094
+system.toL2Bus.pkt_size::total 41907508
+system.toL2Bus.snoops 396124
+system.toL2Bus.snoopTraffic 15887052
+system.toL2Bus.snoop_fanout::samples 902717
+system.toL2Bus.snoop_fanout::mean 0.407309
+system.toL2Bus.snoop_fanout::stdev 0.494119
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.toL2Bus.snoop_fanout::0 536271 59.41% 59.41%
+system.toL2Bus.snoop_fanout::1 365207 40.46% 99.86%
+system.toL2Bus.snoop_fanout::2 1239 0.14% 100.00%
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.toL2Bus.snoop_fanout::min_value 0
+system.toL2Bus.snoop_fanout::max_value 2
+system.toL2Bus.snoop_fanout::total 902717
+system.toL2Bus.reqLayer0.occupancy 897869135
+system.toL2Bus.reqLayer0.utilization 0.0
+system.toL2Bus.snoopLayer0.occupancy 2163785
+system.toL2Bus.snoopLayer0.utilization 0.0
+system.toL2Bus.respLayer0.occupancy 676148084
+system.toL2Bus.respLayer0.utilization 0.0
+system.toL2Bus.respLayer1.occupancy 261623426
+system.toL2Bus.respLayer1.utilization 0.0
+system.cpu0.kern.inst.arm 0
+system.cpu0.kern.inst.quiesce 1835
+system.cpu1.kern.inst.arm 0
+system.cpu1.kern.inst.quiesce 2780
---------- End Simulation Statistics ----------
ata1.00: configured for UDMA/33\r
scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)\r
-sd 0:0:0:0: [sda] Write Protect is off\r
sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+sd 0:0:0:0: [sda] Write Protect is off\r
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
sda: sda1\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
+boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_panic=true
phys_addr_range_64=40
power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
+readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
+image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
activity=0
backComSize=5
branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
sequential_access=false
size=32768
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
[system.cpu.fuPool.FUList2]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
-[system.cpu.fuPool.FUList2.opList]
+[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
-[system.cpu.fuPool.FUList3.opList]
+[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
-opLat=1
+opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
opLat=4
pipelined=true
+[system.cpu.fuPool.FUList4.opList26]
+type=OpDesc
+eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList4.opList27]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
[system.cpu.icache]
type=Cache
children=tags
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
sequential_access=false
size=32768
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
sequential_access=false
size=4194304
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=4194304
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
+data_latency=50
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=50
is_read_only=false
max_miss_count=0
mshrs=20
sequential_access=false
size=1024
system=system
+tag_latency=50
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
assoc=8
block_size=64
clk_domain=system.clk_domain
+data_latency=50
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=50
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1024
+tag_latency=50
[system.membus]
type=CoherentXBar
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+info: Entering event queue @ 0. Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
warn: Ignoring write to miscreg pmintenclr
warn: Ignoring write to miscreg pmovsr
warn: Ignoring write to miscreg pmcr
+warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5]
warn: instruction 'mcr dcisw' unimplemented
warn: instruction 'mcr bpiall' unimplemented
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:43:01
-gem5 executing on e108600-lin, pid 17340
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3
+gem5 compiled Mar 29 2017 19:38:26
+gem5 started Mar 29 2017 19:38:42
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83598
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2829112944500 because m5_exit instruction encountered
+Exiting @ tick 2829109393000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.829112 # Number of seconds simulated
-sim_ticks 2829111899000 # Number of ticks simulated
-final_tick 2829111899000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 175088 # Simulator instruction rate (inst/s)
-host_op_rate 212371 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4377954653 # Simulator tick rate (ticks/s)
-host_mem_usage 587752 # Number of bytes of host memory used
-host_seconds 646.22 # Real time elapsed on the host
-sim_insts 113144906 # Number of instructions simulated
-sim_ops 137237936 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker 960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1316192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9473064 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10791560 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1316192 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1316192 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8091072 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8108596 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 22817 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 148537 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 171390 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 126423 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 130804 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 339 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 465232 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3348423 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3814469 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 465232 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 465232 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2859934 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 6194 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2866128 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2859934 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 339 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 465232 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3354617 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6680597 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 171391 # Number of read requests accepted
-system.physmem.writeReqs 130804 # Number of write requests accepted
-system.physmem.readBursts 171391 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 130804 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10959616 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8121152 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10791624 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8108596 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 10684 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10046 # Per bank write bursts
-system.physmem.perBankRdBursts::2 10837 # Per bank write bursts
-system.physmem.perBankRdBursts::3 10895 # Per bank write bursts
-system.physmem.perBankRdBursts::4 13724 # Per bank write bursts
-system.physmem.perBankRdBursts::5 10674 # Per bank write bursts
-system.physmem.perBankRdBursts::6 11441 # Per bank write bursts
-system.physmem.perBankRdBursts::7 11403 # Per bank write bursts
-system.physmem.perBankRdBursts::8 10108 # Per bank write bursts
-system.physmem.perBankRdBursts::9 10400 # Per bank write bursts
-system.physmem.perBankRdBursts::10 10362 # Per bank write bursts
-system.physmem.perBankRdBursts::11 9483 # Per bank write bursts
-system.physmem.perBankRdBursts::12 10233 # Per bank write bursts
-system.physmem.perBankRdBursts::13 11051 # Per bank write bursts
-system.physmem.perBankRdBursts::14 10017 # Per bank write bursts
-system.physmem.perBankRdBursts::15 9886 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8065 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7694 # Per bank write bursts
-system.physmem.perBankWrBursts::2 8363 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8151 # Per bank write bursts
-system.physmem.perBankWrBursts::4 8125 # Per bank write bursts
-system.physmem.perBankWrBursts::5 8034 # Per bank write bursts
-system.physmem.perBankWrBursts::6 8547 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8477 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7686 # Per bank write bursts
-system.physmem.perBankWrBursts::9 7978 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7776 # Per bank write bursts
-system.physmem.perBankWrBursts::11 7088 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7779 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8428 # Per bank write bursts
-system.physmem.perBankWrBursts::14 7464 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7238 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 67 # Number of times write queue was full causing retry
-system.physmem.totGap 2829111664000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 542 # Read request sizes (log2)
-system.physmem.readPktSize::3 14 # Read request sizes (log2)
-system.physmem.readPktSize::4 3002 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 167833 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 4381 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 126423 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 150076 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 14975 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5318 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 858 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1808 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2673 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5607 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5955 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6548 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6411 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6735 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 7002 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 7869 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 7630 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 8658 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 9211 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 7730 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 7272 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 7334 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 7222 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6702 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 6780 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 504 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 461 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 422 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 369 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 304 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 261 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 275 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 248 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 268 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 281 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 333 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 274 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 273 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 220 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 185 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 216 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 234 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 170 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 195 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 192 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 170 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 208 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 182 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 159 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 193 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 158 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 205 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 85 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 180 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 61280 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 311.370235 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 183.627944 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 329.836836 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22555 36.81% 36.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 14711 24.01% 60.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6399 10.44% 71.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3617 5.90% 77.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2643 4.31% 81.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1730 2.82% 84.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1046 1.71% 86.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1020 1.66% 87.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7559 12.34% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 61280 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6329 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 27.046295 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 535.582122 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6327 99.97% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6329 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6329 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.049455 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.259917 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 14.703816 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5592 88.36% 88.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 89 1.41% 89.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 39 0.62% 90.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 43 0.68% 91.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 270 4.27% 95.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 18 0.28% 95.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 20 0.32% 95.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 12 0.19% 96.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 11 0.17% 96.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 6 0.09% 96.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 2 0.03% 96.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 6 0.09% 96.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 144 2.28% 98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 4 0.06% 98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 7 0.11% 98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 1 0.02% 98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 4 0.06% 99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 2 0.03% 99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 2 0.03% 99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 2 0.03% 99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 2 0.03% 99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 8 0.13% 99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 4 0.06% 99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 1 0.02% 99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 1 0.02% 99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 15 0.24% 99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 4 0.06% 99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 2 0.03% 99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 2 0.03% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 2 0.03% 99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 2 0.03% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 1 0.02% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 1 0.02% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183 2 0.03% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187 1 0.02% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191 1 0.02% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 5 0.08% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6329 # Writes before turning the bus around for reads
-system.physmem.totQLat 4759784250 # Total ticks spent queuing
-system.physmem.totMemAccLat 7970609250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 856220000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 27795.17 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 46545.06 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 3.87 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.87 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.87 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.05 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 22.41 # Average write queue length when enqueuing
-system.physmem.readRowHits 141725 # Number of row buffer hits during reads
-system.physmem.writeRowHits 95132 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.76 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.96 # Row buffer hit rate for writes
-system.physmem.avgGap 9361874.50 # Average gap between requests
-system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 229315380 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 121884015 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 640486560 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 341680320 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 5265620880.000001 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 4324767840 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 323323200 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 10830363660 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 7337789280 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 667252731645 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 696670151130 # Total energy per rank (pJ)
-system.physmem_0.averagePower 246.250476 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 2818571248250 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 597049500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 2238844000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 2775921295250 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 19108902750 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 7495096250 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 23750711250 # Time in different power states
-system.physmem_1.actEnergy 208223820 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 110673585 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 582195600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 320701140 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 5120565840.000001 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 4126082940 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 330709920 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 10081531860 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 7328179680 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 667772142345 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 695983009200 # Total energy per rank (pJ)
-system.physmem_1.averagePower 246.007593 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 2819198005500 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 626918750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 2177664000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 2778005345250 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 19083791250 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 7109310750 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 22108869000 # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 46861889 # Number of BP lookups
-system.cpu.branchPred.condPredicted 23994211 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1178677 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 29377087 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 13527695 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 46.048456 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 11745847 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 34771 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 7932573 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 7787517 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 145056 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 60304 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 70988 # Table walker walks requested
-system.cpu.dtb.walker.walksShort 70988 # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1 28945 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23300 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore 18743 # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples 52245 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean 398.564456 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 2327.323415 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-4095 50380 96.43% 96.43% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::4096-8191 694 1.33% 97.76% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-12287 600 1.15% 98.91% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::12288-16383 333 0.64% 99.54% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-20479 70 0.13% 99.68% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::20480-24575 116 0.22% 99.90% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::24576-28671 29 0.06% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-36863 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::45056-49151 9 0.02% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 52245 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 16835 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 9419.156519 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 7648.743457 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 6474.178852 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-8191 8274 49.15% 49.15% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::8192-16383 6961 41.35% 90.50% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::16384-24575 1349 8.01% 98.51% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::24576-32767 164 0.97% 99.48% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-40959 19 0.11% 99.60% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::40960-49151 59 0.35% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::90112-98303 2 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::98304-106495 3 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::114688-122879 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 16835 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 118986443724 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean 0.628139 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev 0.489522 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1 118939907724 99.96% 99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3 32370000 0.03% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5 6888500 0.01% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7 4293000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9 974500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11 505000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13 1161500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15 334500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17 9000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 118986443724 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 6321 82.34% 82.34% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M 1356 17.66% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 7677 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 70988 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 70988 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7677 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7677 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 78665 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 25415823 # DTB read hits
-system.cpu.dtb.read_misses 61333 # DTB read misses
-system.cpu.dtb.write_hits 19865547 # DTB write hits
-system.cpu.dtb.write_misses 9655 # DTB write misses
-system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4258 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 385 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 2212 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1098 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 25477156 # DTB read accesses
-system.cpu.dtb.write_accesses 19875202 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 45281370 # DTB hits
-system.cpu.dtb.misses 70988 # DTB misses
-system.cpu.dtb.accesses 45352358 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 12746 # Table walker walks requested
-system.cpu.itb.walker.walksShort 12746 # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1 3372 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2 7811 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore 1563 # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples 11183 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean 675.266029 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev 2802.587445 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095 10603 94.81% 94.81% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::4096-8191 140 1.25% 96.07% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287 267 2.39% 98.45% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383 112 1.00% 99.45% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479 22 0.20% 99.65% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575 26 0.23% 99.88% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-28671 5 0.04% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::28672-32767 4 0.04% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::40960-45055 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 11183 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 4880 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 9080.327869 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 7055.685836 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 11146.166993 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535 4878 99.96% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 4880 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 24496220212 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean 0.683787 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev 0.465095 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 7747033500 31.63% 31.63% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1 16748218212 68.37% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2 952500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3 3000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4 3500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::5 3000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::6 6500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 24496220212 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 2980 89.84% 89.84% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M 337 10.16% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 3317 # Table walker page sizes translated
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12746 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 12746 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3317 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 3317 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 16063 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 66035618 # ITB inst hits
-system.cpu.itb.inst_misses 12746 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 3018 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2274 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 66048364 # ITB inst accesses
-system.cpu.itb.hits 66035618 # DTB hits
-system.cpu.itb.misses 12746 # DTB misses
-system.cpu.itb.accesses 66048364 # DTB accesses
-system.cpu.numPwrStateTransitions 6078 # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples 3039 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean 886809089.600197 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev 17417893131.253975 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows 2967 97.63% 97.63% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10 66 2.17% 99.80% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 499972215488 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total 3039 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON 134099075705 # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 2695012823295 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 268198207 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 105002772 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 184114970 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 46861889 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 33061059 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 151938402 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6072000 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 175966 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 7979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 334285 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 875612 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 143 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 66034467 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1042471 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6106 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 261371159 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.859042 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.228291 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 162416335 62.14% 62.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 29147387 11.15% 73.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 14040939 5.37% 78.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 55766498 21.34% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 261371159 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.174729 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.686488 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 78127678 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 112458141 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 64373777 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3837716 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2573847 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 10211840 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 470330 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 157024104 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3522922 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2573847 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 83881832 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 11236308 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 76411931 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 62459889 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 24807352 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 146462333 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 915339 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 473585 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 65974 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 19134 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 22055359 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 150259400 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 677124866 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 163984739 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 11050 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 141797655 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 8461739 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2842470 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2647297 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13853647 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 26344198 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 21214401 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1696128 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2146370 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 143256850 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2116673 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 143077391 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 262359 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 8135583 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14293372 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 121607 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 261371159 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.547411 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.874705 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 173167745 66.25% 66.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 45242575 17.31% 83.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 31871715 12.19% 95.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 10265143 3.93% 99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 823948 0.32% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 261371159 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 7332033 32.77% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 5621223 25.12% 57.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 9411536 42.06% 99.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 2405 0.01% 99.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 8745 0.04% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 95878441 67.01% 67.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 114347 0.08% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 8549 0.01% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 26131013 18.26% 85.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 20930310 14.63% 99.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 2708 0.00% 99.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 9686 0.01% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 143077391 # Type of FU issued
-system.cpu.iq.rate 0.533476 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 22375974 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.156391 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 570128328 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 153514376 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 140022897 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 35946 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 13304 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 11498 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 165427480 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 23548 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 325201 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1431545 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 741 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18622 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 620213 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 88247 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 6406 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2573847 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1145032 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 405376 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 145553638 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 26344198 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 21214401 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1093740 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 17692 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 369492 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18622 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 275358 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 475095 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 750453 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 142177506 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25738555 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 828985 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 180115 # number of nop insts executed
-system.cpu.iew.exec_refs 46565887 # number of memory reference insts executed
-system.cpu.iew.exec_branches 26507471 # Number of branches executed
-system.cpu.iew.exec_stores 20827332 # Number of stores executed
-system.cpu.iew.exec_rate 0.530121 # Inst execution rate
-system.cpu.iew.wb_sent 141808684 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 140034395 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 63259988 # num instructions producing a value
-system.cpu.iew.wb_consumers 95801132 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.522130 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.660326 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 7349911 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1995066 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 716524 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 258476519 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.531549 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.133767 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 185006238 71.58% 71.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 43313968 16.76% 88.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 15459084 5.98% 94.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 4363700 1.69% 96.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 6431569 2.49% 98.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1619656 0.63% 99.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 798464 0.31% 99.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 416455 0.16% 99.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1067385 0.41% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 258476519 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 113299811 # Number of instructions committed
-system.cpu.commit.committedOps 137392841 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 45506841 # Number of memory references committed
-system.cpu.commit.loads 24912653 # Number of loads committed
-system.cpu.commit.membars 814563 # Number of memory barriers committed
-system.cpu.commit.branches 26044441 # Number of branches committed
-system.cpu.commit.fp_insts 11492 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 120215331 # Number of committed integer instructions.
-system.cpu.commit.function_calls 4891729 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 91764545 66.79% 66.79% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 112906 0.08% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 8549 0.01% 66.88% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 24909945 18.13% 85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 20585408 14.98% 99.99% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 8780 0.01% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 137392841 # Class of committed instruction
-system.cpu.commit.bw_lim_events 1067385 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 379915503 # The number of ROB reads
-system.cpu.rob.rob_writes 292367166 # The number of ROB writes
-system.cpu.timesIdled 894415 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 6827048 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 5390025592 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 113144906 # Number of Instructions Simulated
-system.cpu.committedOps 137237936 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 2.370396 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.370396 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.421870 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.421870 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 155555257 # number of integer regfile reads
-system.cpu.int_regfile_writes 88513526 # number of integer regfile writes
-system.cpu.fp_regfile_reads 9686 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
-system.cpu.cc_regfile_reads 502284717 # number of cc regfile reads
-system.cpu.cc_regfile_writes 53144427 # number of cc regfile writes
-system.cpu.misc_regfile_reads 455456531 # number of misc regfile reads
-system.cpu.misc_regfile_writes 1521074 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 834899 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.950856 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 40072104 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 835411 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 47.966934 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 291735500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.950856 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999904 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999904 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 179153223 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 179153223 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 23270451 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23270451 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 15550335 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 15550335 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 346358 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 346358 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 441909 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 441909 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 460176 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 460176 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 38820786 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 38820786 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 39167144 # number of overall hits
-system.cpu.dcache.overall_hits::total 39167144 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 703305 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 703305 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3603558 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3603558 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 176816 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 176816 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 26536 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 26536 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 4306863 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4306863 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4483679 # number of overall misses
-system.cpu.dcache.overall_misses::total 4483679 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11004555500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11004555500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 167287466703 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 167287466703 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 367903000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 367903000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 196000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 196000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 178292022203 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 178292022203 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 178292022203 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 178292022203 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 23973756 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 23973756 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19153893 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 19153893 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 523174 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 523174 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468445 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 468445 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 460180 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 460180 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 43127649 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 43127649 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 43650823 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 43650823 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029336 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.029336 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188137 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.188137 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.337968 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.337968 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056647 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056647 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.099863 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.099863 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.102717 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.102717 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15646.917767 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15646.917767 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46422.859491 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 46422.859491 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13864.297558 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13864.297558 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 49000 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 49000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41397.189138 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41397.189138 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 39764.671423 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 39764.671423 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 631960 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 7043 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 89.728809 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 693774 # number of writebacks
-system.cpu.dcache.writebacks::total 693774 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291761 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 291761 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3304379 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3304379 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18239 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 18239 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3596140 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3596140 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3596140 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3596140 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 411544 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 411544 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299179 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 299179 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119204 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 119204 # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8297 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 8297 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 710723 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 710723 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 829927 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 829927 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6158767500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 6158767500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14913404483 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 14913404483 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1645609500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1645609500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 125434500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 125434500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 192000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 192000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21072171983 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 21072171983 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22717781483 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 22717781483 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6282018000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6282018000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6282018000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 6282018000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017166 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017166 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227848 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227848 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017712 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017712 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016480 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.016480 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019013 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.019013 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14965.028041 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14965.028041 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49847.764994 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49847.764994 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13804.985571 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13804.985571 # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15118.054719 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15118.054719 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 48000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 48000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29648.923678 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29648.923678 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27373.228589 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 27373.228589 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201818.935329 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201818.935329 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106998.995078 # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106998.995078 # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 1887711 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.315276 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 64050692 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1888223 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 33.921148 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 14108989500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.315276 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.998663 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.998663 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 67919712 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 67919712 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 64050692 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 64050692 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 64050692 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 64050692 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 64050692 # number of overall hits
-system.cpu.icache.overall_hits::total 64050692 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1980765 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1980765 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1980765 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1980765 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1980765 # number of overall misses
-system.cpu.icache.overall_misses::total 1980765 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 27590430995 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 27590430995 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 27590430995 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 27590430995 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 27590430995 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 27590430995 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 66031457 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 66031457 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 66031457 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 66031457 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 66031457 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 66031457 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029997 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.029997 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.029997 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.029997 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.029997 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.029997 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13929.179380 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13929.179380 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13929.179380 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13929.179380 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13929.179380 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13929.179380 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 2703 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 141 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 19.170213 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks 1887711 # number of writebacks
-system.cpu.icache.writebacks::total 1887711 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92509 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 92509 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 92509 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 92509 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 92509 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 92509 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1888256 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1888256 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1888256 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1888256 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1888256 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1888256 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3009 # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total 3009 # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3009 # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total 3009 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24716064497 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 24716064497 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24716064497 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 24716064497 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24716064497 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 24716064497 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 246809500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 246809500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 246809500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total 246809500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028596 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028596 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028596 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.028596 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028596 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.028596 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13089.361028 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13089.361028 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13089.361028 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13089.361028 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13089.361028 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13089.361028 # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82023.762047 # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82023.762047 # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82023.762047 # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82023.762047 # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 98094 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 65152.111665 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 5295433 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 163482 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 32.391535 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 91189489000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 7.957155 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 4.692905 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10411.783860 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 54727.677744 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000121 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000072 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158871 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.835078 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.994142 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 65376 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 313 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5395 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59668 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997559 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 43899166 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 43899166 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52220 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10081 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 62301 # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks 693774 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 693774 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 1849835 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 1849835 # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 2788 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 2788 # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 161417 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 161417 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1868356 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 1868356 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 525524 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 525524 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 52220 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 10081 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 1868356 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 686941 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2617598 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 52220 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 10081 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 1868356 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 686941 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2617598 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 15 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 21 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 135097 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 135097 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19843 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 19843 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13393 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 13393 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 15 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 19843 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 148490 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 168354 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 15 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 19843 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 148490 # number of overall misses
-system.cpu.l2cache.overall_misses::total 168354 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4534500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 2124500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 6659000 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 144500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 144500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 164000 # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total 164000 # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12738264500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 12738264500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2148357000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 2148357000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1551011500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 1551011500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4534500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 2124500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 2148357000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 14289276000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 16444292000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4534500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 2124500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 2148357000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 14289276000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 16444292000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52235 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10087 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 62322 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 693774 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 693774 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks 1849835 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 1849835 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2793 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 2793 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 296514 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 296514 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1888199 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 1888199 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 538917 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 538917 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52235 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 10087 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 1888199 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 835431 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2785952 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52235 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 10087 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1888199 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 835431 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2785952 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000287 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000595 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.000337 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.001790 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.001790 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455618 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.455618 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010509 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010509 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024852 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024852 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000287 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000595 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010509 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.177741 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.060430 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000287 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000595 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010509 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.177741 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.060430 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 302300 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 354083.333333 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 317095.238095 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 28900 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 28900 # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82000 # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82000 # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94289.765872 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94289.765872 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 108267.751852 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 108267.751852 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115807.623385 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115807.623385 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 302300 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 354083.333333 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 108267.751852 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96230.560981 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 97676.871354 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 302300 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 354083.333333 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 108267.751852 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96230.560981 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 97676.871354 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks 90233 # number of writebacks
-system.cpu.l2cache.writebacks::total 90233 # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 25 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total 25 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 113 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total 113 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 138 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 138 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 15 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 21 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135097 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 135097 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19818 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19818 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13280 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13280 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 15 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 19818 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 148377 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 168216 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 15 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 19818 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 148377 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 168216 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3009 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34136 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3009 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61720 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4384500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 2064500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6449000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 94500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 94500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 144000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 144000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11387294500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11387294500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1948311000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1948311000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1407408500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1407408500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4384500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 2064500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1948311000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12794703000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 14749463000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4384500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 2064500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1948311000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12794703000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 14749463000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209196500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5892920500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6102117000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209196500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5892920500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6102117000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000287 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000595 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000337 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.001790 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.001790 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455618 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455618 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010496 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010496 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024642 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024642 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000287 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000595 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010496 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177605 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.060380 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000287 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000595 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010496 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177605 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.060380 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 292300 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 344083.333333 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 307095.238095 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18900 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18900 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84289.765872 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84289.765872 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 98310.172570 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 98310.172570 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105979.555723 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105979.555723 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 292300 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 344083.333333 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 98310.172570 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86231.039851 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87681.689019 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 292300 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 344083.333333 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 98310.172570 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86231.039851 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87681.689019 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189318.614065 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178758.993438 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100371.659485 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98867.741413 # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 5481318 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757626 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 46311 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 188 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 188 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq 128675 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2556003 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 784007 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 1887711 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 148986 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2793 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2797 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 296514 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 296514 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1888256 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 539126 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 4612 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp 4 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5670183 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2628937 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29081 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127780 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8455981 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241706320 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98062173 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40348 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 208940 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 340017781 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 135349 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 5917412 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 2985660 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.026373 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.160242 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 2906919 97.36% 97.36% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 78741 2.64% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 2985660 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5397955498 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 298125 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 2836300178 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1299640147 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 19000487 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 75596896 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 30169 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30169 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178366 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480117 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 43091500 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 100000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 325500 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 90500 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 648000 # Layer occupancy (ticks)
-system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6160500 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 33869500 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 187578393 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36712000 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 36410 # number of replacements
-system.iocache.tags.tagsinuse 1.001800 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 253685816000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 1.001800 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.062613 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.062613 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 327996 # Number of tag accesses
-system.iocache.tags.data_accesses 327996 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 220 # number of ReadReq misses
-system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide 36444 # number of demand (read+write) misses
-system.iocache.demand_misses::total 36444 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide 36444 # number of overall misses
-system.iocache.overall_misses::total 36444 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 35734875 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 35734875 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 4362724518 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 4362724518 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 4398459393 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 4398459393 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 4398459393 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 4398459393 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide 36444 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 36444 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide 36444 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 36444 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 162431.250000 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 162431.250000 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120437.403876 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 120437.403876 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 120690.906404 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 120690.906404 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 120690.906404 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 120690.906404 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 36190 # number of writebacks
-system.iocache.writebacks::total 36190 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 36444 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 36444 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 36444 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 36444 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 24734875 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 24734875 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2549742484 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 2549742484 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 2574477359 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 2574477359 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 2574477359 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 2574477359 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112431.250000 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 112431.250000 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70388.209033 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70388.209033 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 70642.008534 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70642.008534 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 70642.008534 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70642.008534 # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests 339238 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 139305 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 511 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 34136 # Transaction distribution
-system.membus.trans_dist::ReadResp 67474 # Transaction distribution
-system.membus.trans_dist::WriteReq 27584 # Transaction distribution
-system.membus.trans_dist::WriteResp 27584 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 126423 # Transaction distribution
-system.membus.trans_dist::CleanEvict 8081 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 126 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::ReadExReq 134976 # Transaction distribution
-system.membus.trans_dist::ReadExResp 134976 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 33339 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 4572 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450012 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557574 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72869 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72869 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 630443 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16583036 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16746413 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 19063533 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 5056 # Total snoops (count)
-system.membus.snoopTraffic 30848 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 266387 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.019149 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.137048 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 261286 98.09% 98.09% # Request fanout histogram
-system.membus.snoop_fanout::1 5101 1.91% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 266387 # Request fanout histogram
-system.membus.reqLayer0.occupancy 84461000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1733999 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 877020942 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 984714000 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 5968652 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 3039 # number of quiesce instructions executed
+sim_seconds 2.829109
+sim_ticks 2829109393000
+final_tick 2829109393000
+sim_freq 1000000000000
+host_inst_rate 156850
+host_op_rate 190249
+host_tick_rate 3922204627
+host_mem_usage 597276
+host_seconds 721.31
+sim_insts 113136633
+sim_ops 137227543
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.physmem.bytes_read::cpu.dtb.walker 960
+system.physmem.bytes_read::cpu.itb.walker 384
+system.physmem.bytes_read::cpu.inst 1316768
+system.physmem.bytes_read::cpu.data 9473512
+system.physmem.bytes_read::realview.ide 960
+system.physmem.bytes_read::total 10792584
+system.physmem.bytes_inst_read::cpu.inst 1316768
+system.physmem.bytes_inst_read::total 1316768
+system.physmem.bytes_written::writebacks 8092288
+system.physmem.bytes_written::cpu.data 17524
+system.physmem.bytes_written::total 8109812
+system.physmem.num_reads::cpu.dtb.walker 15
+system.physmem.num_reads::cpu.itb.walker 6
+system.physmem.num_reads::cpu.inst 22826
+system.physmem.num_reads::cpu.data 148544
+system.physmem.num_reads::realview.ide 15
+system.physmem.num_reads::total 171406
+system.physmem.num_writes::writebacks 126442
+system.physmem.num_writes::cpu.data 4381
+system.physmem.num_writes::total 130823
+system.physmem.bw_read::cpu.dtb.walker 339
+system.physmem.bw_read::cpu.itb.walker 136
+system.physmem.bw_read::cpu.inst 465436
+system.physmem.bw_read::cpu.data 3348585
+system.physmem.bw_read::realview.ide 339
+system.physmem.bw_read::total 3814834
+system.physmem.bw_inst_read::cpu.inst 465436
+system.physmem.bw_inst_read::total 465436
+system.physmem.bw_write::writebacks 2860366
+system.physmem.bw_write::cpu.data 6194
+system.physmem.bw_write::total 2866560
+system.physmem.bw_total::writebacks 2860366
+system.physmem.bw_total::cpu.dtb.walker 339
+system.physmem.bw_total::cpu.itb.walker 136
+system.physmem.bw_total::cpu.inst 465436
+system.physmem.bw_total::cpu.data 3354779
+system.physmem.bw_total::realview.ide 339
+system.physmem.bw_total::total 6681395
+system.physmem.readReqs 171407
+system.physmem.writeReqs 130823
+system.physmem.readBursts 171407
+system.physmem.writeBursts 130823
+system.physmem.bytesReadDRAM 10960384
+system.physmem.bytesReadWrQ 9600
+system.physmem.bytesWritten 8122304
+system.physmem.bytesReadSys 10792648
+system.physmem.bytesWrittenSys 8109812
+system.physmem.servicedByWrQ 150
+system.physmem.mergedWrBursts 3888
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 10684
+system.physmem.perBankRdBursts::1 10049
+system.physmem.perBankRdBursts::2 10840
+system.physmem.perBankRdBursts::3 10900
+system.physmem.perBankRdBursts::4 13724
+system.physmem.perBankRdBursts::5 10682
+system.physmem.perBankRdBursts::6 11440
+system.physmem.perBankRdBursts::7 11401
+system.physmem.perBankRdBursts::8 10108
+system.physmem.perBankRdBursts::9 10401
+system.physmem.perBankRdBursts::10 10362
+system.physmem.perBankRdBursts::11 9483
+system.physmem.perBankRdBursts::12 10229
+system.physmem.perBankRdBursts::13 11049
+system.physmem.perBankRdBursts::14 10017
+system.physmem.perBankRdBursts::15 9887
+system.physmem.perBankWrBursts::0 8065
+system.physmem.perBankWrBursts::1 7697
+system.physmem.perBankWrBursts::2 8367
+system.physmem.perBankWrBursts::3 8156
+system.physmem.perBankWrBursts::4 8125
+system.physmem.perBankWrBursts::5 8041
+system.physmem.perBankWrBursts::6 8547
+system.physmem.perBankWrBursts::7 8476
+system.physmem.perBankWrBursts::8 7686
+system.physmem.perBankWrBursts::9 7979
+system.physmem.perBankWrBursts::10 7776
+system.physmem.perBankWrBursts::11 7088
+system.physmem.perBankWrBursts::12 7779
+system.physmem.perBankWrBursts::13 8427
+system.physmem.perBankWrBursts::14 7463
+system.physmem.perBankWrBursts::15 7239
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 69
+system.physmem.totGap 2829109158000
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 542
+system.physmem.readPktSize::3 14
+system.physmem.readPktSize::4 3002
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 167849
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 4381
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 126442
+system.physmem.rdQLenPdf::0 150080
+system.physmem.rdQLenPdf::1 14981
+system.physmem.rdQLenPdf::2 5321
+system.physmem.rdQLenPdf::3 857
+system.physmem.rdQLenPdf::4 8
+system.physmem.rdQLenPdf::5 1
+system.physmem.rdQLenPdf::6 1
+system.physmem.rdQLenPdf::7 1
+system.physmem.rdQLenPdf::8 1
+system.physmem.rdQLenPdf::9 1
+system.physmem.rdQLenPdf::10 1
+system.physmem.rdQLenPdf::11 1
+system.physmem.rdQLenPdf::12 1
+system.physmem.rdQLenPdf::13 1
+system.physmem.rdQLenPdf::14 1
+system.physmem.rdQLenPdf::15 0
+system.physmem.rdQLenPdf::16 0
+system.physmem.rdQLenPdf::17 0
+system.physmem.rdQLenPdf::18 0
+system.physmem.rdQLenPdf::19 0
+system.physmem.rdQLenPdf::20 0
+system.physmem.rdQLenPdf::21 0
+system.physmem.rdQLenPdf::22 0
+system.physmem.rdQLenPdf::23 0
+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
+system.physmem.rdQLenPdf::26 0
+system.physmem.rdQLenPdf::27 0
+system.physmem.rdQLenPdf::28 0
+system.physmem.rdQLenPdf::29 0
+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 1
+system.physmem.wrQLenPdf::1 1
+system.physmem.wrQLenPdf::2 1
+system.physmem.wrQLenPdf::3 1
+system.physmem.wrQLenPdf::4 1
+system.physmem.wrQLenPdf::5 1
+system.physmem.wrQLenPdf::6 1
+system.physmem.wrQLenPdf::7 1
+system.physmem.wrQLenPdf::8 1
+system.physmem.wrQLenPdf::9 1
+system.physmem.wrQLenPdf::10 1
+system.physmem.wrQLenPdf::11 1
+system.physmem.wrQLenPdf::12 1
+system.physmem.wrQLenPdf::13 1
+system.physmem.wrQLenPdf::14 1
+system.physmem.wrQLenPdf::15 1803
+system.physmem.wrQLenPdf::16 2658
+system.physmem.wrQLenPdf::17 5613
+system.physmem.wrQLenPdf::18 5988
+system.physmem.wrQLenPdf::19 6569
+system.physmem.wrQLenPdf::20 6381
+system.physmem.wrQLenPdf::21 6737
+system.physmem.wrQLenPdf::22 7035
+system.physmem.wrQLenPdf::23 7852
+system.physmem.wrQLenPdf::24 7599
+system.physmem.wrQLenPdf::25 8624
+system.physmem.wrQLenPdf::26 9219
+system.physmem.wrQLenPdf::27 7734
+system.physmem.wrQLenPdf::28 7242
+system.physmem.wrQLenPdf::29 7370
+system.physmem.wrQLenPdf::30 7208
+system.physmem.wrQLenPdf::31 6701
+system.physmem.wrQLenPdf::32 6786
+system.physmem.wrQLenPdf::33 501
+system.physmem.wrQLenPdf::34 459
+system.physmem.wrQLenPdf::35 378
+system.physmem.wrQLenPdf::36 383
+system.physmem.wrQLenPdf::37 289
+system.physmem.wrQLenPdf::38 265
+system.physmem.wrQLenPdf::39 270
+system.physmem.wrQLenPdf::40 276
+system.physmem.wrQLenPdf::41 266
+system.physmem.wrQLenPdf::42 282
+system.physmem.wrQLenPdf::43 261
+system.physmem.wrQLenPdf::44 314
+system.physmem.wrQLenPdf::45 244
+system.physmem.wrQLenPdf::46 267
+system.physmem.wrQLenPdf::47 237
+system.physmem.wrQLenPdf::48 219
+system.physmem.wrQLenPdf::49 245
+system.physmem.wrQLenPdf::50 257
+system.physmem.wrQLenPdf::51 167
+system.physmem.wrQLenPdf::52 195
+system.physmem.wrQLenPdf::53 254
+system.physmem.wrQLenPdf::54 199
+system.physmem.wrQLenPdf::55 174
+system.physmem.wrQLenPdf::56 193
+system.physmem.wrQLenPdf::57 192
+system.physmem.wrQLenPdf::58 143
+system.physmem.wrQLenPdf::59 217
+system.physmem.wrQLenPdf::60 164
+system.physmem.wrQLenPdf::61 198
+system.physmem.wrQLenPdf::62 91
+system.physmem.wrQLenPdf::63 201
+system.physmem.bytesPerActivate::samples 61301
+system.physmem.bytesPerActivate::mean 311.294889
+system.physmem.bytesPerActivate::gmean 183.533809
+system.physmem.bytesPerActivate::stdev 329.850338
+system.physmem.bytesPerActivate::0-127 22597 36.86% 36.86%
+system.physmem.bytesPerActivate::128-255 14681 23.95% 60.81%
+system.physmem.bytesPerActivate::256-383 6414 10.46% 71.27%
+system.physmem.bytesPerActivate::384-511 3628 5.92% 77.19%
+system.physmem.bytesPerActivate::512-639 2616 4.27% 81.46%
+system.physmem.bytesPerActivate::640-767 1714 2.80% 84.26%
+system.physmem.bytesPerActivate::768-895 1083 1.77% 86.02%
+system.physmem.bytesPerActivate::896-1023 1015 1.66% 87.68%
+system.physmem.bytesPerActivate::1024-1151 7553 12.32% 100.00%
+system.physmem.bytesPerActivate::total 61301
+system.physmem.rdPerTurnAround::samples 6324
+system.physmem.rdPerTurnAround::mean 27.068786
+system.physmem.rdPerTurnAround::stdev 535.793139
+system.physmem.rdPerTurnAround::0-2047 6322 99.97% 99.97%
+system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98%
+system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00%
+system.physmem.rdPerTurnAround::total 6324
+system.physmem.wrPerTurnAround::samples 6324
+system.physmem.wrPerTurnAround::mean 20.068153
+system.physmem.wrPerTurnAround::gmean 18.259919
+system.physmem.wrPerTurnAround::stdev 14.825047
+system.physmem.wrPerTurnAround::16-19 5588 88.36% 88.36%
+system.physmem.wrPerTurnAround::20-23 93 1.47% 89.83%
+system.physmem.wrPerTurnAround::24-27 31 0.49% 90.32%
+system.physmem.wrPerTurnAround::28-31 49 0.77% 91.10%
+system.physmem.wrPerTurnAround::32-35 267 4.22% 95.32%
+system.physmem.wrPerTurnAround::36-39 17 0.27% 95.59%
+system.physmem.wrPerTurnAround::40-43 23 0.36% 95.95%
+system.physmem.wrPerTurnAround::44-47 11 0.17% 96.13%
+system.physmem.wrPerTurnAround::48-51 10 0.16% 96.28%
+system.physmem.wrPerTurnAround::52-55 5 0.08% 96.36%
+system.physmem.wrPerTurnAround::56-59 4 0.06% 96.43%
+system.physmem.wrPerTurnAround::60-63 8 0.13% 96.55%
+system.physmem.wrPerTurnAround::64-67 137 2.17% 98.72%
+system.physmem.wrPerTurnAround::68-71 5 0.08% 98.80%
+system.physmem.wrPerTurnAround::72-75 8 0.13% 98.92%
+system.physmem.wrPerTurnAround::76-79 1 0.02% 98.94%
+system.physmem.wrPerTurnAround::80-83 5 0.08% 99.02%
+system.physmem.wrPerTurnAround::88-91 2 0.03% 99.05%
+system.physmem.wrPerTurnAround::96-99 1 0.02% 99.07%
+system.physmem.wrPerTurnAround::104-107 2 0.03% 99.10%
+system.physmem.wrPerTurnAround::108-111 10 0.16% 99.26%
+system.physmem.wrPerTurnAround::112-115 5 0.08% 99.34%
+system.physmem.wrPerTurnAround::116-119 1 0.02% 99.35%
+system.physmem.wrPerTurnAround::120-123 1 0.02% 99.37%
+system.physmem.wrPerTurnAround::128-131 16 0.25% 99.62%
+system.physmem.wrPerTurnAround::132-135 3 0.05% 99.67%
+system.physmem.wrPerTurnAround::136-139 1 0.02% 99.68%
+system.physmem.wrPerTurnAround::140-143 2 0.03% 99.72%
+system.physmem.wrPerTurnAround::144-147 3 0.05% 99.76%
+system.physmem.wrPerTurnAround::156-159 2 0.03% 99.79%
+system.physmem.wrPerTurnAround::160-163 1 0.02% 99.81%
+system.physmem.wrPerTurnAround::172-175 1 0.02% 99.83%
+system.physmem.wrPerTurnAround::176-179 1 0.02% 99.84%
+system.physmem.wrPerTurnAround::180-183 2 0.03% 99.87%
+system.physmem.wrPerTurnAround::184-187 1 0.02% 99.89%
+system.physmem.wrPerTurnAround::188-191 1 0.02% 99.91%
+system.physmem.wrPerTurnAround::192-195 4 0.06% 99.97%
+system.physmem.wrPerTurnAround::196-199 1 0.02% 99.98%
+system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00%
+system.physmem.wrPerTurnAround::total 6324
+system.physmem.totQLat 4760140250
+system.physmem.totMemAccLat 7971190250
+system.physmem.totBusLat 856280000
+system.physmem.avgQLat 27795.30
+system.physmem.avgBusLat 4999.97
+system.physmem.avgMemAccLat 46545.19
+system.physmem.avgRdBW 3.87
+system.physmem.avgWrBW 2.87
+system.physmem.avgRdBWSys 3.81
+system.physmem.avgWrBWSys 2.87
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 0.05
+system.physmem.busUtilRead 0.03
+system.physmem.busUtilWrite 0.02
+system.physmem.avgRdQLen 1.02
+system.physmem.avgWrQLen 23.64
+system.physmem.readRowHits 141716
+system.physmem.writeRowHits 95150
+system.physmem.readRowHitRate 82.75
+system.physmem.writeRowHitRate 74.96
+system.physmem.avgGap 9360782.05
+system.physmem.pageHitRate 79.43
+system.physmem_0.actEnergy 229572420
+system.physmem_0.preEnergy 122020635
+system.physmem_0.readEnergy 640600800
+system.physmem_0.writeEnergy 341774280
+system.physmem_0.refreshEnergy 5269923360.000001
+system.physmem_0.actBackEnergy 4312565850
+system.physmem_0.preBackEnergy 326693280
+system.physmem_0.actPowerDownEnergy 10849448970
+system.physmem_0.prePowerDownEnergy 7349503200
+system.physmem_0.selfRefreshEnergy 667239109650
+system.physmem_0.totalEnergy 696683452245
+system.physmem_0.averagePower 246.255395
+system.physmem_0.totalIdleTime 2818586504250
+system.physmem_0.memoryStateTime::IDLE 605493250
+system.physmem_0.memoryStateTime::REF 2240628000
+system.physmem_0.memoryStateTime::SREF 2775864285500
+system.physmem_0.memoryStateTime::PRE_PDN 19139403000
+system.physmem_0.memoryStateTime::ACT 7466972000
+system.physmem_0.memoryStateTime::ACT_PDN 23792611250
+system.physmem_1.actEnergy 208116720
+system.physmem_1.preEnergy 110616660
+system.physmem_1.readEnergy 582167040
+system.physmem_1.writeEnergy 320701140
+system.physmem_1.refreshEnergy 5118721920.000001
+system.physmem_1.actBackEnergy 4117624710
+system.physmem_1.preBackEnergy 324216480
+system.physmem_1.actPowerDownEnergy 10065932100
+system.physmem_1.prePowerDownEnergy 7337666400
+system.physmem_1.selfRefreshEnergy 667784018070
+system.physmem_1.totalEnergy 695971721280
+system.physmem_1.averagePower 246.003821
+system.physmem_1.totalIdleTime 2819231186750
+system.physmem_1.memoryStateTime::IDLE 609856000
+system.physmem_1.memoryStateTime::REF 2176896000
+system.physmem_1.memoryStateTime::SREF 2778047948750
+system.physmem_1.memoryStateTime::PRE_PDN 19108514500
+system.physmem_1.memoryStateTime::ACT 7091454250
+system.physmem_1.memoryStateTime::ACT_PDN 22074723500
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.nvmem.bytes_read::cpu.inst 112
+system.realview.nvmem.bytes_read::total 112
+system.realview.nvmem.bytes_inst_read::cpu.inst 112
+system.realview.nvmem.bytes_inst_read::total 112
+system.realview.nvmem.num_reads::cpu.inst 7
+system.realview.nvmem.num_reads::total 7
+system.realview.nvmem.bw_read::cpu.inst 40
+system.realview.nvmem.bw_read::total 40
+system.realview.nvmem.bw_inst_read::cpu.inst 40
+system.realview.nvmem.bw_inst_read::total 40
+system.realview.nvmem.bw_total::cpu.inst 40
+system.realview.nvmem.bw_total::total 40
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.cf0.dma_read_full_pages 0
+system.cf0.dma_read_bytes 1024
+system.cf0.dma_read_txs 1
+system.cf0.dma_write_full_pages 540
+system.cf0.dma_write_bytes 2318336
+system.cf0.dma_write_txs 631
+system.cpu.branchPred.lookups 46858510
+system.cpu.branchPred.condPredicted 23992607
+system.cpu.branchPred.condIncorrect 1178674
+system.cpu.branchPred.BTBLookups 29379094
+system.cpu.branchPred.BTBHits 13526716
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 46.041978
+system.cpu.branchPred.usedRAS 11744952
+system.cpu.branchPred.RASInCorrect 34823
+system.cpu.branchPred.indirectLookups 7931680
+system.cpu.branchPred.indirectHits 7786825
+system.cpu.branchPred.indirectMisses 144855
+system.cpu.branchPredindirectMispredicted 60323
+system.cpu_clk_domain.clock 500
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.hits 0
+system.cpu.dstage2_mmu.stage2_tlb.misses 0
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.cpu.dtb.walker.walks 70955
+system.cpu.dtb.walker.walksShort 70955
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1 28940
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23312
+system.cpu.dtb.walker.walksSquashedBefore 18703
+system.cpu.dtb.walker.walkWaitTime::samples 52252
+system.cpu.dtb.walker.walkWaitTime::mean 400.731072
+system.cpu.dtb.walker.walkWaitTime::stdev 2345.357182
+system.cpu.dtb.walker.walkWaitTime::0-4095 50383 96.42% 96.42%
+system.cpu.dtb.walker.walkWaitTime::4096-8191 693 1.33% 97.75%
+system.cpu.dtb.walker.walkWaitTime::8192-12287 603 1.15% 98.90%
+system.cpu.dtb.walker.walkWaitTime::12288-16383 333 0.64% 99.54%
+system.cpu.dtb.walker.walkWaitTime::16384-20479 70 0.13% 99.67%
+system.cpu.dtb.walker.walkWaitTime::20480-24575 115 0.22% 99.89%
+system.cpu.dtb.walker.walkWaitTime::24576-28671 29 0.06% 99.95%
+system.cpu.dtb.walker.walkWaitTime::28672-32767 4 0.01% 99.96%
+system.cpu.dtb.walker.walkWaitTime::32768-36863 3 0.01% 99.96%
+system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.97%
+system.cpu.dtb.walker.walkWaitTime::40960-45055 4 0.01% 99.98%
+system.cpu.dtb.walker.walkWaitTime::45056-49151 10 0.02% 100.00%
+system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00%
+system.cpu.dtb.walker.walkWaitTime::total 52252
+system.cpu.dtb.walker.walkCompletionTime::samples 16817
+system.cpu.dtb.walker.walkCompletionTime::mean 9418.713207
+system.cpu.dtb.walker.walkCompletionTime::gmean 7646.134327
+system.cpu.dtb.walker.walkCompletionTime::stdev 6474.251777
+system.cpu.dtb.walker.walkCompletionTime::0-8191 8266 49.15% 49.15%
+system.cpu.dtb.walker.walkCompletionTime::8192-16383 6953 41.35% 90.50%
+system.cpu.dtb.walker.walkCompletionTime::16384-24575 1348 8.02% 98.51%
+system.cpu.dtb.walker.walkCompletionTime::24576-32767 164 0.98% 99.49%
+system.cpu.dtb.walker.walkCompletionTime::32768-40959 19 0.11% 99.60%
+system.cpu.dtb.walker.walkCompletionTime::40960-49151 58 0.34% 99.95%
+system.cpu.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.95%
+system.cpu.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.96%
+system.cpu.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.96%
+system.cpu.dtb.walker.walkCompletionTime::90112-98303 2 0.01% 99.98%
+system.cpu.dtb.walker.walkCompletionTime::98304-106495 3 0.02% 99.99%
+system.cpu.dtb.walker.walkCompletionTime::114688-122879 1 0.01% 100.00%
+system.cpu.dtb.walker.walkCompletionTime::total 16817
+system.cpu.dtb.walker.walksPending::samples 118983937724
+system.cpu.dtb.walker.walksPending::mean 0.628000
+system.cpu.dtb.walker.walksPending::stdev 0.489529
+system.cpu.dtb.walker.walksPending::0-1 118937531224 99.96% 99.96%
+system.cpu.dtb.walker.walksPending::2-3 32256000 0.03% 99.99%
+system.cpu.dtb.walker.walksPending::4-5 6888500 0.01% 99.99%
+system.cpu.dtb.walker.walksPending::6-7 4293500 0.00% 100.00%
+system.cpu.dtb.walker.walksPending::8-9 966500 0.00% 100.00%
+system.cpu.dtb.walker.walksPending::10-11 503500 0.00% 100.00%
+system.cpu.dtb.walker.walksPending::12-13 1160000 0.00% 100.00%
+system.cpu.dtb.walker.walksPending::14-15 329500 0.00% 100.00%
+system.cpu.dtb.walker.walksPending::16-17 9000 0.00% 100.00%
+system.cpu.dtb.walker.walksPending::total 118983937724
+system.cpu.dtb.walker.walkPageSizes::4K 6321 82.34% 82.34%
+system.cpu.dtb.walker.walkPageSizes::1M 1356 17.66% 100.00%
+system.cpu.dtb.walker.walkPageSizes::total 7677
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 70955
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 70955
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7677
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7677
+system.cpu.dtb.walker.walkRequestOrigin::total 78632
+system.cpu.dtb.inst_hits 0
+system.cpu.dtb.inst_misses 0
+system.cpu.dtb.read_hits 25413632
+system.cpu.dtb.read_misses 61342
+system.cpu.dtb.write_hits 19864302
+system.cpu.dtb.write_misses 9613
+system.cpu.dtb.flush_tlb 64
+system.cpu.dtb.flush_tlb_mva 917
+system.cpu.dtb.flush_tlb_mva_asid 0
+system.cpu.dtb.flush_tlb_asid 0
+system.cpu.dtb.flush_entries 4258
+system.cpu.dtb.align_faults 389
+system.cpu.dtb.prefetch_faults 2212
+system.cpu.dtb.domain_faults 0
+system.cpu.dtb.perms_faults 1100
+system.cpu.dtb.read_accesses 25474974
+system.cpu.dtb.write_accesses 19873915
+system.cpu.dtb.inst_accesses 0
+system.cpu.dtb.hits 45277934
+system.cpu.dtb.misses 70955
+system.cpu.dtb.accesses 45348889
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.hits 0
+system.cpu.istage2_mmu.stage2_tlb.misses 0
+system.cpu.istage2_mmu.stage2_tlb.accesses 0
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.cpu.itb.walker.walks 12753
+system.cpu.itb.walker.walksShort 12753
+system.cpu.itb.walker.walksShortTerminationLevel::Level1 3360
+system.cpu.itb.walker.walksShortTerminationLevel::Level2 7831
+system.cpu.itb.walker.walksSquashedBefore 1562
+system.cpu.itb.walker.walkWaitTime::samples 11191
+system.cpu.itb.walker.walkWaitTime::mean 685.908319
+system.cpu.itb.walker.walkWaitTime::stdev 2838.967763
+system.cpu.itb.walker.walkWaitTime::0-4095 10603 94.75% 94.75%
+system.cpu.itb.walker.walkWaitTime::4096-8191 139 1.24% 95.99%
+system.cpu.itb.walker.walkWaitTime::8192-12287 279 2.49% 98.48%
+system.cpu.itb.walker.walkWaitTime::12288-16383 104 0.93% 99.41%
+system.cpu.itb.walker.walkWaitTime::16384-20479 24 0.21% 99.62%
+system.cpu.itb.walker.walkWaitTime::20480-24575 27 0.24% 99.87%
+system.cpu.itb.walker.walkWaitTime::24576-28671 5 0.04% 99.91%
+system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.96%
+system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.98%
+system.cpu.itb.walker.walkWaitTime::40960-45055 2 0.02% 100.00%
+system.cpu.itb.walker.walkWaitTime::total 11191
+system.cpu.itb.walker.walkCompletionTime::samples 4876
+system.cpu.itb.walker.walkCompletionTime::mean 9094.852338
+system.cpu.itb.walker.walkCompletionTime::gmean 7058.332581
+system.cpu.itb.walker.walkCompletionTime::stdev 11165.238002
+system.cpu.itb.walker.walkCompletionTime::0-65535 4874 99.96% 99.96%
+system.cpu.itb.walker.walkCompletionTime::65536-131071 1 0.02% 99.98%
+system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00%
+system.cpu.itb.walker.walkCompletionTime::total 4876
+system.cpu.itb.walker.walksPending::samples 24493714212
+system.cpu.itb.walker.walksPending::mean 0.675662
+system.cpu.itb.walker.walksPending::stdev 0.468232
+system.cpu.itb.walker.walksPending::0 7945355000 32.44% 32.44%
+system.cpu.itb.walker.walksPending::1 16547293712 67.56% 100.00%
+system.cpu.itb.walker.walksPending::2 1049500 0.00% 100.00%
+system.cpu.itb.walker.walksPending::3 3000 0.00% 100.00%
+system.cpu.itb.walker.walksPending::4 3500 0.00% 100.00%
+system.cpu.itb.walker.walksPending::5 3000 0.00% 100.00%
+system.cpu.itb.walker.walksPending::6 6500 0.00% 100.00%
+system.cpu.itb.walker.walksPending::total 24493714212
+system.cpu.itb.walker.walkPageSizes::4K 2977 89.83% 89.83%
+system.cpu.itb.walker.walkPageSizes::1M 337 10.17% 100.00%
+system.cpu.itb.walker.walkPageSizes::total 3314
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12753
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 12753
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3314
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 3314
+system.cpu.itb.walker.walkRequestOrigin::total 16067
+system.cpu.itb.inst_hits 66036311
+system.cpu.itb.inst_misses 12753
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.flush_tlb 64
+system.cpu.itb.flush_tlb_mva 917
+system.cpu.itb.flush_tlb_mva_asid 0
+system.cpu.itb.flush_tlb_asid 0
+system.cpu.itb.flush_entries 3015
+system.cpu.itb.align_faults 0
+system.cpu.itb.prefetch_faults 0
+system.cpu.itb.domain_faults 0
+system.cpu.itb.perms_faults 2275
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.inst_accesses 66049064
+system.cpu.itb.hits 66036311
+system.cpu.itb.misses 12753
+system.cpu.itb.accesses 66049064
+system.cpu.numPwrStateTransitions 6078
+system.cpu.pwrStateClkGateDist::samples 3039
+system.cpu.pwrStateClkGateDist::mean 886811818.751892
+system.cpu.pwrStateClkGateDist::stdev 17417921758.732147
+system.cpu.pwrStateClkGateDist::underflows 2967 97.63% 97.63%
+system.cpu.pwrStateClkGateDist::1000-5e+10 66 2.17% 99.80%
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84%
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87%
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90%
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00%
+system.cpu.pwrStateClkGateDist::min_value 501
+system.cpu.pwrStateClkGateDist::max_value 499973248624
+system.cpu.pwrStateClkGateDist::total 3039
+system.cpu.pwrStateResidencyTicks::ON 134088275813
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2695021117187
+system.cpu.numCycles 268176607
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.fetch.icacheStallCycles 104995942
+system.cpu.fetch.Insts 184118580
+system.cpu.fetch.Branches 46858510
+system.cpu.fetch.predictedBranches 33058493
+system.cpu.fetch.Cycles 151932480
+system.cpu.fetch.SquashCycles 6071662
+system.cpu.fetch.TlbCycles 175779
+system.cpu.fetch.MiscStallCycles 8549
+system.cpu.fetch.PendingTrapStallCycles 332119
+system.cpu.fetch.PendingQuiesceStallCycles 875755
+system.cpu.fetch.IcacheWaitRetryStallCycles 141
+system.cpu.fetch.CacheLines 66035161
+system.cpu.fetch.IcacheSquashes 1048417
+system.cpu.fetch.ItlbSquashes 6109
+system.cpu.fetch.rateDist::samples 261356596
+system.cpu.fetch.rateDist::mean 0.859092
+system.cpu.fetch.rateDist::stdev 1.228319
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00%
+system.cpu.fetch.rateDist::0 162403300 62.14% 62.14%
+system.cpu.fetch.rateDist::1 29145504 11.15% 73.29%
+system.cpu.fetch.rateDist::2 14039632 5.37% 78.66%
+system.cpu.fetch.rateDist::3 55768160 21.34% 100.00%
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00%
+system.cpu.fetch.rateDist::min_value 0
+system.cpu.fetch.rateDist::max_value 3
+system.cpu.fetch.rateDist::total 261356596
+system.cpu.fetch.branchRate 0.174730
+system.cpu.fetch.rate 0.686557
+system.cpu.decode.IdleCycles 78122860
+system.cpu.decode.BlockedCycles 112453830
+system.cpu.decode.RunCycles 64368440
+system.cpu.decode.UnblockCycles 3837780
+system.cpu.decode.SquashCycles 2573686
+system.cpu.decode.BranchResolved 10211370
+system.cpu.decode.BranchMispred 470310
+system.cpu.decode.DecodedInsts 157012279
+system.cpu.decode.SquashedInsts 3522469
+system.cpu.rename.SquashCycles 2573686
+system.cpu.rename.IdleCycles 83876823
+system.cpu.rename.BlockCycles 11235911
+system.cpu.rename.serializeStallCycles 76409268
+system.cpu.rename.RunCycles 62454802
+system.cpu.rename.UnblockCycles 24806106
+system.cpu.rename.RenamedInsts 146451322
+system.cpu.rename.SquashedInsts 915133
+system.cpu.rename.ROBFullEvents 474402
+system.cpu.rename.IQFullEvents 66041
+system.cpu.rename.LQFullEvents 19198
+system.cpu.rename.SQFullEvents 22054075
+system.cpu.rename.RenamedOperands 150247130
+system.cpu.rename.RenameLookups 677072667
+system.cpu.rename.int_rename_lookups 163972167
+system.cpu.rename.fp_rename_lookups 11057
+system.cpu.rename.CommittedMaps 141787120
+system.cpu.rename.UndoneMaps 8460004
+system.cpu.rename.serializingInsts 2842191
+system.cpu.rename.tempSerializingInsts 2647031
+system.cpu.rename.skidInsts 13853490
+system.cpu.memDep0.insertedLoads 26341767
+system.cpu.memDep0.insertedStores 21213167
+system.cpu.memDep0.conflictingLoads 1696076
+system.cpu.memDep0.conflictingStores 2157401
+system.cpu.iq.iqInstsAdded 143246065
+system.cpu.iq.iqNonSpecInstsAdded 2116491
+system.cpu.iq.iqInstsIssued 143066858
+system.cpu.iq.iqSquashedInstsIssued 262231
+system.cpu.iq.iqSquashedInstsExamined 8135009
+system.cpu.iq.iqSquashedOperandsExamined 14291222
+system.cpu.iq.iqSquashedNonSpecRemoved 121565
+system.cpu.iq.issued_per_cycle::samples 261356596
+system.cpu.iq.issued_per_cycle::mean 0.547401
+system.cpu.iq.issued_per_cycle::stdev 0.874728
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
+system.cpu.iq.issued_per_cycle::0 173165676 66.26% 66.26%
+system.cpu.iq.issued_per_cycle::1 45227403 17.30% 83.56%
+system.cpu.iq.issued_per_cycle::2 31875093 12.20% 95.76%
+system.cpu.iq.issued_per_cycle::3 10264460 3.93% 99.68%
+system.cpu.iq.issued_per_cycle::4 823931 0.32% 100.00%
+system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::min_value 0
+system.cpu.iq.issued_per_cycle::max_value 5
+system.cpu.iq.issued_per_cycle::total 261356596
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00%
+system.cpu.iq.fu_full::IntAlu 7331892 32.77% 32.77%
+system.cpu.iq.fu_full::IntMult 32 0.00% 32.77%
+system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77%
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77%
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77%
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77%
+system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77%
+system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 32.77%
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77%
+system.cpu.iq.fu_full::FloatMisc 0 0.00% 32.77%
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77%
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77%
+system.cpu.iq.fu_full::MemRead 5620748 25.13% 57.90%
+system.cpu.iq.fu_full::MemWrite 9406816 42.05% 99.95%
+system.cpu.iq.fu_full::FloatMemRead 2397 0.01% 99.96%
+system.cpu.iq.fu_full::FloatMemWrite 8747 0.04% 100.00%
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00%
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00%
+system.cpu.iq.FU_type_0::IntAlu 95871562 67.01% 67.01%
+system.cpu.iq.FU_type_0::IntMult 114346 0.08% 67.09%
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09%
+system.cpu.iq.FU_type_0::SimdFloatMisc 8549 0.01% 67.10%
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10%
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10%
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10%
+system.cpu.iq.FU_type_0::MemRead 26128615 18.26% 85.36%
+system.cpu.iq.FU_type_0::MemWrite 20929052 14.63% 99.99%
+system.cpu.iq.FU_type_0::FloatMemRead 2708 0.00% 99.99%
+system.cpu.iq.FU_type_0::FloatMemWrite 9689 0.01% 100.00%
+system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::total 143066858
+system.cpu.iq.rate 0.533480
+system.cpu.iq.fu_busy_cnt 22370632
+system.cpu.iq.fu_busy_rate 0.156365
+system.cpu.iq.int_inst_queue_reads 570087229
+system.cpu.iq.int_inst_queue_writes 153502844
+system.cpu.iq.int_inst_queue_wakeup_accesses 140012626
+system.cpu.iq.fp_inst_queue_reads 35946
+system.cpu.iq.fp_inst_queue_writes 13310
+system.cpu.iq.fp_inst_queue_wakeup_accesses 11500
+system.cpu.iq.int_alu_accesses 165411608
+system.cpu.iq.fp_alu_accesses 23545
+system.cpu.iew.lsq.thread0.forwLoads 325209
+system.cpu.iew.lsq.thread0.invAddrLoads 0
+system.cpu.iew.lsq.thread0.squashedLoads 1431384
+system.cpu.iew.lsq.thread0.ignoredResponses 764
+system.cpu.iew.lsq.thread0.memOrderViolation 18637
+system.cpu.iew.lsq.thread0.squashedStores 620442
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0
+system.cpu.iew.lsq.thread0.blockedLoads 0
+system.cpu.iew.lsq.thread0.rescheduledLoads 88151
+system.cpu.iew.lsq.thread0.cacheBlocked 6418
+system.cpu.iew.iewIdleCycles 0
+system.cpu.iew.iewSquashCycles 2573686
+system.cpu.iew.iewBlockCycles 1145658
+system.cpu.iew.iewUnblockCycles 407900
+system.cpu.iew.iewDispatchedInsts 145542745
+system.cpu.iew.iewDispSquashedInsts 0
+system.cpu.iew.iewDispLoadInsts 26341767
+system.cpu.iew.iewDispStoreInsts 21213167
+system.cpu.iew.iewDispNonSpecInsts 1093664
+system.cpu.iew.iewIQFullEvents 17707
+system.cpu.iew.iewLSQFullEvents 371985
+system.cpu.iew.memOrderViolationEvents 18637
+system.cpu.iew.predictedTakenIncorrect 275331
+system.cpu.iew.predictedNotTakenIncorrect 475113
+system.cpu.iew.branchMispredicts 750444
+system.cpu.iew.iewExecutedInsts 142167062
+system.cpu.iew.iewExecLoadInsts 25736255
+system.cpu.iew.iewExecSquashedInsts 828929
+system.cpu.iew.exec_swp 0
+system.cpu.iew.exec_nop 180189
+system.cpu.iew.exec_refs 46562321
+system.cpu.iew.exec_branches 26505839
+system.cpu.iew.exec_stores 20826066
+system.cpu.iew.exec_rate 0.530125
+system.cpu.iew.wb_sent 141798243
+system.cpu.iew.wb_count 140024126
+system.cpu.iew.wb_producers 63255174
+system.cpu.iew.wb_consumers 95794820
+system.cpu.iew.wb_rate 0.522134
+system.cpu.iew.wb_fanout 0.660319
+system.cpu.commit.commitSquashedInsts 7349353
+system.cpu.commit.commitNonSpecStalls 1994926
+system.cpu.commit.branchMispredicts 716529
+system.cpu.commit.committed_per_cycle::samples 258462119
+system.cpu.commit.committed_per_cycle::mean 0.531538
+system.cpu.commit.committed_per_cycle::stdev 1.133870
+system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00%
+system.cpu.commit.committed_per_cycle::0 185004934 71.58% 71.58%
+system.cpu.commit.committed_per_cycle::1 43303760 16.75% 88.33%
+system.cpu.commit.committed_per_cycle::2 15456955 5.98% 94.31%
+system.cpu.commit.committed_per_cycle::3 4363252 1.69% 96.00%
+system.cpu.commit.committed_per_cycle::4 6425314 2.49% 98.49%
+system.cpu.commit.committed_per_cycle::5 1625380 0.63% 99.12%
+system.cpu.commit.committed_per_cycle::6 798451 0.31% 99.43%
+system.cpu.commit.committed_per_cycle::7 416424 0.16% 99.59%
+system.cpu.commit.committed_per_cycle::8 1067649 0.41% 100.00%
+system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00%
+system.cpu.commit.committed_per_cycle::min_value 0
+system.cpu.commit.committed_per_cycle::max_value 8
+system.cpu.commit.committed_per_cycle::total 258462119
+system.cpu.commit.committedInsts 113291538
+system.cpu.commit.committedOps 137382448
+system.cpu.commit.swp_count 0
+system.cpu.commit.refs 45503108
+system.cpu.commit.loads 24910383
+system.cpu.commit.membars 814524
+system.cpu.commit.branches 26042703
+system.cpu.commit.fp_insts 11492
+system.cpu.commit.int_insts 120205788
+system.cpu.commit.function_calls 4891273
+system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00%
+system.cpu.commit.op_class_0::IntAlu 91757883 66.79% 66.79%
+system.cpu.commit.op_class_0::IntMult 112908 0.08% 66.87%
+system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87%
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87%
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87%
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87%
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87%
+system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 66.87%
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87%
+system.cpu.commit.op_class_0::FloatMisc 0 0.00% 66.87%
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87%
+system.cpu.commit.op_class_0::SimdFloatMisc 8549 0.01% 66.88%
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88%
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88%
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88%
+system.cpu.commit.op_class_0::MemRead 24907675 18.13% 85.01%
+system.cpu.commit.op_class_0::MemWrite 20583945 14.98% 99.99%
+system.cpu.commit.op_class_0::FloatMemRead 2708 0.00% 99.99%
+system.cpu.commit.op_class_0::FloatMemWrite 8780 0.01% 100.00%
+system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00%
+system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
+system.cpu.commit.op_class_0::total 137382448
+system.cpu.commit.bw_lim_events 1067649
+system.cpu.rob.rob_reads 379891933
+system.cpu.rob.rob_writes 292345121
+system.cpu.timesIdled 894136
+system.cpu.idleCycles 6820011
+system.cpu.quiesceCycles 5390042180
+system.cpu.committedInsts 113136633
+system.cpu.committedOps 137227543
+system.cpu.cpi 2.370378
+system.cpu.cpi_total 2.370378
+system.cpu.ipc 0.421874
+system.cpu.ipc_total 0.421874
+system.cpu.int_regfile_reads 155543428
+system.cpu.int_regfile_writes 88505834
+system.cpu.fp_regfile_reads 9689
+system.cpu.fp_regfile_writes 2716
+system.cpu.cc_regfile_reads 502246692
+system.cpu.cc_regfile_writes 53141585
+system.cpu.misc_regfile_reads 455411720
+system.cpu.misc_regfile_writes 1520982
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.cpu.dcache.tags.replacements 834916
+system.cpu.dcache.tags.tagsinuse 511.950856
+system.cpu.dcache.tags.total_refs 40068822
+system.cpu.dcache.tags.sampled_refs 835428
+system.cpu.dcache.tags.avg_refs 47.962029
+system.cpu.dcache.tags.warmup_cycle 291735500
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.950856
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999904
+system.cpu.dcache.tags.occ_percent::total 0.999904
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 123
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 360
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 29
+system.cpu.dcache.tags.occ_task_id_percent::1024 1
+system.cpu.dcache.tags.tag_accesses 179139020
+system.cpu.dcache.tags.data_accesses 179139020
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.cpu.dcache.ReadReq_hits::cpu.data 23268362
+system.cpu.dcache.ReadReq_hits::total 23268362
+system.cpu.dcache.WriteReq_hits::cpu.data 15549192
+system.cpu.dcache.WriteReq_hits::total 15549192
+system.cpu.dcache.SoftPFReq_hits::cpu.data 346345
+system.cpu.dcache.SoftPFReq_hits::total 346345
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 441888
+system.cpu.dcache.LoadLockedReq_hits::total 441888
+system.cpu.dcache.StoreCondReq_hits::cpu.data 460157
+system.cpu.dcache.StoreCondReq_hits::total 460157
+system.cpu.dcache.demand_hits::cpu.data 38817554
+system.cpu.dcache.demand_hits::total 38817554
+system.cpu.dcache.overall_hits::cpu.data 39163899
+system.cpu.dcache.overall_hits::total 39163899
+system.cpu.dcache.ReadReq_misses::cpu.data 703325
+system.cpu.dcache.ReadReq_misses::total 703325
+system.cpu.dcache.WriteReq_misses::cpu.data 3603267
+system.cpu.dcache.WriteReq_misses::total 3603267
+system.cpu.dcache.SoftPFReq_misses::cpu.data 176818
+system.cpu.dcache.SoftPFReq_misses::total 176818
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 26535
+system.cpu.dcache.LoadLockedReq_misses::total 26535
+system.cpu.dcache.StoreCondReq_misses::cpu.data 4
+system.cpu.dcache.StoreCondReq_misses::total 4
+system.cpu.dcache.demand_misses::cpu.data 4306592
+system.cpu.dcache.demand_misses::total 4306592
+system.cpu.dcache.overall_misses::cpu.data 4483410
+system.cpu.dcache.overall_misses::total 4483410
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11009518000
+system.cpu.dcache.ReadReq_miss_latency::total 11009518000
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 167255817206
+system.cpu.dcache.WriteReq_miss_latency::total 167255817206
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 368105000
+system.cpu.dcache.LoadLockedReq_miss_latency::total 368105000
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 196000
+system.cpu.dcache.StoreCondReq_miss_latency::total 196000
+system.cpu.dcache.demand_miss_latency::cpu.data 178265335206
+system.cpu.dcache.demand_miss_latency::total 178265335206
+system.cpu.dcache.overall_miss_latency::cpu.data 178265335206
+system.cpu.dcache.overall_miss_latency::total 178265335206
+system.cpu.dcache.ReadReq_accesses::cpu.data 23971687
+system.cpu.dcache.ReadReq_accesses::total 23971687
+system.cpu.dcache.WriteReq_accesses::cpu.data 19152459
+system.cpu.dcache.WriteReq_accesses::total 19152459
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 523163
+system.cpu.dcache.SoftPFReq_accesses::total 523163
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468423
+system.cpu.dcache.LoadLockedReq_accesses::total 468423
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 460161
+system.cpu.dcache.StoreCondReq_accesses::total 460161
+system.cpu.dcache.demand_accesses::cpu.data 43124146
+system.cpu.dcache.demand_accesses::total 43124146
+system.cpu.dcache.overall_accesses::cpu.data 43647309
+system.cpu.dcache.overall_accesses::total 43647309
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029340
+system.cpu.dcache.ReadReq_miss_rate::total 0.029340
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188136
+system.cpu.dcache.WriteReq_miss_rate::total 0.188136
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.337979
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.337979
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056648
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056648
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009
+system.cpu.dcache.demand_miss_rate::cpu.data 0.099865
+system.cpu.dcache.demand_miss_rate::total 0.099865
+system.cpu.dcache.overall_miss_rate::cpu.data 0.102719
+system.cpu.dcache.overall_miss_rate::total 0.102719
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15653.528596
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15653.528596
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46417.825048
+system.cpu.dcache.WriteReq_avg_miss_latency::total 46417.825048
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13872.432636
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13872.432636
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 49000
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 49000
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41393.597352
+system.cpu.dcache.demand_avg_miss_latency::total 41393.597352
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39761.104875
+system.cpu.dcache.overall_avg_miss_latency::total 39761.104875
+system.cpu.dcache.blocked_cycles::no_mshrs 631432
+system.cpu.dcache.blocked_cycles::no_targets 0
+system.cpu.dcache.blocked::no_mshrs 7043
+system.cpu.dcache.blocked::no_targets 0
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 89.653841
+system.cpu.dcache.avg_blocked_cycles::no_targets nan
+system.cpu.dcache.writebacks::writebacks 693790
+system.cpu.dcache.writebacks::total 693790
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291766
+system.cpu.dcache.ReadReq_mshr_hits::total 291766
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3304082
+system.cpu.dcache.WriteReq_mshr_hits::total 3304082
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18240
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 18240
+system.cpu.dcache.demand_mshr_hits::cpu.data 3595848
+system.cpu.dcache.demand_mshr_hits::total 3595848
+system.cpu.dcache.overall_mshr_hits::cpu.data 3595848
+system.cpu.dcache.overall_mshr_hits::total 3595848
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 411559
+system.cpu.dcache.ReadReq_mshr_misses::total 411559
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299185
+system.cpu.dcache.WriteReq_mshr_misses::total 299185
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119205
+system.cpu.dcache.SoftPFReq_mshr_misses::total 119205
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8295
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 8295
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4
+system.cpu.dcache.StoreCondReq_mshr_misses::total 4
+system.cpu.dcache.demand_mshr_misses::cpu.data 710744
+system.cpu.dcache.demand_mshr_misses::total 710744
+system.cpu.dcache.overall_mshr_misses::cpu.data 829949
+system.cpu.dcache.overall_mshr_misses::total 829949
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31107
+system.cpu.dcache.ReadReq_mshr_uncacheable::total 31107
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27574
+system.cpu.dcache.WriteReq_mshr_uncacheable::total 27574
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58681
+system.cpu.dcache.overall_mshr_uncacheable_misses::total 58681
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6160571000
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 6160571000
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14913434484
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 14913434484
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1646806500
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1646806500
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 125627500
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 125627500
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 192000
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 192000
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21074005484
+system.cpu.dcache.demand_mshr_miss_latency::total 21074005484
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22720811984
+system.cpu.dcache.overall_mshr_miss_latency::total 22720811984
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6279184500
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6279184500
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6279184500
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 6279184500
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017169
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017169
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015621
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015621
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227854
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227854
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017708
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017708
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016481
+system.cpu.dcache.demand_mshr_miss_rate::total 0.016481
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019015
+system.cpu.dcache.overall_mshr_miss_rate::total 0.019015
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14968.864731
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14968.864731
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49846.865598
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49846.865598
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13814.911287
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13814.911287
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15144.966847
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15144.966847
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 48000
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 48000
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29650.627348
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29650.627348
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27376.154419
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 27376.154419
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201857.604398
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201857.604398
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107005.410610
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107005.410610
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.cpu.icache.tags.replacements 1887504
+system.cpu.icache.tags.tagsinuse 511.315248
+system.cpu.icache.tags.total_refs 64051567
+system.cpu.icache.tags.sampled_refs 1888016
+system.cpu.icache.tags.avg_refs 33.925331
+system.cpu.icache.tags.warmup_cycle 14108989500
+system.cpu.icache.tags.occ_blocks::cpu.inst 511.315248
+system.cpu.icache.tags.occ_percent::cpu.inst 0.998663
+system.cpu.icache.tags.occ_percent::total 0.998663
+system.cpu.icache.tags.occ_task_id_blocks::1024 512
+system.cpu.icache.tags.age_task_id_blocks_1024::0 132
+system.cpu.icache.tags.age_task_id_blocks_1024::1 165
+system.cpu.icache.tags.age_task_id_blocks_1024::2 212
+system.cpu.icache.tags.age_task_id_blocks_1024::3 3
+system.cpu.icache.tags.occ_task_id_percent::1024 1
+system.cpu.icache.tags.tag_accesses 67920204
+system.cpu.icache.tags.data_accesses 67920204
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.cpu.icache.ReadReq_hits::cpu.inst 64051567
+system.cpu.icache.ReadReq_hits::total 64051567
+system.cpu.icache.demand_hits::cpu.inst 64051567
+system.cpu.icache.demand_hits::total 64051567
+system.cpu.icache.overall_hits::cpu.inst 64051567
+system.cpu.icache.overall_hits::total 64051567
+system.cpu.icache.ReadReq_misses::cpu.inst 1980584
+system.cpu.icache.ReadReq_misses::total 1980584
+system.cpu.icache.demand_misses::cpu.inst 1980584
+system.cpu.icache.demand_misses::total 1980584
+system.cpu.icache.overall_misses::cpu.inst 1980584
+system.cpu.icache.overall_misses::total 1980584
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 27586536495
+system.cpu.icache.ReadReq_miss_latency::total 27586536495
+system.cpu.icache.demand_miss_latency::cpu.inst 27586536495
+system.cpu.icache.demand_miss_latency::total 27586536495
+system.cpu.icache.overall_miss_latency::cpu.inst 27586536495
+system.cpu.icache.overall_miss_latency::total 27586536495
+system.cpu.icache.ReadReq_accesses::cpu.inst 66032151
+system.cpu.icache.ReadReq_accesses::total 66032151
+system.cpu.icache.demand_accesses::cpu.inst 66032151
+system.cpu.icache.demand_accesses::total 66032151
+system.cpu.icache.overall_accesses::cpu.inst 66032151
+system.cpu.icache.overall_accesses::total 66032151
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029994
+system.cpu.icache.ReadReq_miss_rate::total 0.029994
+system.cpu.icache.demand_miss_rate::cpu.inst 0.029994
+system.cpu.icache.demand_miss_rate::total 0.029994
+system.cpu.icache.overall_miss_rate::cpu.inst 0.029994
+system.cpu.icache.overall_miss_rate::total 0.029994
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13928.485989
+system.cpu.icache.ReadReq_avg_miss_latency::total 13928.485989
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13928.485989
+system.cpu.icache.demand_avg_miss_latency::total 13928.485989
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13928.485989
+system.cpu.icache.overall_avg_miss_latency::total 13928.485989
+system.cpu.icache.blocked_cycles::no_mshrs 2723
+system.cpu.icache.blocked_cycles::no_targets 0
+system.cpu.icache.blocked::no_mshrs 142
+system.cpu.icache.blocked::no_targets 0
+system.cpu.icache.avg_blocked_cycles::no_mshrs 19.176056
+system.cpu.icache.avg_blocked_cycles::no_targets nan
+system.cpu.icache.writebacks::writebacks 1887504
+system.cpu.icache.writebacks::total 1887504
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92530
+system.cpu.icache.ReadReq_mshr_hits::total 92530
+system.cpu.icache.demand_mshr_hits::cpu.inst 92530
+system.cpu.icache.demand_mshr_hits::total 92530
+system.cpu.icache.overall_mshr_hits::cpu.inst 92530
+system.cpu.icache.overall_mshr_hits::total 92530
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1888054
+system.cpu.icache.ReadReq_mshr_misses::total 1888054
+system.cpu.icache.demand_mshr_misses::cpu.inst 1888054
+system.cpu.icache.demand_mshr_misses::total 1888054
+system.cpu.icache.overall_mshr_misses::cpu.inst 1888054
+system.cpu.icache.overall_mshr_misses::total 1888054
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3009
+system.cpu.icache.ReadReq_mshr_uncacheable::total 3009
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3009
+system.cpu.icache.overall_mshr_uncacheable_misses::total 3009
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24712457497
+system.cpu.icache.ReadReq_mshr_miss_latency::total 24712457497
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24712457497
+system.cpu.icache.demand_mshr_miss_latency::total 24712457497
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24712457497
+system.cpu.icache.overall_mshr_miss_latency::total 24712457497
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 246809500
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 246809500
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 246809500
+system.cpu.icache.overall_mshr_uncacheable_latency::total 246809500
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028593
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028593
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028593
+system.cpu.icache.demand_mshr_miss_rate::total 0.028593
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028593
+system.cpu.icache.overall_mshr_miss_rate::total 0.028593
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13088.851006
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13088.851006
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13088.851006
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13088.851006
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13088.851006
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13088.851006
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82023.762047
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82023.762047
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82023.762047
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82023.762047
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.cpu.l2cache.tags.replacements 98110
+system.cpu.l2cache.tags.tagsinuse 65152.111674
+system.cpu.l2cache.tags.total_refs 5295053
+system.cpu.l2cache.tags.sampled_refs 163498
+system.cpu.l2cache.tags.avg_refs 32.386041
+system.cpu.l2cache.tags.warmup_cycle 91189489000
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 7.957156
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 4.699732
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10410.827737
+system.cpu.l2cache.tags.occ_blocks::cpu.data 54728.627049
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000121
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000072
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158857
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.835093
+system.cpu.l2cache.tags.occ_percent::total 0.994142
+system.cpu.l2cache.tags.occ_task_id_blocks::1023 13
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 65375
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 313
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5397
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59665
+system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997543
+system.cpu.l2cache.tags.tag_accesses 43896238
+system.cpu.l2cache.tags.data_accesses 43896238
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52236
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10063
+system.cpu.l2cache.ReadReq_hits::total 62299
+system.cpu.l2cache.WritebackDirty_hits::writebacks 693790
+system.cpu.l2cache.WritebackDirty_hits::total 693790
+system.cpu.l2cache.WritebackClean_hits::writebacks 1849631
+system.cpu.l2cache.WritebackClean_hits::total 1849631
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 2791
+system.cpu.l2cache.UpgradeReq_hits::total 2791
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2
+system.cpu.l2cache.SCUpgradeReq_hits::total 2
+system.cpu.l2cache.ReadExReq_hits::cpu.data 161416
+system.cpu.l2cache.ReadExReq_hits::total 161416
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1868144
+system.cpu.l2cache.ReadCleanReq_hits::total 1868144
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 525535
+system.cpu.l2cache.ReadSharedReq_hits::total 525535
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 52236
+system.cpu.l2cache.demand_hits::cpu.itb.walker 10063
+system.cpu.l2cache.demand_hits::cpu.inst 1868144
+system.cpu.l2cache.demand_hits::cpu.data 686951
+system.cpu.l2cache.demand_hits::total 2617394
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 52236
+system.cpu.l2cache.overall_hits::cpu.itb.walker 10063
+system.cpu.l2cache.overall_hits::cpu.inst 1868144
+system.cpu.l2cache.overall_hits::cpu.data 686951
+system.cpu.l2cache.overall_hits::total 2617394
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 15
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6
+system.cpu.l2cache.ReadReq_misses::total 21
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 5
+system.cpu.l2cache.UpgradeReq_misses::total 5
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2
+system.cpu.l2cache.SCUpgradeReq_misses::total 2
+system.cpu.l2cache.ReadExReq_misses::cpu.data 135101
+system.cpu.l2cache.ReadExReq_misses::total 135101
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19852
+system.cpu.l2cache.ReadCleanReq_misses::total 19852
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13396
+system.cpu.l2cache.ReadSharedReq_misses::total 13396
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 15
+system.cpu.l2cache.demand_misses::cpu.itb.walker 6
+system.cpu.l2cache.demand_misses::cpu.inst 19852
+system.cpu.l2cache.demand_misses::cpu.data 148497
+system.cpu.l2cache.demand_misses::total 168370
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 15
+system.cpu.l2cache.overall_misses::cpu.itb.walker 6
+system.cpu.l2cache.overall_misses::cpu.inst 19852
+system.cpu.l2cache.overall_misses::cpu.data 148497
+system.cpu.l2cache.overall_misses::total 168370
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4526000
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 2124000
+system.cpu.l2cache.ReadReq_miss_latency::total 6650000
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 144500
+system.cpu.l2cache.UpgradeReq_miss_latency::total 144500
+system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 164000
+system.cpu.l2cache.SCUpgradeReq_miss_latency::total 164000
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12738262000
+system.cpu.l2cache.ReadExReq_miss_latency::total 12738262000
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2147273500
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 2147273500
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1554048000
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 1554048000
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4526000
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 2124000
+system.cpu.l2cache.demand_miss_latency::cpu.inst 2147273500
+system.cpu.l2cache.demand_miss_latency::cpu.data 14292310000
+system.cpu.l2cache.demand_miss_latency::total 16446233500
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4526000
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 2124000
+system.cpu.l2cache.overall_miss_latency::cpu.inst 2147273500
+system.cpu.l2cache.overall_miss_latency::cpu.data 14292310000
+system.cpu.l2cache.overall_miss_latency::total 16446233500
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52251
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10069
+system.cpu.l2cache.ReadReq_accesses::total 62320
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 693790
+system.cpu.l2cache.WritebackDirty_accesses::total 693790
+system.cpu.l2cache.WritebackClean_accesses::writebacks 1849631
+system.cpu.l2cache.WritebackClean_accesses::total 1849631
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2796
+system.cpu.l2cache.UpgradeReq_accesses::total 2796
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4
+system.cpu.l2cache.SCUpgradeReq_accesses::total 4
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 296517
+system.cpu.l2cache.ReadExReq_accesses::total 296517
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1887996
+system.cpu.l2cache.ReadCleanReq_accesses::total 1887996
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 538931
+system.cpu.l2cache.ReadSharedReq_accesses::total 538931
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52251
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 10069
+system.cpu.l2cache.demand_accesses::cpu.inst 1887996
+system.cpu.l2cache.demand_accesses::cpu.data 835448
+system.cpu.l2cache.demand_accesses::total 2785764
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52251
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 10069
+system.cpu.l2cache.overall_accesses::cpu.inst 1887996
+system.cpu.l2cache.overall_accesses::cpu.data 835448
+system.cpu.l2cache.overall_accesses::total 2785764
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000287
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000596
+system.cpu.l2cache.ReadReq_miss_rate::total 0.000337
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.001788
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.001788
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455626
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.455626
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010515
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010515
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024857
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024857
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000287
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000596
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010515
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.177745
+system.cpu.l2cache.demand_miss_rate::total 0.060439
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000287
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000596
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010515
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.177745
+system.cpu.l2cache.overall_miss_rate::total 0.060439
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 301733.333333
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 354000
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 316666.666667
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 28900
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 28900
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82000
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82000
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94286.955685
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94286.955685
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 108164.089261
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 108164.089261
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 116008.360705
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 116008.360705
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 301733.333333
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 354000
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 108164.089261
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96246.456157
+system.cpu.l2cache.demand_avg_miss_latency::total 97679.120390
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 301733.333333
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 354000
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 108164.089261
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96246.456157
+system.cpu.l2cache.overall_avg_miss_latency::total 97679.120390
+system.cpu.l2cache.blocked_cycles::no_mshrs 0
+system.cpu.l2cache.blocked_cycles::no_targets 0
+system.cpu.l2cache.blocked::no_mshrs 0
+system.cpu.l2cache.blocked::no_targets 0
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu.l2cache.writebacks::writebacks 90252
+system.cpu.l2cache.writebacks::total 90252
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 25
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total 25
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 113
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total 113
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 25
+system.cpu.l2cache.demand_mshr_hits::cpu.data 113
+system.cpu.l2cache.demand_mshr_hits::total 138
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 25
+system.cpu.l2cache.overall_mshr_hits::cpu.data 113
+system.cpu.l2cache.overall_mshr_hits::total 138
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 15
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6
+system.cpu.l2cache.ReadReq_mshr_misses::total 21
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 5
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135101
+system.cpu.l2cache.ReadExReq_mshr_misses::total 135101
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19827
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19827
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13283
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13283
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 15
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 19827
+system.cpu.l2cache.demand_mshr_misses::cpu.data 148384
+system.cpu.l2cache.demand_mshr_misses::total 168232
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 15
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 19827
+system.cpu.l2cache.overall_mshr_misses::cpu.data 148384
+system.cpu.l2cache.overall_mshr_misses::total 168232
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3009
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31107
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34116
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27574
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27574
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3009
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58681
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61690
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4376000
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 2064000
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6440000
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 94500
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 94500
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 144000
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 144000
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11387252000
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11387252000
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1947143500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1947143500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1409759500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1409759500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4376000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 2064000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1947143500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12797011500
+system.cpu.l2cache.demand_mshr_miss_latency::total 14750595000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4376000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 2064000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1947143500
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12797011500
+system.cpu.l2cache.overall_mshr_miss_latency::total 14750595000
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209196500
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5890336000
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6099532500
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209196500
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5890336000
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6099532500
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000287
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000596
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000337
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.001788
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.001788
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455626
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455626
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010502
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010502
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024647
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024647
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000287
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000596
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010502
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177610
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.060390
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000287
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000596
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010502
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177610
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.060390
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 291733.333333
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 344000
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 306666.666667
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18900
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18900
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84286.955685
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84286.955685
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 98206.662632
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 98206.662632
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 106132.613115
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 106132.613115
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 291733.333333
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 344000
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 98206.662632
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86242.529518
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87680.078701
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 291733.333333
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 344000
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 98206.662632
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86242.529518
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87680.078701
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69523.595879
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189357.250780
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178788.032008
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69523.595879
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100378.930148
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98873.926082
+system.cpu.toL2Bus.snoop_filter.tot_requests 5480995
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757483
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 46363
+system.cpu.toL2Bus.snoop_filter.tot_snoops 188
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 188
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.cpu.toL2Bus.trans_dist::ReadReq 128702
+system.cpu.toL2Bus.trans_dist::ReadResp 2555842
+system.cpu.toL2Bus.trans_dist::WriteReq 27574
+system.cpu.toL2Bus.trans_dist::WriteResp 27574
+system.cpu.toL2Bus.trans_dist::WritebackDirty 784042
+system.cpu.toL2Bus.trans_dist::WritebackClean 1887504
+system.cpu.toL2Bus.trans_dist::CleanEvict 148984
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2796
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2800
+system.cpu.toL2Bus.trans_dist::ReadExReq 296517
+system.cpu.toL2Bus.trans_dist::ReadExResp 296517
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 1888054
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 539140
+system.cpu.toL2Bus.trans_dist::InvalidateReq 4612
+system.cpu.toL2Bus.trans_dist::InvalidateResp 4
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5669571
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2628934
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29091
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127815
+system.cpu.toL2Bus.pkt_count::total 8455411
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241680080
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98064195
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40276
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209004
+system.cpu.toL2Bus.pkt_size::total 339993555
+system.cpu.toL2Bus.snoops 135415
+system.cpu.toL2Bus.snoopTraffic 5918888
+system.cpu.toL2Bus.snoop_fanout::samples 2985511
+system.cpu.toL2Bus.snoop_fanout::mean 0.026408
+system.cpu.toL2Bus.snoop_fanout::stdev 0.160346
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 2906669 97.36% 97.36%
+system.cpu.toL2Bus.snoop_fanout::1 78842 2.64% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 1
+system.cpu.toL2Bus.snoop_fanout::total 2985511
+system.cpu.toL2Bus.reqLayer0.occupancy 5397581998
+system.cpu.toL2Bus.reqLayer0.utilization 0.2
+system.cpu.toL2Bus.snoopLayer0.occupancy 298125
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer0.occupancy 2835995182
+system.cpu.toL2Bus.respLayer0.utilization 0.1
+system.cpu.toL2Bus.respLayer1.occupancy 1299642147
+system.cpu.toL2Bus.respLayer1.utilization 0.0
+system.cpu.toL2Bus.respLayer2.occupancy 19027489
+system.cpu.toL2Bus.respLayer2.utilization 0.0
+system.cpu.toL2Bus.respLayer3.occupancy 75618391
+system.cpu.toL2Bus.respLayer3.utilization 0.0
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.iobus.trans_dist::ReadReq 30159
+system.iobus.trans_dist::ReadResp 30159
+system.iobus.trans_dist::WriteReq 59014
+system.iobus.trans_dist::WriteResp 59014
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268
+system.iobus.pkt_count_system.bridge.master::total 105458
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888
+system.iobus.pkt_count_system.realview.ide.dma::total 72888
+system.iobus.pkt_count::total 178346
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536
+system.iobus.pkt_size_system.bridge.master::total 159115
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992
+system.iobus.pkt_size_system.realview.ide.dma::total 2320992
+system.iobus.pkt_size::total 2480107
+system.iobus.reqLayer0.occupancy 43091500
+system.iobus.reqLayer0.utilization 0.0
+system.iobus.reqLayer1.occupancy 100000
+system.iobus.reqLayer1.utilization 0.0
+system.iobus.reqLayer2.occupancy 325000
+system.iobus.reqLayer2.utilization 0.0
+system.iobus.reqLayer3.occupancy 28000
+system.iobus.reqLayer3.utilization 0.0
+system.iobus.reqLayer4.occupancy 13500
+system.iobus.reqLayer4.utilization 0.0
+system.iobus.reqLayer7.occupancy 87500
+system.iobus.reqLayer7.utilization 0.0
+system.iobus.reqLayer8.occupancy 634500
+system.iobus.reqLayer8.utilization 0.0
+system.iobus.reqLayer10.occupancy 20000
+system.iobus.reqLayer10.utilization 0.0
+system.iobus.reqLayer13.occupancy 9500
+system.iobus.reqLayer13.utilization 0.0
+system.iobus.reqLayer14.occupancy 9000
+system.iobus.reqLayer14.utilization 0.0
+system.iobus.reqLayer15.occupancy 9000
+system.iobus.reqLayer15.utilization 0.0
+system.iobus.reqLayer16.occupancy 47500
+system.iobus.reqLayer16.utilization 0.0
+system.iobus.reqLayer17.occupancy 8500
+system.iobus.reqLayer17.utilization 0.0
+system.iobus.reqLayer18.occupancy 9500
+system.iobus.reqLayer18.utilization 0.0
+system.iobus.reqLayer19.occupancy 3000
+system.iobus.reqLayer19.utilization 0.0
+system.iobus.reqLayer20.occupancy 9000
+system.iobus.reqLayer20.utilization 0.0
+system.iobus.reqLayer21.occupancy 8500
+system.iobus.reqLayer21.utilization 0.0
+system.iobus.reqLayer23.occupancy 6162500
+system.iobus.reqLayer23.utilization 0.0
+system.iobus.reqLayer24.occupancy 33869500
+system.iobus.reqLayer24.utilization 0.0
+system.iobus.reqLayer25.occupancy 187590638
+system.iobus.reqLayer25.utilization 0.0
+system.iobus.respLayer0.occupancy 82668000
+system.iobus.respLayer0.utilization 0.0
+system.iobus.respLayer3.occupancy 36712000
+system.iobus.respLayer3.utilization 0.0
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.iocache.tags.replacements 36410
+system.iocache.tags.tagsinuse 1.001806
+system.iocache.tags.total_refs 0
+system.iocache.tags.sampled_refs 36426
+system.iocache.tags.avg_refs 0
+system.iocache.tags.warmup_cycle 253685816000
+system.iocache.tags.occ_blocks::realview.ide 1.001806
+system.iocache.tags.occ_percent::realview.ide 0.062613
+system.iocache.tags.occ_percent::total 0.062613
+system.iocache.tags.occ_task_id_blocks::1023 16
+system.iocache.tags.age_task_id_blocks_1023::3 16
+system.iocache.tags.occ_task_id_percent::1023 1
+system.iocache.tags.tag_accesses 327996
+system.iocache.tags.data_accesses 327996
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.iocache.ReadReq_misses::realview.ide 220
+system.iocache.ReadReq_misses::total 220
+system.iocache.WriteLineReq_misses::realview.ide 36224
+system.iocache.WriteLineReq_misses::total 36224
+system.iocache.demand_misses::realview.ide 36444
+system.iocache.demand_misses::total 36444
+system.iocache.overall_misses::realview.ide 36444
+system.iocache.overall_misses::total 36444
+system.iocache.ReadReq_miss_latency::realview.ide 35734875
+system.iocache.ReadReq_miss_latency::total 35734875
+system.iocache.WriteLineReq_miss_latency::realview.ide 4371242763
+system.iocache.WriteLineReq_miss_latency::total 4371242763
+system.iocache.demand_miss_latency::realview.ide 4406977638
+system.iocache.demand_miss_latency::total 4406977638
+system.iocache.overall_miss_latency::realview.ide 4406977638
+system.iocache.overall_miss_latency::total 4406977638
+system.iocache.ReadReq_accesses::realview.ide 220
+system.iocache.ReadReq_accesses::total 220
+system.iocache.WriteLineReq_accesses::realview.ide 36224
+system.iocache.WriteLineReq_accesses::total 36224
+system.iocache.demand_accesses::realview.ide 36444
+system.iocache.demand_accesses::total 36444
+system.iocache.overall_accesses::realview.ide 36444
+system.iocache.overall_accesses::total 36444
+system.iocache.ReadReq_miss_rate::realview.ide 1
+system.iocache.ReadReq_miss_rate::total 1
+system.iocache.WriteLineReq_miss_rate::realview.ide 1
+system.iocache.WriteLineReq_miss_rate::total 1
+system.iocache.demand_miss_rate::realview.ide 1
+system.iocache.demand_miss_rate::total 1
+system.iocache.overall_miss_rate::realview.ide 1
+system.iocache.overall_miss_rate::total 1
+system.iocache.ReadReq_avg_miss_latency::realview.ide 162431.250000
+system.iocache.ReadReq_avg_miss_latency::total 162431.250000
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120672.558608
+system.iocache.WriteLineReq_avg_miss_latency::total 120672.558608
+system.iocache.demand_avg_miss_latency::realview.ide 120924.641587
+system.iocache.demand_avg_miss_latency::total 120924.641587
+system.iocache.overall_avg_miss_latency::realview.ide 120924.641587
+system.iocache.overall_avg_miss_latency::total 120924.641587
+system.iocache.blocked_cycles::no_mshrs 270
+system.iocache.blocked_cycles::no_targets 0
+system.iocache.blocked::no_mshrs 2
+system.iocache.blocked::no_targets 0
+system.iocache.avg_blocked_cycles::no_mshrs 135
+system.iocache.avg_blocked_cycles::no_targets nan
+system.iocache.writebacks::writebacks 36190
+system.iocache.writebacks::total 36190
+system.iocache.ReadReq_mshr_misses::realview.ide 220
+system.iocache.ReadReq_mshr_misses::total 220
+system.iocache.WriteLineReq_mshr_misses::realview.ide 36224
+system.iocache.WriteLineReq_mshr_misses::total 36224
+system.iocache.demand_mshr_misses::realview.ide 36444
+system.iocache.demand_mshr_misses::total 36444
+system.iocache.overall_mshr_misses::realview.ide 36444
+system.iocache.overall_mshr_misses::total 36444
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 24734875
+system.iocache.ReadReq_mshr_miss_latency::total 24734875
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2558257981
+system.iocache.WriteLineReq_mshr_miss_latency::total 2558257981
+system.iocache.demand_mshr_miss_latency::realview.ide 2582992856
+system.iocache.demand_mshr_miss_latency::total 2582992856
+system.iocache.overall_mshr_miss_latency::realview.ide 2582992856
+system.iocache.overall_mshr_miss_latency::total 2582992856
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1
+system.iocache.ReadReq_mshr_miss_rate::total 1
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1
+system.iocache.WriteLineReq_mshr_miss_rate::total 1
+system.iocache.demand_mshr_miss_rate::realview.ide 1
+system.iocache.demand_mshr_miss_rate::total 1
+system.iocache.overall_mshr_miss_rate::realview.ide 1
+system.iocache.overall_mshr_miss_rate::total 1
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112431.250000
+system.iocache.ReadReq_avg_mshr_miss_latency::total 112431.250000
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70623.287903
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70623.287903
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 70875.668313
+system.iocache.demand_avg_mshr_miss_latency::total 70875.668313
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 70875.668313
+system.iocache.overall_avg_mshr_miss_latency::total 70875.668313
+system.membus.snoop_filter.tot_requests 339272
+system.membus.snoop_filter.hit_single_requests 139323
+system.membus.snoop_filter.hit_multi_requests 511
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.membus.trans_dist::ReadReq 34116
+system.membus.trans_dist::ReadResp 67466
+system.membus.trans_dist::WriteReq 27574
+system.membus.trans_dist::WriteResp 27574
+system.membus.trans_dist::WritebackDirty 126442
+system.membus.trans_dist::CleanEvict 8078
+system.membus.trans_dist::UpgradeReq 126
+system.membus.trans_dist::SCUpgradeReq 2
+system.membus.trans_dist::UpgradeResp 2
+system.membus.trans_dist::ReadExReq 134980
+system.membus.trans_dist::ReadExResp 134980
+system.membus.trans_dist::ReadSharedReq 33351
+system.membus.trans_dist::InvalidateReq 36224
+system.membus.trans_dist::InvalidateResp 4572
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105458
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2030
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450060
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557562
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72869
+system.membus.pkt_count_system.iocache.mem_side::total 72869
+system.membus.pkt_count::total 630431
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159115
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4060
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16585276
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16748563
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120
+system.membus.pkt_size_system.iocache.mem_side::total 2317120
+system.membus.pkt_size::total 19065683
+system.membus.snoops 5056
+system.membus.snoopTraffic 30848
+system.membus.snoop_fanout::samples 266373
+system.membus.snoop_fanout::mean 0.019150
+system.membus.snoop_fanout::stdev 0.137052
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 261272 98.09% 98.09%
+system.membus.snoop_fanout::1 5101 1.91% 100.00%
+system.membus.snoop_fanout::2 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 1
+system.membus.snoop_fanout::total 266373
+system.membus.reqLayer0.occupancy 84445500
+system.membus.reqLayer0.utilization 0.0
+system.membus.reqLayer1.occupancy 9000
+system.membus.reqLayer1.utilization 0.0
+system.membus.reqLayer2.occupancy 1696499
+system.membus.reqLayer2.utilization 0.0
+system.membus.reqLayer5.occupancy 877138444
+system.membus.reqLayer5.utilization 0.0
+system.membus.respLayer2.occupancy 984755250
+system.membus.respLayer2.utilization 0.0
+system.membus.respLayer3.occupancy 5968652
+system.membus.respLayer3.utilization 0.0
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.dcc.osc_cpu.clock 16667
+system.realview.dcc.osc_ddr.clock 25000
+system.realview.dcc.osc_hsbm.clock 25000
+system.realview.dcc.osc_pxl.clock 42105
+system.realview.dcc.osc_smb.clock 20000
+system.realview.dcc.osc_sys.clock 16667
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.ethernet.descDMAReads 0
+system.realview.ethernet.descDMAWrites 0
+system.realview.ethernet.descDmaReadBytes 0
+system.realview.ethernet.descDmaWriteBytes 0
+system.realview.ethernet.postedSwi 0
+system.realview.ethernet.coalescedSwi nan
+system.realview.ethernet.totalSwi 0
+system.realview.ethernet.postedRxIdle 0
+system.realview.ethernet.coalescedRxIdle nan
+system.realview.ethernet.totalRxIdle 0
+system.realview.ethernet.postedRxOk 0
+system.realview.ethernet.coalescedRxOk nan
+system.realview.ethernet.totalRxOk 0
+system.realview.ethernet.postedRxDesc 0
+system.realview.ethernet.coalescedRxDesc nan
+system.realview.ethernet.totalRxDesc 0
+system.realview.ethernet.postedTxOk 0
+system.realview.ethernet.coalescedTxOk nan
+system.realview.ethernet.totalTxOk 0
+system.realview.ethernet.postedTxIdle 0
+system.realview.ethernet.coalescedTxIdle nan
+system.realview.ethernet.totalTxIdle 0
+system.realview.ethernet.postedTxDesc 0
+system.realview.ethernet.coalescedTxDesc nan
+system.realview.ethernet.totalTxDesc 0
+system.realview.ethernet.postedRxOrn 0
+system.realview.ethernet.coalescedRxOrn nan
+system.realview.ethernet.totalRxOrn 0
+system.realview.ethernet.coalescedTotal nan
+system.realview.ethernet.postedInterrupts 0
+system.realview.ethernet.droppedPackets 0
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.mcc.osc_clcd.clock 42105
+system.realview.mcc.osc_mcc.clock 20000
+system.realview.mcc.osc_peripheral.clock 41667
+system.realview.mcc.osc_system_bus.clock 41667
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2829109393000
+system.cpu.kern.inst.arm 0
+system.cpu.kern.inst.quiesce 3039
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/dist/m5/system/binaries/boot_emm.arm
+boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
-dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_panic=true
phys_addr_range_64=40
power_model=Null
-readfile=/z/powerjg/gem5-upstream/tests/testing/../halt.sh
+readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/m5/system/disks/linux-aarch32-ael.img
+image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu0.tracer
workload=
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu1.tracer
workload=
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+info: Entering event queue @ 0. Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: instruction 'mcr bpiall' unimplemented
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 29 2016 19:03:48
-gem5 started Nov 29 2016 19:04:20
-gem5 executing on zizzer, pid 5756
-command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
+gem5 compiled Mar 29 2017 18:44:23
+gem5 started Mar 29 2017 18:44:38
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 53279
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2870988926500 because m5_exit instruction encountered
+Exiting @ tick 2871012355500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.870996 # Number of seconds simulated
-sim_ticks 2870995800500 # Number of ticks simulated
-final_tick 2870995800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1013503 # Simulator instruction rate (inst/s)
-host_op_rate 1225877 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 22160332076 # Simulator tick rate (ticks/s)
-host_mem_usage 622032 # Number of bytes of host memory used
-host_seconds 129.56 # Real time elapsed on the host
-sim_insts 131304972 # Number of instructions simulated
-sim_ops 158819278 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1181796 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 1294372 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8555136 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 152212 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 573844 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 414464 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12173424 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1181796 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 152212 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1334008 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8754752 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8772316 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 26919 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 20744 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 133674 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2533 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 8987 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 6476 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 199358 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 136793 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 141184 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 411633 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 450844 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 2979850 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 53017 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 199876 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 144362 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4240140 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 411633 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 53017 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 464650 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3049378 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3055496 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3049378 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 411633 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 456948 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 2979850 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 53017 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 199890 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 144362 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7295636 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 199358 # Number of read requests accepted
-system.physmem.writeReqs 141184 # Number of write requests accepted
-system.physmem.readBursts 199358 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 141184 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 12748800 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 10112 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8785280 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 12173424 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8772316 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 158 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11937 # Per bank write bursts
-system.physmem.perBankRdBursts::1 11961 # Per bank write bursts
-system.physmem.perBankRdBursts::2 12063 # Per bank write bursts
-system.physmem.perBankRdBursts::3 12015 # Per bank write bursts
-system.physmem.perBankRdBursts::4 20362 # Per bank write bursts
-system.physmem.perBankRdBursts::5 11984 # Per bank write bursts
-system.physmem.perBankRdBursts::6 12067 # Per bank write bursts
-system.physmem.perBankRdBursts::7 12160 # Per bank write bursts
-system.physmem.perBankRdBursts::8 12406 # Per bank write bursts
-system.physmem.perBankRdBursts::9 12763 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11654 # Per bank write bursts
-system.physmem.perBankRdBursts::11 11199 # Per bank write bursts
-system.physmem.perBankRdBursts::12 11763 # Per bank write bursts
-system.physmem.perBankRdBursts::13 11689 # Per bank write bursts
-system.physmem.perBankRdBursts::14 11766 # Per bank write bursts
-system.physmem.perBankRdBursts::15 11411 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8587 # Per bank write bursts
-system.physmem.perBankWrBursts::1 8807 # Per bank write bursts
-system.physmem.perBankWrBursts::2 8988 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8742 # Per bank write bursts
-system.physmem.perBankWrBursts::4 8269 # Per bank write bursts
-system.physmem.perBankWrBursts::5 8555 # Per bank write bursts
-system.physmem.perBankWrBursts::6 8883 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8651 # Per bank write bursts
-system.physmem.perBankWrBursts::8 8881 # Per bank write bursts
-system.physmem.perBankWrBursts::9 9204 # Per bank write bursts
-system.physmem.perBankWrBursts::10 8442 # Per bank write bursts
-system.physmem.perBankWrBursts::11 8330 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8611 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8076 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8388 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7856 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 86 # Number of times write queue was full causing retry
-system.physmem.totGap 2870994769000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 9732 # Read request sizes (log2)
-system.physmem.readPktSize::3 28 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 189598 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 4391 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 136793 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 136138 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 17236 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 10604 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 8747 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7299 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 5883 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 5032 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 4260 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3698 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 128 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 84 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 51 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2554 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 3487 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4394 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5386 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6479 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6593 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 7166 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 7546 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 8490 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 8347 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 9668 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 9980 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 8490 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 8119 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 8411 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 9434 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 7894 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 7591 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 637 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 442 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 414 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 292 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 248 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 218 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 227 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 239 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 215 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 211 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 252 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 237 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 193 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 151 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 181 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 201 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 166 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 201 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 162 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 225 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 193 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 209 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 221 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 146 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 250 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 135 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 104 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 244 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 85519 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 251.803880 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 143.212865 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 307.683468 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 42851 50.11% 50.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 18042 21.10% 71.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6336 7.41% 78.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3652 4.27% 82.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2667 3.12% 86.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1677 1.96% 87.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 875 1.02% 88.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 945 1.11% 90.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8474 9.91% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 85519 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6795 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 29.315232 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 564.685462 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6793 99.97% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6795 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6795 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.201619 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.574221 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 13.473858 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5740 84.47% 84.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 356 5.24% 89.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 65 0.96% 90.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 46 0.68% 91.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 271 3.99% 95.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 21 0.31% 95.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 19 0.28% 95.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 18 0.26% 96.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 11 0.16% 96.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 7 0.10% 96.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 2 0.03% 96.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 7 0.10% 96.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 153 2.25% 98.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 7 0.10% 98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 9 0.13% 99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 5 0.07% 99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 7 0.10% 99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 2 0.03% 99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 1 0.01% 99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 3 0.04% 99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 3 0.04% 99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 1 0.01% 99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 4 0.06% 99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 2 0.03% 99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 3 0.04% 99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 2 0.03% 99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 10 0.15% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 1 0.01% 99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 3 0.04% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 2 0.03% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.01% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 1 0.01% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 3 0.04% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 2 0.03% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 2 0.03% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6795 # Writes before turning the bus around for reads
-system.physmem.totQLat 9377591483 # Total ticks spent queuing
-system.physmem.totMemAccLat 13112591483 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 996000000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 47076.26 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 65826.26 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 4.44 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 3.06 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 4.24 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.06 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.06 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing
-system.physmem.readRowHits 166242 # Number of row buffer hits during reads
-system.physmem.writeRowHits 84708 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.45 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 61.70 # Row buffer hit rate for writes
-system.physmem.avgGap 8430662.79 # Average gap between requests
-system.physmem.pageHitRate 74.58 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 309183420 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 164331090 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 746479860 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 362696040 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 6139024320.000001 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 5630456580 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 369226560 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 11487380430 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 9121751040 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 675280298985 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 709613489745 # Total energy per rank (pJ)
-system.physmem_0.averagePower 247.166328 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 2857680941179 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 688127950 # Time in different power states
-system.physmem_0.memoryStateTime::REF 2609960000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 2808734663750 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 23754548081 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 10016707371 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 25191793348 # Time in different power states
-system.physmem_1.actEnergy 301429380 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 160213515 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 675808140 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 353853360 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 6242283840.000001 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 5675698050 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 365488800 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 11403357870 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 9537644640 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 675067441050 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 709786212765 # Total energy per rank (pJ)
-system.physmem_1.averagePower 247.226489 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 2857340478310 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 678311229 # Time in different power states
-system.physmem_1.memoryStateTime::REF 2653946000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 2807745675250 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 24837614861 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 10072973461 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 25007279699 # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks 7823 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 7823 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1468 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6355 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 7823 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 7823 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 7823 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 6429 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 12550.163322 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 11491.858959 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 6296.322703 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383 5867 91.26% 91.26% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767 463 7.20% 98.46% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151 86 1.34% 99.80% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535 8 0.12% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.05% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 6429 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 1181300000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 1181300000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 1181300000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 5000 77.77% 77.77% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1429 22.23% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 6429 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7823 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7823 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6429 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6429 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 14252 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.inst_hits 0 # ITB inst hits
-system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 25081905 # DTB read hits
-system.cpu0.dtb.read_misses 6707 # DTB read misses
-system.cpu0.dtb.write_hits 18693539 # DTB write hits
-system.cpu0.dtb.write_misses 1116 # DTB write misses
-system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3387 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 1738 # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 25088612 # DTB read accesses
-system.cpu0.dtb.write_accesses 18694655 # DTB write accesses
-system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 43775444 # DTB hits
-system.cpu0.dtb.misses 7823 # DTB misses
-system.cpu0.dtb.accesses 43783267 # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks 3349 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12879.339906 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 12002.998619 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 5903.446394 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191 363 15.56% 15.56% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383 1682 72.10% 87.66% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575 212 9.09% 96.74% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767 37 1.59% 98.33% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-40959 36 1.54% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 1180899500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 1180899500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 1180899500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 118659015 # ITB inst hits
-system.cpu0.itb.inst_misses 3349 # ITB inst misses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2087 # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 118662364 # ITB inst accesses
-system.cpu0.itb.hits 118659015 # DTB hits
-system.cpu0.itb.misses 3349 # DTB misses
-system.cpu0.itb.accesses 118662364 # DTB accesses
-system.cpu0.numPwrStateTransitions 3724 # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples 1862 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean 1466902343.272825 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev 23730658455.603134 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows 1082 58.11% 58.11% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10 775 41.62% 99.73% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 499963373360 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total 1862 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON 139623637326 # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731372163174 # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles 5741991601 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 1862 # number of quiesce instructions executed
-system.cpu0.committedInsts 114996919 # Number of instructions committed
-system.cpu0.committedOps 138962993 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 122999157 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses
-system.cpu0.num_func_calls 12659267 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 15643522 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 122999157 # number of integer instructions
-system.cpu0.num_fp_insts 9755 # number of float instructions
-system.cpu0.num_int_register_reads 226444380 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 85465434 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 503448381 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 52091583 # number of times the CC registers were written
-system.cpu0.num_mem_refs 44908198 # number of memory refs
-system.cpu0.num_load_insts 25331105 # Number of load instructions
-system.cpu0.num_store_insts 19577093 # Number of store instructions
-system.cpu0.num_idle_cycles 5462744326.346097 # Number of idle cycles
-system.cpu0.num_busy_cycles 279247274.653903 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.048632 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.951368 # Percentage of idle cycles
-system.cpu0.Branches 29039529 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 97695313 68.45% 68.45% # Class of executed instruction
-system.cpu0.op_class::IntMult 108459 0.08% 68.53% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::FloatMultAcc 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::FloatMisc 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 7991 0.01% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::MemRead 25328849 17.75% 86.28% # Class of executed instruction
-system.cpu0.op_class::MemWrite 19569598 13.71% 99.99% # Class of executed instruction
-system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% # Class of executed instruction
-system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 142722234 # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements 690121 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 498.373175 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 42907120 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 690633 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 62.127237 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 1207348000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.373175 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.973385 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.973385 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 88185256 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 88185256 # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data 23824030 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 23824030 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 17964029 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 17964029 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318863 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 318863 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364525 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 364525 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361510 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 361510 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 41788059 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 41788059 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 42106922 # number of overall hits
-system.cpu0.dcache.overall_hits::total 42106922 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 394827 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 394827 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 324085 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 324085 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127008 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 127008 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21435 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 21435 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19554 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 19554 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 718912 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 718912 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 845920 # number of overall misses
-system.cpu0.dcache.overall_misses::total 845920 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5517390500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 5517390500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6298218500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 6298218500 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 337010500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 337010500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 458737500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 458737500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1113000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1113000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 11815609000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 11815609000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 11815609000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 11815609000 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 24218857 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 24218857 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 18288114 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 18288114 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 445871 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 445871 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 385960 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 385960 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381064 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 381064 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 42506971 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 42506971 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 42952842 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 42952842 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016302 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.016302 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017721 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.017721 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.284854 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.284854 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055537 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055537 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051314 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051314 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016913 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.016913 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019694 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.019694 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13974.197560 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13974.197560 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19433.847602 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 19433.847602 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15722.439935 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15722.439935 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23460.033753 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23460.033753 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16435.403777 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16435.403777 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13967.761727 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 13967.761727 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks 690121 # number of writebacks
-system.cpu0.dcache.writebacks::total 690121 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25200 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 25200 # number of ReadReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15056 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15056 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 25200 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 25200 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 25200 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 25200 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369627 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 369627 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324085 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 324085 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100010 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 100010 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6379 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6379 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19554 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 19554 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 693712 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 693712 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 793722 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 793722 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31768 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31768 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28446 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28446 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60214 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60214 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4739955500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4739955500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5974133500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5974133500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1650418500 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1650418500 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101003000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101003000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 439215500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 439215500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1081000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1081000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10714089000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 10714089000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12364507500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 12364507500 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6631169500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6631169500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6631169500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6631169500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015262 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015262 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017721 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017721 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224303 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224303 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016528 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016528 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051314 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051314 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016320 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.016320 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018479 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.018479 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12823.618134 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12823.618134 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18433.847602 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18433.847602 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16502.534747 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16502.534747 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15833.672989 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15833.672989 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22461.670246 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22461.670246 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15444.577865 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15444.577865 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15577.881802 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15577.881802 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208737.392974 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208737.392974 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110126.706414 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110126.706414 # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements 1095423 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.436912 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 117563071 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1095935 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 107.271938 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 14178985000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436912 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998900 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.998900 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 238413974 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 238413974 # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst 117563071 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 117563071 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 117563071 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 117563071 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 117563071 # number of overall hits
-system.cpu0.icache.overall_hits::total 117563071 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 1095944 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 1095944 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 1095944 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 1095944 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 1095944 # number of overall misses
-system.cpu0.icache.overall_misses::total 1095944 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11846969000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 11846969000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 11846969000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 11846969000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 11846969000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 11846969000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 118659015 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 118659015 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 118659015 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 118659015 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 118659015 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 118659015 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009236 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.009236 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009236 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.009236 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009236 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.009236 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10809.830612 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10809.830612 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10809.830612 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10809.830612 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10809.830612 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10809.830612 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks 1095423 # number of writebacks
-system.cpu0.icache.writebacks::total 1095423 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1095944 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 1095944 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 1095944 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 1095944 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 1095944 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 1095944 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11298997000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 11298997000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11298997000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 11298997000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11298997000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 11298997000 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 863305500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 863305500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 863305500 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total 863305500 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009236 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009236 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009236 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.009236 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009236 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.009236 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10309.830612 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10309.830612 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10309.830612 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10309.830612 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10309.830612 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10309.830612 # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067 # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067 # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued 1843455 # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified 1843489 # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit 30 # number of redundant prefetches already in prefetch queue
-system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage 237167 # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements 260392 # number of replacements
-system.cpu0.l2cache.tags.tagsinuse 15616.554479 # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs 1673878 # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs 276011 # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs 6.064534 # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 14458.510897 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.380966 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.135465 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1156.527151 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks 0.882477 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000084 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.070589 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total 0.953159 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022 316 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15300 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 27 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 129 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 150 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 827 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6046 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6216 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2035 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.019287 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.933838 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses 60952812 # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses 60952812 # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9949 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4513 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total 14462 # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks 474087 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total 474087 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks 1283679 # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total 1283679 # number of WritebackClean hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data 226501 # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total 226501 # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1033387 # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total 1033387 # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 374984 # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total 374984 # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9949 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4513 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst 1033387 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data 601485 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total 1649334 # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9949 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4513 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst 1033387 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data 601485 # number of overall hits
-system.cpu0.l2cache.overall_hits::total 1649334 # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 333 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 154 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total 487 # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54609 # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total 54609 # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19552 # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total 19552 # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data 42975 # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total 42975 # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62557 # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total 62557 # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101032 # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total 101032 # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 333 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker 154 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst 62557 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data 144007 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total 207051 # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 333 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker 154 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst 62557 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data 144007 # number of overall misses
-system.cpu0.l2cache.overall_misses::total 207051 # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 8868000 # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3618500 # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total 12486500 # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 29801000 # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total 29801000 # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 8716000 # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 8716000 # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1032499 # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1032499 # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2749345500 # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total 2749345500 # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3431495000 # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3431495000 # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3333037000 # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3333037000 # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 8868000 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3618500 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3431495000 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data 6082382500 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total 9526364000 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 8868000 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3618500 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3431495000 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data 6082382500 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total 9526364000 # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10282 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4667 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total 14949 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks 474087 # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total 474087 # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks 1283679 # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total 1283679 # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54609 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total 54609 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19552 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total 19552 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269476 # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total 269476 # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1095944 # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total 1095944 # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 476016 # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total 476016 # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10282 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4667 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst 1095944 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data 745492 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total 1856385 # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10282 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4667 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst 1095944 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data 745492 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total 1856385 # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.032387 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.032998 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total 0.032577 # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.159476 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total 0.159476 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.057080 # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.057080 # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.212245 # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.212245 # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.032387 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.032998 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.057080 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.193170 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total 0.111535 # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.032387 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.032998 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.057080 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.193170 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total 0.111535 # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26630.630631 # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23496.753247 # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25639.630390 # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 545.715908 # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 545.715908 # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 445.785597 # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 445.785597 # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 516249.500000 # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 516249.500000 # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63975.462478 # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63975.462478 # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 54853.893249 # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 54853.893249 # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32989.914087 # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32989.914087 # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26630.630631 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23496.753247 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 54853.893249 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42236.714188 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 46009.746391 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26630.630631 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23496.753247 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 54853.893249 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42236.714188 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 46009.746391 # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches 10486 # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks 227470 # number of writebacks
-system.cpu0.l2cache.writebacks::total 227470 # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1575 # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total 1575 # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 30 # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1605 # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total 1605 # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1605 # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total 1605 # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 333 # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 154 # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total 487 # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 261736 # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total 261736 # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 54609 # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total 54609 # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19552 # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19552 # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41400 # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total 41400 # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62557 # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62557 # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101002 # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101002 # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 333 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 154 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62557 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142402 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total 205446 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 333 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 154 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62557 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142402 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 261736 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total 467182 # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31768 # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40790 # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28446 # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28446 # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60214 # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69236 # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 6870000 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2694500 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 9564500 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16748653122 # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16748653122 # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 936375500 # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 936375500 # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 292739000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 292739000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 840499 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 840499 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2221757000 # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2221757000 # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3056153000 # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3056153000 # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2721461500 # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2721461500 # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 6870000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2694500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3056153000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4943218500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total 8008936000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 6870000 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2694500 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3056153000 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4943218500 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16748653122 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 24757589122 # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 795640500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6376615000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7172255500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 795640500 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6376615000 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7172255500 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.032387 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.032998 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.032577 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153631 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153631 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.057080 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.057080 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.212182 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.212182 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.032387 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032998 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.057080 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191017 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110670 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.032387 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032998 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.057080 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191017 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.251662 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 19639.630390 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63990.636068 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63990.636068 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17146.908019 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17146.908019 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14972.330196 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14972.330196 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 420249.500000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 420249.500000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53665.628019 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53665.628019 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 48853.893249 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 48853.893249 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26944.629809 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26944.629809 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 48853.893249 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34713.125518 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38983.168326 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 48853.893249 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34713.125518 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63990.636068 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52993.456773 # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200724.471166 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175833.672469 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105899.209486 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103591.419204 # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests 3713043 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1871637 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27791 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 210694 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 209047 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1647 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq 61395 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 1681090 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 28446 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 28446 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 701864 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 1311457 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 80209 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 307976 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 86960 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41708 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 111633 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 288540 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 285048 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1095944 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 562349 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 3227 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 12 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3305355 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2550756 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11066 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24460 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 5891637 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140283576 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96129280 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18668 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 41128 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 236472652 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 885693 # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic 18656572 # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples 2784580 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.090516 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.288973 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 2534179 91.01% 91.01% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 248754 8.93% 99.94% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 1647 0.06% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 2784580 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 3695245998 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 113887546 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 1652938000 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1201348488 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 14180994 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks 3368 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 3368 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 669 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2699 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 3368 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 3368 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 3368 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 2598 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 12496.920708 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 11544.208502 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 5669.313441 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191 611 23.52% 23.52% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1671 64.32% 87.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575 230 8.85% 96.69% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767 69 2.66% 99.35% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959 10 0.38% 99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.08% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 2598 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples -1937787828 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 -1937787828 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total -1937787828 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 1937 74.56% 74.56% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 661 25.44% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 2598 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3368 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3368 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2598 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2598 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 5966 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.inst_hits 0 # ITB inst hits
-system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 3952331 # DTB read hits
-system.cpu1.dtb.read_misses 2852 # DTB read misses
-system.cpu1.dtb.write_hits 3427850 # DTB write hits
-system.cpu1.dtb.write_misses 516 # DTB write misses
-system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1975 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 341 # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 3955183 # DTB read accesses
-system.cpu1.dtb.write_accesses 3428366 # DTB write accesses
-system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 7380181 # DTB hits
-system.cpu1.dtb.misses 3368 # DTB misses
-system.cpu1.dtb.accesses 7383549 # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks 1746 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12746.160795 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11849.716682 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 5651.710937 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191 170 15.36% 15.36% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287 628 56.73% 72.09% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383 162 14.63% 86.72% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.43% 91.15% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575 38 3.43% 94.58% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671 32 2.89% 97.47% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 99.01% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-36863 4 0.36% 99.37% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.46% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples -1938367828 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 -1938367828 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total -1938367828 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 16663369 # ITB inst hits
-system.cpu1.itb.inst_misses 1746 # ITB inst misses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1084 # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 16665115 # ITB inst accesses
-system.cpu1.itb.hits 16663369 # DTB hits
-system.cpu1.itb.misses 1746 # DTB misses
-system.cpu1.itb.accesses 16665115 # DTB accesses
-system.cpu1.numPwrStateTransitions 5435 # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples 2718 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean 1046549937.704562 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev 25917662670.452511 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows 1945 71.56% 71.56% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10 767 28.22% 99.78% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 929980418584 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total 2718 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON 26473069819 # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844522730681 # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles 5741059879 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2718 # number of quiesce instructions executed
-system.cpu1.committedInsts 16308053 # Number of instructions committed
-system.cpu1.committedOps 19856285 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 17888019 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses
-system.cpu1.num_func_calls 1028859 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1844250 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 17888019 # number of integer instructions
-system.cpu1.num_fp_insts 1792 # number of float instructions
-system.cpu1.num_int_register_reads 32444258 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 12537466 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 72543530 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 6508973 # number of times the CC registers were written
-system.cpu1.num_mem_refs 7613771 # number of memory refs
-system.cpu1.num_load_insts 4063495 # Number of load instructions
-system.cpu1.num_store_insts 3550276 # Number of store instructions
-system.cpu1.num_idle_cycles 5688122330.646462 # Number of idle cycles
-system.cpu1.num_busy_cycles 52937548.353538 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.009221 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.990779 # Percentage of idle cycles
-system.cpu1.Branches 2952894 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 12563541 62.17% 62.17% # Class of executed instruction
-system.cpu1.op_class::IntMult 26310 0.13% 62.30% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::FloatMultAcc 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::FloatMisc 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 3279 0.02% 62.32% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 62.32% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.32% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.32% # Class of executed instruction
-system.cpu1.op_class::MemRead 4062979 20.11% 82.43% # Class of executed instruction
-system.cpu1.op_class::MemWrite 3549000 17.56% 99.99% # Class of executed instruction
-system.cpu1.op_class::FloatMemRead 516 0.00% 99.99% # Class of executed instruction
-system.cpu1.op_class::FloatMemWrite 1276 0.01% 100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 20206967 # Class of executed instruction
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements 187241 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 470.165247 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 7113602 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 187604 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 37.918179 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 128171950500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.165247 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.918291 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.918291 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 290 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 73 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 14979376 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 14979376 # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data 3640649 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 3640649 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 3239316 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 3239316 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49005 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 49005 # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78940 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 78940 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70837 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 70837 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 6879965 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 6879965 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 6928970 # number of overall hits
-system.cpu1.dcache.overall_hits::total 6928970 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 133578 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 133578 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 91863 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 91863 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30193 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 30193 # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16916 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 16916 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23207 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 23207 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 225441 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 225441 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 255634 # number of overall misses
-system.cpu1.dcache.overall_misses::total 255634 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2045952000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 2045952000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2531885000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 2531885000 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322352500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 322352500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544400500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 544400500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2036500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2036500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 4577837000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 4577837000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 4577837000 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 4577837000 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 3774227 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 3774227 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 3331179 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 3331179 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79198 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 79198 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95856 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 95856 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94044 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 94044 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 7105406 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 7105406 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 7184604 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 7184604 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035392 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.035392 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027577 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.027577 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381234 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381234 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176473 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176473 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246767 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246767 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031728 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.031728 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035581 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.035581 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15316.534160 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15316.534160 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27561.531846 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 27561.531846 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19056.071175 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19056.071175 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23458.460809 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23458.460809 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20306.142184 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 20306.142184 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17907.778308 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 17907.778308 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks 187241 # number of writebacks
-system.cpu1.dcache.writebacks::total 187241 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 248 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11947 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11947 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 248 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 248 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133330 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 133330 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91863 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 91863 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29503 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 29503 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4969 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4969 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23207 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 23207 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 225193 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 225193 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 254696 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 254696 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3077 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3077 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2432 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2432 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5509 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5509 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1901282500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1901282500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2440022000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2440022000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 505317500 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 505317500 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91175500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91175500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521240500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521240500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1989500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1989500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4341304500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 4341304500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4846622000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 4846622000 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 442663500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 442663500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 442663500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 442663500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035326 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035326 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027577 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027577 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.372522 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.372522 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051838 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051838 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246767 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246767 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031693 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.031693 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035450 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.035450 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14259.975249 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14259.975249 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26561.531846 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26561.531846 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17127.664983 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17127.664983 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18348.862950 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18348.862950 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22460.486060 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22460.486060 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19278.150298 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19278.150298 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19029.046393 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19029.046393 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143862.040949 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143862.040949 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80352.786350 # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80352.786350 # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements 503470 # number of replacements
-system.cpu1.icache.tags.tagsinuse 498.455555 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 16159382 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 503982 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 32.063411 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 85409649000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.455555 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973546 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.973546 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::4 4 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 33830710 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 33830710 # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst 16159382 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 16159382 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 16159382 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 16159382 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 16159382 # number of overall hits
-system.cpu1.icache.overall_hits::total 16159382 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 503982 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 503982 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 503982 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 503982 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 503982 # number of overall misses
-system.cpu1.icache.overall_misses::total 503982 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4760681000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 4760681000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 4760681000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 4760681000 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 4760681000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 4760681000 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 16663364 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 16663364 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 16663364 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 16663364 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 16663364 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 16663364 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030245 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.030245 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030245 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.030245 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030245 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.030245 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9446.132997 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 9446.132997 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9446.132997 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 9446.132997 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9446.132997 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 9446.132997 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks 503470 # number of writebacks
-system.cpu1.icache.writebacks::total 503470 # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 503982 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 503982 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 503982 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 503982 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 503982 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 503982 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
-system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable
-system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
-system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4508690000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 4508690000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4508690000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 4508690000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4508690000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 4508690000 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17068500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17068500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17068500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 17068500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030245 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030245 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030245 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.030245 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030245 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.030245 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8946.132997 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8946.132997 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8946.132997 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 8946.132997 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8946.132997 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 8946.132997 # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96432.203390 # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96432.203390 # average overall mshr uncacheable latency
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued 202393 # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified 202393 # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
-system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage 60767 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements 44084 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 14674.344516 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 603056 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 58488 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 10.310765 # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14288.601821 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.272921 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.058859 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 381.410915 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks 0.872107 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000139 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023279 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total 0.895651 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022 311 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14077 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 292 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 892 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2699 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10486 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.018982 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.859192 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses 24261935 # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses 24261935 # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3748 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1963 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total 5711 # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks 114339 # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total 114339 # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks 565289 # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total 565289 # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27869 # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total 27869 # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 482614 # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total 482614 # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98302 # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total 98302 # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3748 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1963 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst 482614 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data 126171 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total 614496 # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3748 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1963 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst 482614 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data 126171 # number of overall hits
-system.cpu1.l2cache.overall_hits::total 614496 # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 433 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 316 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total 749 # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29344 # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total 29344 # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23201 # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total 23201 # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34650 # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total 34650 # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21368 # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total 21368 # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69500 # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total 69500 # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 433 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker 316 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst 21368 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data 104150 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total 126267 # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 433 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker 316 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst 21368 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data 104150 # number of overall misses
-system.cpu1.l2cache.overall_misses::total 126267 # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8916500 # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6346000 # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total 15262500 # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14232000 # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total 14232000 # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17729000 # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17729000 # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1919000 # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1919000 # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1493005000 # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total 1493005000 # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 842821500 # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total 842821500 # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1603059500 # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1603059500 # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8916500 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6346000 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst 842821500 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data 3096064500 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total 3954148500 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8916500 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6346000 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst 842821500 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data 3096064500 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total 3954148500 # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4181 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2279 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total 6460 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114339 # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total 114339 # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks 565289 # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total 565289 # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29344 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total 29344 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23201 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total 23201 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62519 # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total 62519 # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 503982 # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total 503982 # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167802 # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total 167802 # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4181 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2279 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst 503982 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data 230321 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total 740763 # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4181 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2279 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst 503982 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data 230321 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total 740763 # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.103564 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138657 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total 0.115944 # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.554232 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total 0.554232 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.042398 # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.042398 # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.414179 # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.414179 # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.103564 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138657 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.042398 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.452195 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total 0.170455 # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.103564 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138657 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.042398 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.452195 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total 0.170455 # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20592.378753 # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20082.278481 # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20377.169559 # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 485.005453 # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 485.005453 # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 764.148097 # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 764.148097 # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 319833.333333 # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 319833.333333 # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43088.167388 # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43088.167388 # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39443.162673 # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39443.162673 # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23065.604317 # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23065.604317 # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20592.378753 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20082.278481 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39443.162673 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29726.975516 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 31315.771342 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20592.378753 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20082.278481 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39443.162673 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29726.975516 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 31315.771342 # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches 850 # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks 33278 # number of writebacks
-system.cpu1.l2cache.writebacks::total 33278 # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 91 # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total 91 # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data 91 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data 91 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total 91 # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 433 # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 316 # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 26693 # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total 26693 # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29344 # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29344 # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23201 # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23201 # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34559 # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total 34559 # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21368 # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21368 # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69500 # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69500 # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 433 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 316 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21368 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104059 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total 126176 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 433 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 316 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21368 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104059 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 26693 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total 152869 # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3077 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3254 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2432 # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2432 # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5509 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5686 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6318500 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4450000 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10768500 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 957745966 # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 957745966 # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 449306000 # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 449306000 # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347204000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347204000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1637000 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1637000 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1274798000 # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1274798000 # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 714613500 # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 714613500 # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1186059500 # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1186059500 # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6318500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4450000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 714613500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2460857500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total 3186239500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6318500 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4450000 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 714613500 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2460857500 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 957745966 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total 4143985466 # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15741000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 417705000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 433446000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 15741000 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 417705000 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 433446000 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.103564 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138657 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.115944 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.552776 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.552776 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.042398 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042398 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.414179 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.414179 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.103564 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.138657 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.042398 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.451800 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170332 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.103564 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.138657 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.042398 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.451800 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.206367 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14377.169559 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35880.042183 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35880.042183 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15311.682116 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15311.682116 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14965.044610 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14965.044610 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 272833.333333 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 272833.333333 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36887.583553 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36887.583553 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33443.162673 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33443.162673 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17065.604317 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17065.604317 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33443.162673 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23648.675271 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25252.341967 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33443.162673 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23648.675271 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35880.042183 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27108.082515 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135750.731232 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133204.056546 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75822.290797 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76230.390433 # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests 1483973 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 749706 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11083 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 112750 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104482 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8268 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq 12645 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 721727 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 2432 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 2432 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 148874 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 576372 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 28336 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 31823 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 70615 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40952 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 85036 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 38 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 69693 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 67178 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 503982 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263487 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 292 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1511788 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 838524 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5603 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10248 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 2366163 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64477636 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29432570 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9116 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16724 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 93936046 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 334351 # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic 4909260 # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples 1058830 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.130816 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.359612 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 928586 87.70% 87.70% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 121976 11.52% 99.22% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 8268 0.78% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1058830 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 1438248000 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 79282585 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 756150000 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 376097000 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 6067998 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 31015 # Transaction distribution
-system.iobus.trans_dist::ReadResp 31015 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59423 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59423 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 48604000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 15000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 623000 # Layer occupancy (ticks)
-system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 46500 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6201500 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 32041500 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 187869528 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 36445 # number of replacements
-system.iocache.tags.tagsinuse 14.382505 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 290037968000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 14.382505 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.898907 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.898907 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 328311 # Number of tag accesses
-system.iocache.tags.data_accesses 328311 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
-system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses
-system.iocache.demand_misses::total 36479 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide 36479 # number of overall misses
-system.iocache.overall_misses::total 36479 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 41042377 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 41042377 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 4379492151 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 4379492151 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 4420534528 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 4420534528 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 4420534528 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 4420534528 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 160950.498039 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 160950.498039 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120900.291271 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 120900.291271 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 121180.255161 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 121180.255161 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 121180.255161 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 121180.255161 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 9 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 33.111111 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 36190 # number of writebacks
-system.iocache.writebacks::total 36190 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 28292377 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 28292377 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2566405842 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 2566405842 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 2594698219 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 2594698219 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 2594698219 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 2594698219 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110950.498039 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 110950.498039 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70848.217811 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70848.217811 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 71128.545711 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 71128.545711 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 71128.545711 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 71128.545711 # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements 137345 # number of replacements
-system.l2c.tags.tagsinuse 65074.392349 # Cycle average of tags in use
-system.l2c.tags.total_refs 526935 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 202695 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 2.599645 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 103119965000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 6537.248776 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.009779 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.050987 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 7065.227850 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 6920.254188 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37485.581661 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954844 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 1513.426266 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 3159.258777 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2388.379223 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.099751 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.107807 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.105595 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.571985 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.023093 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.048206 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036444 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022 34308 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 31034 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2 136 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3 4715 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4 29456 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 1168 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 29797 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022 0.523499 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.473541 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 6118121 # Number of tag accesses
-system.l2c.tags.data_accesses 6118121 # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks 260748 # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total 260748 # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data 39886 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 4893 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 44779 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 2390 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 2219 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 4609 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 3995 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 1504 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 5499 # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 159 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker 75 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst 44649 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data 52745 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45897 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 46 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker 28 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst 18994 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data 11024 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5470 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 179087 # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 159 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 44649 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 56740 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher 45897 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 46 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 28 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 18994 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 12528 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher 5470 # number of demand (read+write) hits
-system.l2c.demand_hits::total 184586 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 159 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 44649 # number of overall hits
-system.l2c.overall_hits::cpu0.data 56740 # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher 45897 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 46 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 28 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 18994 # number of overall hits
-system.l2c.overall_hits::cpu1.data 12528 # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher 5470 # number of overall hits
-system.l2c.overall_hits::total 184586 # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data 631 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 289 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 920 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 83 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 96 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 179 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 11301 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 8030 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 19331 # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst 17908 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data 9085 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133844 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst 2374 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data 942 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6476 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total 170639 # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 17908 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 20386 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher 133844 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 2374 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 8972 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher 6476 # number of demand (read+write) misses
-system.l2c.demand_misses::total 189970 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 17908 # number of overall misses
-system.l2c.overall_misses::cpu0.data 20386 # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher 133844 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 2374 # number of overall misses
-system.l2c.overall_misses::cpu1.data 8972 # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher 6476 # number of overall misses
-system.l2c.overall_misses::total 189970 # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data 10365500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 935500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 11301000 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 563000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 162500 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 725500 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 1654925500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 828235000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 2483160500 # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 1167000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 185500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1949681500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data 1106313500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15937420718 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 90000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst 261013000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data 123092000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 836855283 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 20215818501 # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker 1167000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker 185500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 1949681500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 2761239000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15937420718 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker 90000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 261013000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 951327000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 836855283 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 22698979001 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker 1167000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker 185500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 1949681500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 2761239000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15937420718 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker 90000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 261013000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 951327000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 836855283 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 22698979001 # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks 260748 # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total 260748 # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 40517 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 5182 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 45699 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 2473 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 2315 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 4788 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 15296 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 9534 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 24830 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 166 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 77 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst 62557 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data 61830 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179741 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 47 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 28 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst 21368 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data 11966 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11946 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total 349726 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 166 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 77 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 62557 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 77126 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179741 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 47 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 28 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 21368 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 21500 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11946 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 374556 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 166 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 77 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 62557 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 77126 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179741 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 47 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 28 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 21368 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 21500 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11946 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 374556 # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.015574 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.055770 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.020132 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.033562 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.041469 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.037385 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.738821 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.842249 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.778534 # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.042169 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.025974 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.286267 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.146935 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744649 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.021277 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.111101 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078723 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.542106 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total 0.487922 # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.042169 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.025974 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.286267 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.264321 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744649 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.021277 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.111101 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.417302 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.542106 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.507187 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.042169 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.025974 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.286267 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.264321 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744649 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.021277 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.111101 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.417302 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.542106 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.507187 # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16427.099842 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3237.024221 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 12283.695652 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6783.132530 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1692.708333 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 4053.072626 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 146440.624723 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103142.590286 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 128454.839377 # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 166714.285714 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92750 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 108872.096270 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 121773.637865 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119074.599668 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90000 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 109946.503791 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 130670.912951 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 129224.101760 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 118471.266832 # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 166714.285714 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92750 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 108872.096270 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 135447.807319 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119074.599668 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 109946.503791 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 106032.880071 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 129224.101760 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 119487.176928 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 166714.285714 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92750 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 108872.096270 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 135447.807319 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119074.599668 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 109946.503791 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 106032.880071 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 129224.101760 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 119487.176928 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks 100603 # number of writebacks
-system.l2c.writebacks::total 100603 # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 6 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total 10 # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 10 # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks 3738 # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total 3738 # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data 631 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 289 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 920 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 83 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 96 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 179 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 11301 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 8030 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 19331 # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17904 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9085 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133844 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2368 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data 942 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6476 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total 170629 # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 17904 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 20386 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133844 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 2368 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 8972 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6476 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 189960 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 17904 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 20386 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133844 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 2368 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 8972 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6476 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 189960 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31768 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3074 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total 44041 # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28446 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2432 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total 30878 # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60214 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5506 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total 74919 # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14735500 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 6305500 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 21041000 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2194500 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2340500 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 4535000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1541915500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 747935000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 2289850500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1097000 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 165500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1770529000 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1015463500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14598976726 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 80000 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 236880000 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 113671002 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 772093287 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total 18508956015 # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1097000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 165500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 1770529000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 2557379000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14598976726 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 80000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 236880000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 861606002 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 772093287 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 20798806515 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1097000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 165500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 1770529000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 2557379000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14598976726 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 80000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 236880000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 861606002 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 772093287 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 20798806515 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 633244000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5804773000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12555000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362314500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 6812886500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 633244000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5804773000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12555000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362314500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 6812886500 # number of overall MSHR uncacheable cycles
-system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
-system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.015574 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.055770 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.020132 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.033562 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.041469 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.037385 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.738821 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.842249 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.778534 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.042169 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.025974 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.286203 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146935 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744649 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.021277 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.110820 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078723 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542106 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.487893 # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.042169 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.025974 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.286203 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.264321 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744649 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.021277 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.110820 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.417302 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542106 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.507160 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.042169 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.025974 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.286203 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.264321 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744649 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.021277 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.110820 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.417302 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542106 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.507160 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23352.614897 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21818.339100 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22870.652174 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26439.759036 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24380.208333 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25335.195531 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 136440.624723 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 93142.590286 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 118454.839377 # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82750 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 98890.136282 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 111773.637865 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80000 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100033.783784 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120669.853503 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108474.854890 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82750 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 98890.136282 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125447.807319 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100033.783784 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96032.768836 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 109490.453332 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82750 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 98890.136282 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125447.807319 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100033.783784 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96032.768836 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 109490.453332 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182723.904558 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117864.183474 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154694.182693 # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96402.381506 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65803.577915 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 90936.698301 # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests 502698 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 282285 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 634 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 44041 # Transaction distribution
-system.membus.trans_dist::ReadResp 214925 # Transaction distribution
-system.membus.trans_dist::WriteReq 30878 # Transaction distribution
-system.membus.trans_dist::WriteResp 30878 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 136793 # Transaction distribution
-system.membus.trans_dist::CleanEvict 16421 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 64440 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 38073 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 16 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
-system.membus.trans_dist::ReadExReq 39751 # Transaction distribution
-system.membus.trans_dist::ReadExResp 19302 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 170884 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 4530 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13584 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 647548 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 769084 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 842023 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27168 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18628620 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 18818654 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 21135774 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 126969 # Total snoops (count)
-system.membus.snoopTraffic 37632 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 424292 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.012213 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.109837 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 419110 98.78% 98.78% # Request fanout histogram
-system.membus.snoop_fanout::1 5182 1.22% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 424292 # Request fanout histogram
-system.membus.reqLayer0.occupancy 88179000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 11330000 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 970733801 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1113560532 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 7243389 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests 1013922 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 527446 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 187526 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 29573 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 28355 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 1218 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq 44044 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 511645 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 30878 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 30878 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 361351 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 119836 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 109190 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 42682 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 151872 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 50757 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 50757 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 467605 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 4574 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 3427 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1275330 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 317115 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1592445 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35259052 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5662514 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 40921566 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 390876 # Total snoops (count)
-system.toL2Bus.snoopTraffic 15646988 # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples 887171 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.397282 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.492133 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 535932 60.41% 60.41% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 350021 39.45% 99.86% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 1218 0.14% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 887171 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 894860010 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2155585 # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 676392933 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 238880542 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+sim_seconds 2.871012
+sim_ticks 2871012355500
+final_tick 2871012355500
+sim_freq 1000000000000
+host_inst_rate 1070603
+host_op_rate 1294963
+host_tick_rate 23409963735
+host_mem_usage 628644
+host_seconds 122.64
+sim_insts 131299345
+sim_ops 158815094
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.physmem.bytes_read::cpu0.dtb.walker 448
+system.physmem.bytes_read::cpu0.itb.walker 128
+system.physmem.bytes_read::cpu0.inst 1181348
+system.physmem.bytes_read::cpu0.data 1294820
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 8551616
+system.physmem.bytes_read::cpu1.dtb.walker 64
+system.physmem.bytes_read::cpu1.inst 152660
+system.physmem.bytes_read::cpu1.data 573908
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 413696
+system.physmem.bytes_read::realview.ide 960
+system.physmem.bytes_read::total 12169648
+system.physmem.bytes_inst_read::cpu0.inst 1181348
+system.physmem.bytes_inst_read::cpu1.inst 152660
+system.physmem.bytes_inst_read::total 1334008
+system.physmem.bytes_written::writebacks 8749184
+system.physmem.bytes_written::cpu0.data 17524
+system.physmem.bytes_written::cpu1.data 40
+system.physmem.bytes_written::total 8766748
+system.physmem.num_reads::cpu0.dtb.walker 7
+system.physmem.num_reads::cpu0.itb.walker 2
+system.physmem.num_reads::cpu0.inst 26912
+system.physmem.num_reads::cpu0.data 20751
+system.physmem.num_reads::cpu0.l2cache.prefetcher 133619
+system.physmem.num_reads::cpu1.dtb.walker 1
+system.physmem.num_reads::cpu1.inst 2540
+system.physmem.num_reads::cpu1.data 8988
+system.physmem.num_reads::cpu1.l2cache.prefetcher 6464
+system.physmem.num_reads::realview.ide 15
+system.physmem.num_reads::total 199299
+system.physmem.num_writes::writebacks 136706
+system.physmem.num_writes::cpu0.data 4381
+system.physmem.num_writes::cpu1.data 10
+system.physmem.num_writes::total 141097
+system.physmem.bw_read::cpu0.dtb.walker 156
+system.physmem.bw_read::cpu0.itb.walker 45
+system.physmem.bw_read::cpu0.inst 411474
+system.physmem.bw_read::cpu0.data 450998
+system.physmem.bw_read::cpu0.l2cache.prefetcher 2978606
+system.physmem.bw_read::cpu1.dtb.walker 22
+system.physmem.bw_read::cpu1.inst 53173
+system.physmem.bw_read::cpu1.data 199897
+system.physmem.bw_read::cpu1.l2cache.prefetcher 144094
+system.physmem.bw_read::realview.ide 334
+system.physmem.bw_read::total 4238800
+system.physmem.bw_inst_read::cpu0.inst 411474
+system.physmem.bw_inst_read::cpu1.inst 53173
+system.physmem.bw_inst_read::total 464647
+system.physmem.bw_write::writebacks 3047421
+system.physmem.bw_write::cpu0.data 6104
+system.physmem.bw_write::cpu1.data 14
+system.physmem.bw_write::total 3053539
+system.physmem.bw_total::writebacks 3047421
+system.physmem.bw_total::cpu0.dtb.walker 156
+system.physmem.bw_total::cpu0.itb.walker 45
+system.physmem.bw_total::cpu0.inst 411474
+system.physmem.bw_total::cpu0.data 457101
+system.physmem.bw_total::cpu0.l2cache.prefetcher 2978606
+system.physmem.bw_total::cpu1.dtb.walker 22
+system.physmem.bw_total::cpu1.inst 53173
+system.physmem.bw_total::cpu1.data 199911
+system.physmem.bw_total::cpu1.l2cache.prefetcher 144094
+system.physmem.bw_total::realview.ide 334
+system.physmem.bw_total::total 7292339
+system.physmem.readReqs 199299
+system.physmem.writeReqs 141097
+system.physmem.readBursts 199299
+system.physmem.writeBursts 141097
+system.physmem.bytesReadDRAM 12744832
+system.physmem.bytesReadWrQ 10304
+system.physmem.bytesWritten 8779712
+system.physmem.bytesReadSys 12169648
+system.physmem.bytesWrittenSys 8766748
+system.physmem.servicedByWrQ 161
+system.physmem.mergedWrBursts 3897
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 11941
+system.physmem.perBankRdBursts::1 11941
+system.physmem.perBankRdBursts::2 12061
+system.physmem.perBankRdBursts::3 12014
+system.physmem.perBankRdBursts::4 20277
+system.physmem.perBankRdBursts::5 11993
+system.physmem.perBankRdBursts::6 12082
+system.physmem.perBankRdBursts::7 12163
+system.physmem.perBankRdBursts::8 12412
+system.physmem.perBankRdBursts::9 12768
+system.physmem.perBankRdBursts::10 11659
+system.physmem.perBankRdBursts::11 11203
+system.physmem.perBankRdBursts::12 11765
+system.physmem.perBankRdBursts::13 11689
+system.physmem.perBankRdBursts::14 11759
+system.physmem.perBankRdBursts::15 11411
+system.physmem.perBankWrBursts::0 8593
+system.physmem.perBankWrBursts::1 8809
+system.physmem.perBankWrBursts::2 8990
+system.physmem.perBankWrBursts::3 8736
+system.physmem.perBankWrBursts::4 8204
+system.physmem.perBankWrBursts::5 8547
+system.physmem.perBankWrBursts::6 8879
+system.physmem.perBankWrBursts::7 8644
+system.physmem.perBankWrBursts::8 8884
+system.physmem.perBankWrBursts::9 9196
+system.physmem.perBankWrBursts::10 8452
+system.physmem.perBankWrBursts::11 8329
+system.physmem.perBankWrBursts::12 8624
+system.physmem.perBankWrBursts::13 8076
+system.physmem.perBankWrBursts::14 8386
+system.physmem.perBankWrBursts::15 7834
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 79
+system.physmem.totGap 2871011323500
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 9732
+system.physmem.readPktSize::3 28
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 189539
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 4391
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 136706
+system.physmem.rdQLenPdf::0 135966
+system.physmem.rdQLenPdf::1 17240
+system.physmem.rdQLenPdf::2 10602
+system.physmem.rdQLenPdf::3 8757
+system.physmem.rdQLenPdf::4 7338
+system.physmem.rdQLenPdf::5 5891
+system.physmem.rdQLenPdf::6 5065
+system.physmem.rdQLenPdf::7 4253
+system.physmem.rdQLenPdf::8 3715
+system.physmem.rdQLenPdf::9 134
+system.physmem.rdQLenPdf::10 84
+system.physmem.rdQLenPdf::11 52
+system.physmem.rdQLenPdf::12 25
+system.physmem.rdQLenPdf::13 7
+system.physmem.rdQLenPdf::14 3
+system.physmem.rdQLenPdf::15 2
+system.physmem.rdQLenPdf::16 2
+system.physmem.rdQLenPdf::17 2
+system.physmem.rdQLenPdf::18 0
+system.physmem.rdQLenPdf::19 0
+system.physmem.rdQLenPdf::20 0
+system.physmem.rdQLenPdf::21 0
+system.physmem.rdQLenPdf::22 0
+system.physmem.rdQLenPdf::23 0
+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
+system.physmem.rdQLenPdf::26 0
+system.physmem.rdQLenPdf::27 0
+system.physmem.rdQLenPdf::28 0
+system.physmem.rdQLenPdf::29 0
+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 1
+system.physmem.wrQLenPdf::1 1
+system.physmem.wrQLenPdf::2 1
+system.physmem.wrQLenPdf::3 1
+system.physmem.wrQLenPdf::4 1
+system.physmem.wrQLenPdf::5 1
+system.physmem.wrQLenPdf::6 1
+system.physmem.wrQLenPdf::7 1
+system.physmem.wrQLenPdf::8 1
+system.physmem.wrQLenPdf::9 1
+system.physmem.wrQLenPdf::10 1
+system.physmem.wrQLenPdf::11 1
+system.physmem.wrQLenPdf::12 1
+system.physmem.wrQLenPdf::13 1
+system.physmem.wrQLenPdf::14 1
+system.physmem.wrQLenPdf::15 2529
+system.physmem.wrQLenPdf::16 3481
+system.physmem.wrQLenPdf::17 4419
+system.physmem.wrQLenPdf::18 5391
+system.physmem.wrQLenPdf::19 6442
+system.physmem.wrQLenPdf::20 6509
+system.physmem.wrQLenPdf::21 7071
+system.physmem.wrQLenPdf::22 7524
+system.physmem.wrQLenPdf::23 8510
+system.physmem.wrQLenPdf::24 8349
+system.physmem.wrQLenPdf::25 9606
+system.physmem.wrQLenPdf::26 10061
+system.physmem.wrQLenPdf::27 8512
+system.physmem.wrQLenPdf::28 8112
+system.physmem.wrQLenPdf::29 8311
+system.physmem.wrQLenPdf::30 9404
+system.physmem.wrQLenPdf::31 7883
+system.physmem.wrQLenPdf::32 7638
+system.physmem.wrQLenPdf::33 727
+system.physmem.wrQLenPdf::34 448
+system.physmem.wrQLenPdf::35 388
+system.physmem.wrQLenPdf::36 335
+system.physmem.wrQLenPdf::37 256
+system.physmem.wrQLenPdf::38 272
+system.physmem.wrQLenPdf::39 265
+system.physmem.wrQLenPdf::40 225
+system.physmem.wrQLenPdf::41 178
+system.physmem.wrQLenPdf::42 199
+system.physmem.wrQLenPdf::43 179
+system.physmem.wrQLenPdf::44 202
+system.physmem.wrQLenPdf::45 241
+system.physmem.wrQLenPdf::46 234
+system.physmem.wrQLenPdf::47 176
+system.physmem.wrQLenPdf::48 183
+system.physmem.wrQLenPdf::49 185
+system.physmem.wrQLenPdf::50 199
+system.physmem.wrQLenPdf::51 165
+system.physmem.wrQLenPdf::52 205
+system.physmem.wrQLenPdf::53 189
+system.physmem.wrQLenPdf::54 159
+system.physmem.wrQLenPdf::55 158
+system.physmem.wrQLenPdf::56 255
+system.physmem.wrQLenPdf::57 220
+system.physmem.wrQLenPdf::58 143
+system.physmem.wrQLenPdf::59 244
+system.physmem.wrQLenPdf::60 209
+system.physmem.wrQLenPdf::61 180
+system.physmem.wrQLenPdf::62 157
+system.physmem.wrQLenPdf::63 257
+system.physmem.bytesPerActivate::samples 85488
+system.physmem.bytesPerActivate::mean 251.783642
+system.physmem.bytesPerActivate::gmean 143.209500
+system.physmem.bytesPerActivate::stdev 307.626161
+system.physmem.bytesPerActivate::0-127 42834 50.11% 50.11%
+system.physmem.bytesPerActivate::128-255 18033 21.09% 71.20%
+system.physmem.bytesPerActivate::256-383 6282 7.35% 78.55%
+system.physmem.bytesPerActivate::384-511 3726 4.36% 82.91%
+system.physmem.bytesPerActivate::512-639 2666 3.12% 86.02%
+system.physmem.bytesPerActivate::640-767 1646 1.93% 87.95%
+system.physmem.bytesPerActivate::768-895 883 1.03% 88.98%
+system.physmem.bytesPerActivate::896-1023 975 1.14% 90.12%
+system.physmem.bytesPerActivate::1024-1151 8443 9.88% 100.00%
+system.physmem.bytesPerActivate::total 85488
+system.physmem.rdPerTurnAround::samples 6782
+system.physmem.rdPerTurnAround::mean 29.362430
+system.physmem.rdPerTurnAround::stdev 565.225219
+system.physmem.rdPerTurnAround::0-2047 6780 99.97% 99.97%
+system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99%
+system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00%
+system.physmem.rdPerTurnAround::total 6782
+system.physmem.wrPerTurnAround::samples 6782
+system.physmem.wrPerTurnAround::mean 20.227514
+system.physmem.wrPerTurnAround::gmean 18.570606
+system.physmem.wrPerTurnAround::stdev 13.781277
+system.physmem.wrPerTurnAround::16-19 5756 84.87% 84.87%
+system.physmem.wrPerTurnAround::20-23 321 4.73% 89.60%
+system.physmem.wrPerTurnAround::24-27 54 0.80% 90.40%
+system.physmem.wrPerTurnAround::28-31 63 0.93% 91.33%
+system.physmem.wrPerTurnAround::32-35 275 4.05% 95.38%
+system.physmem.wrPerTurnAround::36-39 22 0.32% 95.71%
+system.physmem.wrPerTurnAround::40-43 19 0.28% 95.99%
+system.physmem.wrPerTurnAround::44-47 12 0.18% 96.17%
+system.physmem.wrPerTurnAround::48-51 17 0.25% 96.42%
+system.physmem.wrPerTurnAround::52-55 2 0.03% 96.45%
+system.physmem.wrPerTurnAround::56-59 1 0.01% 96.46%
+system.physmem.wrPerTurnAround::60-63 11 0.16% 96.62%
+system.physmem.wrPerTurnAround::64-67 152 2.24% 98.86%
+system.physmem.wrPerTurnAround::68-71 7 0.10% 98.97%
+system.physmem.wrPerTurnAround::72-75 10 0.15% 99.12%
+system.physmem.wrPerTurnAround::76-79 5 0.07% 99.19%
+system.physmem.wrPerTurnAround::80-83 2 0.03% 99.22%
+system.physmem.wrPerTurnAround::84-87 1 0.01% 99.23%
+system.physmem.wrPerTurnAround::88-91 1 0.01% 99.25%
+system.physmem.wrPerTurnAround::92-95 2 0.03% 99.28%
+system.physmem.wrPerTurnAround::96-99 3 0.04% 99.32%
+system.physmem.wrPerTurnAround::100-103 2 0.03% 99.35%
+system.physmem.wrPerTurnAround::104-107 1 0.01% 99.37%
+system.physmem.wrPerTurnAround::108-111 5 0.07% 99.44%
+system.physmem.wrPerTurnAround::112-115 2 0.03% 99.47%
+system.physmem.wrPerTurnAround::120-123 1 0.01% 99.48%
+system.physmem.wrPerTurnAround::124-127 2 0.03% 99.51%
+system.physmem.wrPerTurnAround::128-131 8 0.12% 99.63%
+system.physmem.wrPerTurnAround::132-135 3 0.04% 99.68%
+system.physmem.wrPerTurnAround::136-139 5 0.07% 99.75%
+system.physmem.wrPerTurnAround::144-147 2 0.03% 99.78%
+system.physmem.wrPerTurnAround::156-159 3 0.04% 99.82%
+system.physmem.wrPerTurnAround::160-163 2 0.03% 99.85%
+system.physmem.wrPerTurnAround::164-167 1 0.01% 99.87%
+system.physmem.wrPerTurnAround::172-175 3 0.04% 99.91%
+system.physmem.wrPerTurnAround::180-183 1 0.01% 99.93%
+system.physmem.wrPerTurnAround::188-191 1 0.01% 99.94%
+system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00%
+system.physmem.wrPerTurnAround::total 6782
+system.physmem.totQLat 9440334255
+system.physmem.totMemAccLat 13174171755
+system.physmem.totBusLat 995690000
+system.physmem.avgQLat 47405.99
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 66155.99
+system.physmem.avgRdBW 4.44
+system.physmem.avgWrBW 3.06
+system.physmem.avgRdBWSys 4.24
+system.physmem.avgWrBWSys 3.05
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 0.06
+system.physmem.busUtilRead 0.03
+system.physmem.busUtilWrite 0.02
+system.physmem.avgRdQLen 1.05
+system.physmem.avgWrQLen 22.72
+system.physmem.readRowHits 166173
+system.physmem.writeRowHits 84659
+system.physmem.readRowHitRate 83.45
+system.physmem.writeRowHitRate 61.70
+system.physmem.avgGap 8434327.44
+system.physmem.pageHitRate 74.58
+system.physmem_0.actEnergy 308819280
+system.physmem_0.preEnergy 164137545
+system.physmem_0.readEnergy 745930080
+system.physmem_0.writeEnergy 362278440
+system.physmem_0.refreshEnergy 6150087840.000001
+system.physmem_0.actBackEnergy 5622831690
+system.physmem_0.preBackEnergy 364043040
+system.physmem_0.actPowerDownEnergy 11524806630
+system.physmem_0.prePowerDownEnergy 9158295840
+system.physmem_0.selfRefreshEnergy 675248492655
+system.physmem_0.totalEnergy 709652557290
+system.physmem_0.averagePower 247.178510
+system.physmem_0.totalIdleTime 2857727193718
+system.physmem_0.memoryStateTime::IDLE 674787943
+system.physmem_0.memoryStateTime::REF 2614676000
+system.physmem_0.memoryStateTime::SREF 2808603815500
+system.physmem_0.memoryStateTime::PRE_PDN 23849720592
+system.physmem_0.memoryStateTime::ACT 9995633339
+system.physmem_0.memoryStateTime::ACT_PDN 25273722126
+system.physmem_1.actEnergy 301572180
+system.physmem_1.preEnergy 160289415
+system.physmem_1.readEnergy 675915240
+system.physmem_1.writeEnergy 353816820
+system.physmem_1.refreshEnergy 6255191280.000001
+system.physmem_1.actBackEnergy 5736132870
+system.physmem_1.preBackEnergy 359474400
+system.physmem_1.actPowerDownEnergy 11377384680
+system.physmem_1.prePowerDownEnergy 9560351520
+system.physmem_1.selfRefreshEnergy 675046333020
+system.physmem_1.totalEnergy 709829884665
+system.physmem_1.averagePower 247.240275
+system.physmem_1.totalIdleTime 2857311193722
+system.physmem_1.memoryStateTime::IDLE 664285239
+system.physmem_1.memoryStateTime::REF 2659412000
+system.physmem_1.memoryStateTime::SREF 2807642220500
+system.physmem_1.memoryStateTime::PRE_PDN 24896771092
+system.physmem_1.memoryStateTime::ACT 10199382539
+system.physmem_1.memoryStateTime::ACT_PDN 24950284130
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.nvmem.bytes_read::cpu0.inst 20
+system.realview.nvmem.bytes_read::cpu1.inst 48
+system.realview.nvmem.bytes_read::total 68
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20
+system.realview.nvmem.bytes_inst_read::cpu1.inst 48
+system.realview.nvmem.bytes_inst_read::total 68
+system.realview.nvmem.num_reads::cpu0.inst 5
+system.realview.nvmem.num_reads::cpu1.inst 12
+system.realview.nvmem.num_reads::total 17
+system.realview.nvmem.bw_read::cpu0.inst 7
+system.realview.nvmem.bw_read::cpu1.inst 17
+system.realview.nvmem.bw_read::total 24
+system.realview.nvmem.bw_inst_read::cpu0.inst 7
+system.realview.nvmem.bw_inst_read::cpu1.inst 17
+system.realview.nvmem.bw_inst_read::total 24
+system.realview.nvmem.bw_total::cpu0.inst 7
+system.realview.nvmem.bw_total::cpu1.inst 17
+system.realview.nvmem.bw_total::total 24
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cf0.dma_read_full_pages 0
+system.cf0.dma_read_bytes 1024
+system.cf0.dma_read_txs 1
+system.cf0.dma_write_full_pages 540
+system.cf0.dma_write_bytes 2318336
+system.cf0.dma_write_txs 631
+system.cpu_clk_domain.clock 500
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu0.dtb.walker.walks 7823
+system.cpu0.dtb.walker.walksShort 7823
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1470
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6353
+system.cpu0.dtb.walker.walkWaitTime::samples 7823
+system.cpu0.dtb.walker.walkWaitTime::0 7823 100.00% 100.00%
+system.cpu0.dtb.walker.walkWaitTime::total 7823
+system.cpu0.dtb.walker.walkCompletionTime::samples 6429
+system.cpu0.dtb.walker.walkCompletionTime::mean 12399.906673
+system.cpu0.dtb.walker.walkCompletionTime::gmean 11403.406906
+system.cpu0.dtb.walker.walkCompletionTime::stdev 6039.827624
+system.cpu0.dtb.walker.walkCompletionTime::0-16383 5900 91.77% 91.77%
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767 462 7.19% 98.96%
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151 57 0.89% 99.84%
+system.cpu0.dtb.walker.walkCompletionTime::49152-65535 5 0.08% 99.92%
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.94%
+system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.05% 99.98%
+system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00%
+system.cpu0.dtb.walker.walkCompletionTime::total 6429
+system.cpu0.dtb.walker.walksPending::samples 1181300000
+system.cpu0.dtb.walker.walksPending::0 1181300000 100.00% 100.00%
+system.cpu0.dtb.walker.walksPending::total 1181300000
+system.cpu0.dtb.walker.walkPageSizes::4K 4998 77.74% 77.74%
+system.cpu0.dtb.walker.walkPageSizes::1M 1431 22.26% 100.00%
+system.cpu0.dtb.walker.walkPageSizes::total 6429
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7823
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7823
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6429
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6429
+system.cpu0.dtb.walker.walkRequestOrigin::total 14252
+system.cpu0.dtb.inst_hits 0
+system.cpu0.dtb.inst_misses 0
+system.cpu0.dtb.read_hits 25079832
+system.cpu0.dtb.read_misses 6706
+system.cpu0.dtb.write_hits 18692115
+system.cpu0.dtb.write_misses 1117
+system.cpu0.dtb.flush_tlb 66
+system.cpu0.dtb.flush_tlb_mva 917
+system.cpu0.dtb.flush_tlb_mva_asid 0
+system.cpu0.dtb.flush_tlb_asid 0
+system.cpu0.dtb.flush_entries 3388
+system.cpu0.dtb.align_faults 0
+system.cpu0.dtb.prefetch_faults 1745
+system.cpu0.dtb.domain_faults 0
+system.cpu0.dtb.perms_faults 282
+system.cpu0.dtb.read_accesses 25086538
+system.cpu0.dtb.write_accesses 18693232
+system.cpu0.dtb.inst_accesses 0
+system.cpu0.dtb.hits 43771947
+system.cpu0.dtb.misses 7823
+system.cpu0.dtb.accesses 43779770
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu0.istage2_mmu.stage2_tlb.hits 0
+system.cpu0.istage2_mmu.stage2_tlb.misses 0
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu0.itb.walker.walks 3349
+system.cpu0.itb.walker.walksShort 3349
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050
+system.cpu0.itb.walker.walkWaitTime::samples 3349
+system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00%
+system.cpu0.itb.walker.walkWaitTime::total 3349
+system.cpu0.itb.walker.walkCompletionTime::samples 2333
+system.cpu0.itb.walker.walkCompletionTime::mean 13009.858551
+system.cpu0.itb.walker.walkCompletionTime::gmean 12064.182996
+system.cpu0.itb.walker.walkCompletionTime::stdev 6171.150068
+system.cpu0.itb.walker.walkCompletionTime::0-8191 364 15.60% 15.60%
+system.cpu0.itb.walker.walkCompletionTime::8192-16383 1659 71.11% 86.71%
+system.cpu0.itb.walker.walkCompletionTime::16384-24575 218 9.34% 96.06%
+system.cpu0.itb.walker.walkCompletionTime::24576-32767 44 1.89% 97.94%
+system.cpu0.itb.walker.walkCompletionTime::32768-40959 45 1.93% 99.87%
+system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.91%
+system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96%
+system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00%
+system.cpu0.itb.walker.walkCompletionTime::total 2333
+system.cpu0.itb.walker.walksPending::samples 1180899500
+system.cpu0.itb.walker.walksPending::0 1180899500 100.00% 100.00%
+system.cpu0.itb.walker.walksPending::total 1180899500
+system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18%
+system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00%
+system.cpu0.itb.walker.walkPageSizes::total 2333
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333
+system.cpu0.itb.walker.walkRequestOrigin::total 5682
+system.cpu0.itb.inst_hits 118651077
+system.cpu0.itb.inst_misses 3349
+system.cpu0.itb.read_hits 0
+system.cpu0.itb.read_misses 0
+system.cpu0.itb.write_hits 0
+system.cpu0.itb.write_misses 0
+system.cpu0.itb.flush_tlb 66
+system.cpu0.itb.flush_tlb_mva 917
+system.cpu0.itb.flush_tlb_mva_asid 0
+system.cpu0.itb.flush_tlb_asid 0
+system.cpu0.itb.flush_entries 2087
+system.cpu0.itb.align_faults 0
+system.cpu0.itb.prefetch_faults 0
+system.cpu0.itb.domain_faults 0
+system.cpu0.itb.perms_faults 0
+system.cpu0.itb.read_accesses 0
+system.cpu0.itb.write_accesses 0
+system.cpu0.itb.inst_accesses 118654426
+system.cpu0.itb.hits 118651077
+system.cpu0.itb.misses 3349
+system.cpu0.itb.accesses 118654426
+system.cpu0.numPwrStateTransitions 3724
+system.cpu0.pwrStateClkGateDist::samples 1862
+system.cpu0.pwrStateClkGateDist::mean 1466914321.975295
+system.cpu0.pwrStateClkGateDist::stdev 23730695905.598595
+system.cpu0.pwrStateClkGateDist::underflows 1082 58.11% 58.11%
+system.cpu0.pwrStateClkGateDist::1000-5e+10 775 41.62% 99.73%
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79%
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00%
+system.cpu0.pwrStateClkGateDist::min_value 501
+system.cpu0.pwrStateClkGateDist::max_value 499964525704
+system.cpu0.pwrStateClkGateDist::total 1862
+system.cpu0.pwrStateResidencyTicks::ON 139617887982
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731394467518
+system.cpu0.numCycles 5742024711
+system.cpu0.numWorkItemsStarted 0
+system.cpu0.numWorkItemsCompleted 0
+system.cpu0.kern.inst.arm 0
+system.cpu0.kern.inst.quiesce 1862
+system.cpu0.committedInsts 114989095
+system.cpu0.committedOps 138953395
+system.cpu0.num_int_alu_accesses 122990229
+system.cpu0.num_fp_alu_accesses 9755
+system.cpu0.num_func_calls 12658538
+system.cpu0.num_conditional_control_insts 15642727
+system.cpu0.num_int_insts 122990229
+system.cpu0.num_fp_insts 9755
+system.cpu0.num_int_register_reads 226428267
+system.cpu0.num_int_register_writes 85458801
+system.cpu0.num_fp_register_reads 7495
+system.cpu0.num_fp_register_writes 2264
+system.cpu0.num_cc_register_reads 503412465
+system.cpu0.num_cc_register_writes 52088929
+system.cpu0.num_mem_refs 44904529
+system.cpu0.num_load_insts 25328869
+system.cpu0.num_store_insts 19575660
+system.cpu0.num_idle_cycles 5462788935.034097
+system.cpu0.num_busy_cycles 279235775.965903
+system.cpu0.not_idle_fraction 0.048630
+system.cpu0.idle_fraction 0.951370
+system.cpu0.Branches 29038037
+system.cpu0.op_class::No_OpClass 2273 0.00% 0.00%
+system.cpu0.op_class::IntAlu 97689121 68.45% 68.45%
+system.cpu0.op_class::IntMult 108461 0.08% 68.53%
+system.cpu0.op_class::IntDiv 0 0.00% 68.53%
+system.cpu0.op_class::FloatAdd 0 0.00% 68.53%
+system.cpu0.op_class::FloatCmp 0 0.00% 68.53%
+system.cpu0.op_class::FloatCvt 0 0.00% 68.53%
+system.cpu0.op_class::FloatMult 0 0.00% 68.53%
+system.cpu0.op_class::FloatMultAcc 0 0.00% 68.53%
+system.cpu0.op_class::FloatDiv 0 0.00% 68.53%
+system.cpu0.op_class::FloatMisc 0 0.00% 68.53%
+system.cpu0.op_class::FloatSqrt 0 0.00% 68.53%
+system.cpu0.op_class::SimdAdd 0 0.00% 68.53%
+system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53%
+system.cpu0.op_class::SimdAlu 0 0.00% 68.53%
+system.cpu0.op_class::SimdCmp 0 0.00% 68.53%
+system.cpu0.op_class::SimdCvt 0 0.00% 68.53%
+system.cpu0.op_class::SimdMisc 0 0.00% 68.53%
+system.cpu0.op_class::SimdMult 0 0.00% 68.53%
+system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53%
+system.cpu0.op_class::SimdShift 0 0.00% 68.53%
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53%
+system.cpu0.op_class::SimdSqrt 0 0.00% 68.53%
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53%
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53%
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53%
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53%
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53%
+system.cpu0.op_class::SimdFloatMisc 7991 0.01% 68.53%
+system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53%
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53%
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53%
+system.cpu0.op_class::MemRead 25326613 17.75% 86.28%
+system.cpu0.op_class::MemWrite 19568165 13.71% 99.99%
+system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99%
+system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00%
+system.cpu0.op_class::IprAccess 0 0.00% 100.00%
+system.cpu0.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu0.op_class::total 142712375
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu0.dcache.tags.replacements 689805
+system.cpu0.dcache.tags.tagsinuse 498.372694
+system.cpu0.dcache.tags.total_refs 42903858
+system.cpu0.dcache.tags.sampled_refs 690317
+system.cpu0.dcache.tags.avg_refs 62.150951
+system.cpu0.dcache.tags.warmup_cycle 1207348000
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.372694
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.973384
+system.cpu0.dcache.tags.occ_percent::total 0.973384
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 95
+system.cpu0.dcache.tags.occ_task_id_percent::1024 1
+system.cpu0.dcache.tags.tag_accesses 88178135
+system.cpu0.dcache.tags.data_accesses 88178135
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu0.dcache.ReadReq_hits::cpu0.data 23822310
+system.cpu0.dcache.ReadReq_hits::total 23822310
+system.cpu0.dcache.WriteReq_hits::cpu0.data 17962514
+system.cpu0.dcache.WriteReq_hits::total 17962514
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318853
+system.cpu0.dcache.SoftPFReq_hits::total 318853
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364520
+system.cpu0.dcache.LoadLockedReq_hits::total 364520
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361475
+system.cpu0.dcache.StoreCondReq_hits::total 361475
+system.cpu0.dcache.demand_hits::cpu0.data 41784824
+system.cpu0.dcache.demand_hits::total 41784824
+system.cpu0.dcache.overall_hits::cpu0.data 42103677
+system.cpu0.dcache.overall_hits::total 42103677
+system.cpu0.dcache.ReadReq_misses::cpu0.data 394535
+system.cpu0.dcache.ReadReq_misses::total 394535
+system.cpu0.dcache.WriteReq_misses::cpu0.data 324202
+system.cpu0.dcache.WriteReq_misses::total 324202
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 126994
+system.cpu0.dcache.SoftPFReq_misses::total 126994
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21422
+system.cpu0.dcache.LoadLockedReq_misses::total 21422
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19571
+system.cpu0.dcache.StoreCondReq_misses::total 19571
+system.cpu0.dcache.demand_misses::cpu0.data 718737
+system.cpu0.dcache.demand_misses::total 718737
+system.cpu0.dcache.overall_misses::cpu0.data 845731
+system.cpu0.dcache.overall_misses::total 845731
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5513220000
+system.cpu0.dcache.ReadReq_miss_latency::total 5513220000
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6311049000
+system.cpu0.dcache.WriteReq_miss_latency::total 6311049000
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 337488500
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 337488500
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 459190500
+system.cpu0.dcache.StoreCondReq_miss_latency::total 459190500
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1100000
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1100000
+system.cpu0.dcache.demand_miss_latency::cpu0.data 11824269000
+system.cpu0.dcache.demand_miss_latency::total 11824269000
+system.cpu0.dcache.overall_miss_latency::cpu0.data 11824269000
+system.cpu0.dcache.overall_miss_latency::total 11824269000
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 24216845
+system.cpu0.dcache.ReadReq_accesses::total 24216845
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 18286716
+system.cpu0.dcache.WriteReq_accesses::total 18286716
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 445847
+system.cpu0.dcache.SoftPFReq_accesses::total 445847
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 385942
+system.cpu0.dcache.LoadLockedReq_accesses::total 385942
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381046
+system.cpu0.dcache.StoreCondReq_accesses::total 381046
+system.cpu0.dcache.demand_accesses::cpu0.data 42503561
+system.cpu0.dcache.demand_accesses::total 42503561
+system.cpu0.dcache.overall_accesses::cpu0.data 42949408
+system.cpu0.dcache.overall_accesses::total 42949408
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016292
+system.cpu0.dcache.ReadReq_miss_rate::total 0.016292
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017729
+system.cpu0.dcache.WriteReq_miss_rate::total 0.017729
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.284838
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.284838
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055506
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055506
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051361
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051361
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016910
+system.cpu0.dcache.demand_miss_rate::total 0.016910
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019691
+system.cpu0.dcache.overall_miss_rate::total 0.019691
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13973.969356
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13973.969356
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19466.409831
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 19466.409831
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15754.294650
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15754.294650
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23462.802105
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23462.802105
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16451.454426
+system.cpu0.dcache.demand_avg_miss_latency::total 16451.454426
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13981.122839
+system.cpu0.dcache.overall_avg_miss_latency::total 13981.122839
+system.cpu0.dcache.blocked_cycles::no_mshrs 0
+system.cpu0.dcache.blocked_cycles::no_targets 0
+system.cpu0.dcache.blocked::no_mshrs 0
+system.cpu0.dcache.blocked::no_targets 0
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan
+system.cpu0.dcache.writebacks::writebacks 689805
+system.cpu0.dcache.writebacks::total 689805
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25204
+system.cpu0.dcache.ReadReq_mshr_hits::total 25204
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15035
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15035
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 25204
+system.cpu0.dcache.demand_mshr_hits::total 25204
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 25204
+system.cpu0.dcache.overall_mshr_hits::total 25204
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369331
+system.cpu0.dcache.ReadReq_mshr_misses::total 369331
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324202
+system.cpu0.dcache.WriteReq_mshr_misses::total 324202
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100006
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 100006
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6387
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6387
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19571
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 19571
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 693533
+system.cpu0.dcache.demand_mshr_misses::total 693533
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 793539
+system.cpu0.dcache.overall_mshr_misses::total 793539
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31749
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31749
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28437
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28437
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60186
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60186
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4735470000
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4735470000
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5986847000
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5986847000
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1652052500
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1652052500
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101426000
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101426000
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 439651500
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 439651500
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1068000
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1068000
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10722317000
+system.cpu0.dcache.demand_mshr_miss_latency::total 10722317000
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12374369500
+system.cpu0.dcache.overall_mshr_miss_latency::total 12374369500
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628151500
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628151500
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628151500
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628151500
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015251
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015251
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017729
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017729
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224306
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224306
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016549
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016549
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051361
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051361
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016317
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.016317
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018476
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.018476
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12821.750679
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12821.750679
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18466.409831
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18466.409831
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16519.533828
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16519.533828
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15880.068890
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15880.068890
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22464.437177
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22464.437177
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15460.427983
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15460.427983
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15593.902127
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15593.902127
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208767.252512
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208767.252512
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110127.795501
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110127.795501
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu0.icache.tags.replacements 1095179
+system.cpu0.icache.tags.tagsinuse 511.436914
+system.cpu0.icache.tags.total_refs 117555377
+system.cpu0.icache.tags.sampled_refs 1095691
+system.cpu0.icache.tags.avg_refs 107.288804
+system.cpu0.icache.tags.warmup_cycle 14178985000
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436914
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998900
+system.cpu0.icache.tags.occ_percent::total 0.998900
+system.cpu0.icache.tags.occ_task_id_blocks::1024 512
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 85
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 212
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 215
+system.cpu0.icache.tags.occ_task_id_percent::1024 1
+system.cpu0.icache.tags.tag_accesses 238397854
+system.cpu0.icache.tags.data_accesses 238397854
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu0.icache.ReadReq_hits::cpu0.inst 117555377
+system.cpu0.icache.ReadReq_hits::total 117555377
+system.cpu0.icache.demand_hits::cpu0.inst 117555377
+system.cpu0.icache.demand_hits::total 117555377
+system.cpu0.icache.overall_hits::cpu0.inst 117555377
+system.cpu0.icache.overall_hits::total 117555377
+system.cpu0.icache.ReadReq_misses::cpu0.inst 1095700
+system.cpu0.icache.ReadReq_misses::total 1095700
+system.cpu0.icache.demand_misses::cpu0.inst 1095700
+system.cpu0.icache.demand_misses::total 1095700
+system.cpu0.icache.overall_misses::cpu0.inst 1095700
+system.cpu0.icache.overall_misses::total 1095700
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11843020000
+system.cpu0.icache.ReadReq_miss_latency::total 11843020000
+system.cpu0.icache.demand_miss_latency::cpu0.inst 11843020000
+system.cpu0.icache.demand_miss_latency::total 11843020000
+system.cpu0.icache.overall_miss_latency::cpu0.inst 11843020000
+system.cpu0.icache.overall_miss_latency::total 11843020000
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 118651077
+system.cpu0.icache.ReadReq_accesses::total 118651077
+system.cpu0.icache.demand_accesses::cpu0.inst 118651077
+system.cpu0.icache.demand_accesses::total 118651077
+system.cpu0.icache.overall_accesses::cpu0.inst 118651077
+system.cpu0.icache.overall_accesses::total 118651077
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009235
+system.cpu0.icache.ReadReq_miss_rate::total 0.009235
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009235
+system.cpu0.icache.demand_miss_rate::total 0.009235
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009235
+system.cpu0.icache.overall_miss_rate::total 0.009235
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10808.633750
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10808.633750
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10808.633750
+system.cpu0.icache.demand_avg_miss_latency::total 10808.633750
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10808.633750
+system.cpu0.icache.overall_avg_miss_latency::total 10808.633750
+system.cpu0.icache.blocked_cycles::no_mshrs 0
+system.cpu0.icache.blocked_cycles::no_targets 0
+system.cpu0.icache.blocked::no_mshrs 0
+system.cpu0.icache.blocked::no_targets 0
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
+system.cpu0.icache.avg_blocked_cycles::no_targets nan
+system.cpu0.icache.writebacks::writebacks 1095179
+system.cpu0.icache.writebacks::total 1095179
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1095700
+system.cpu0.icache.ReadReq_mshr_misses::total 1095700
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 1095700
+system.cpu0.icache.demand_mshr_misses::total 1095700
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 1095700
+system.cpu0.icache.overall_mshr_misses::total 1095700
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022
+system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022
+system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11295170000
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 11295170000
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11295170000
+system.cpu0.icache.demand_mshr_miss_latency::total 11295170000
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11295170000
+system.cpu0.icache.overall_mshr_miss_latency::total 11295170000
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 863305500
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 863305500
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 863305500
+system.cpu0.icache.overall_mshr_uncacheable_latency::total 863305500
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009235
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009235
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009235
+system.cpu0.icache.demand_mshr_miss_rate::total 0.009235
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009235
+system.cpu0.icache.overall_mshr_miss_rate::total 0.009235
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10308.633750
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10308.633750
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10308.633750
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10308.633750
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10308.633750
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10308.633750
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu0.l2cache.prefetcher.num_hwpf_issued 1843113
+system.cpu0.l2cache.prefetcher.pfIdentified 1843139
+system.cpu0.l2cache.prefetcher.pfBufferHit 23
+system.cpu0.l2cache.prefetcher.pfInCache 0
+system.cpu0.l2cache.prefetcher.pfRemovedFull 0
+system.cpu0.l2cache.prefetcher.pfSpanPage 237133
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu0.l2cache.tags.replacements 260188
+system.cpu0.l2cache.tags.tagsinuse 15622.540020
+system.cpu0.l2cache.tags.total_refs 1673934
+system.cpu0.l2cache.tags.sampled_refs 275818
+system.cpu0.l2cache.tags.avg_refs 6.068980
+system.cpu0.l2cache.tags.warmup_cycle 0
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14428.533255
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.383166
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.133380
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1192.490219
+system.cpu0.l2cache.tags.occ_percent::writebacks 0.880648
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000084
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.072784
+system.cpu0.l2cache.tags.occ_percent::total 0.953524
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022 319
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15303
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 5
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 19
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 135
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 160
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 180
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 824
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6032
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6210
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2057
+system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.019470
+system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488
+system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.934021
+system.cpu0.l2cache.tags.tag_accesses 60936102
+system.cpu0.l2cache.tags.data_accesses 60936102
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9959
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4459
+system.cpu0.l2cache.ReadReq_hits::total 14418
+system.cpu0.l2cache.WritebackDirty_hits::writebacks 473817
+system.cpu0.l2cache.WritebackDirty_hits::total 473817
+system.cpu0.l2cache.WritebackClean_hits::writebacks 1283425
+system.cpu0.l2cache.WritebackClean_hits::total 1283425
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data 226628
+system.cpu0.l2cache.ReadExReq_hits::total 226628
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1033356
+system.cpu0.l2cache.ReadCleanReq_hits::total 1033356
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 374606
+system.cpu0.l2cache.ReadSharedReq_hits::total 374606
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9959
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4459
+system.cpu0.l2cache.demand_hits::cpu0.inst 1033356
+system.cpu0.l2cache.demand_hits::cpu0.data 601234
+system.cpu0.l2cache.demand_hits::total 1649008
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9959
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4459
+system.cpu0.l2cache.overall_hits::cpu0.inst 1033356
+system.cpu0.l2cache.overall_hits::cpu0.data 601234
+system.cpu0.l2cache.overall_hits::total 1649008
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 299
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 184
+system.cpu0.l2cache.ReadReq_misses::total 483
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54615
+system.cpu0.l2cache.UpgradeReq_misses::total 54615
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19569
+system.cpu0.l2cache.SCUpgradeReq_misses::total 19569
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data 42959
+system.cpu0.l2cache.ReadExReq_misses::total 42959
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62344
+system.cpu0.l2cache.ReadCleanReq_misses::total 62344
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101118
+system.cpu0.l2cache.ReadSharedReq_misses::total 101118
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 299
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker 184
+system.cpu0.l2cache.demand_misses::cpu0.inst 62344
+system.cpu0.l2cache.demand_misses::cpu0.data 144077
+system.cpu0.l2cache.demand_misses::total 206904
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 299
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker 184
+system.cpu0.l2cache.overall_misses::cpu0.inst 62344
+system.cpu0.l2cache.overall_misses::cpu0.data 144077
+system.cpu0.l2cache.overall_misses::total 206904
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7929000
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4346000
+system.cpu0.l2cache.ReadReq_miss_latency::total 12275000
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 29867500
+system.cpu0.l2cache.UpgradeReq_miss_latency::total 29867500
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9063000
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9063000
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1019499
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1019499
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2761074000
+system.cpu0.l2cache.ReadExReq_miss_latency::total 2761074000
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3428129000
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3428129000
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3333472000
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3333472000
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7929000
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4346000
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3428129000
+system.cpu0.l2cache.demand_miss_latency::cpu0.data 6094546000
+system.cpu0.l2cache.demand_miss_latency::total 9534950000
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7929000
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4346000
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3428129000
+system.cpu0.l2cache.overall_miss_latency::cpu0.data 6094546000
+system.cpu0.l2cache.overall_miss_latency::total 9534950000
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10258
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4643
+system.cpu0.l2cache.ReadReq_accesses::total 14901
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks 473817
+system.cpu0.l2cache.WritebackDirty_accesses::total 473817
+system.cpu0.l2cache.WritebackClean_accesses::writebacks 1283425
+system.cpu0.l2cache.WritebackClean_accesses::total 1283425
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54615
+system.cpu0.l2cache.UpgradeReq_accesses::total 54615
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19569
+system.cpu0.l2cache.SCUpgradeReq_accesses::total 19569
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269587
+system.cpu0.l2cache.ReadExReq_accesses::total 269587
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1095700
+system.cpu0.l2cache.ReadCleanReq_accesses::total 1095700
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 475724
+system.cpu0.l2cache.ReadSharedReq_accesses::total 475724
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10258
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4643
+system.cpu0.l2cache.demand_accesses::cpu0.inst 1095700
+system.cpu0.l2cache.demand_accesses::cpu0.data 745311
+system.cpu0.l2cache.demand_accesses::total 1855912
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10258
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4643
+system.cpu0.l2cache.overall_accesses::cpu0.inst 1095700
+system.cpu0.l2cache.overall_accesses::cpu0.data 745311
+system.cpu0.l2cache.overall_accesses::total 1855912
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.029148
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.039630
+system.cpu0.l2cache.ReadReq_miss_rate::total 0.032414
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1
+system.cpu0.l2cache.UpgradeReq_miss_rate::total 1
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1
+system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1
+system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.159351
+system.cpu0.l2cache.ReadExReq_miss_rate::total 0.159351
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056899
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056899
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.212556
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.212556
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.029148
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.039630
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056899
+system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.193311
+system.cpu0.l2cache.demand_miss_rate::total 0.111484
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.029148
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.039630
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056899
+system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.193311
+system.cpu0.l2cache.overall_miss_rate::total 0.111484
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26518.394649
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23619.565217
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25414.078675
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 546.873570
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 546.873570
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 463.130461
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 463.130461
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 509749.500000
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 509749.500000
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64272.306152
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64272.306152
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 54987.312332
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 54987.312332
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32966.158350
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32966.158350
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26518.394649
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23619.565217
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 54987.312332
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42300.617031
+system.cpu0.l2cache.demand_avg_miss_latency::total 46083.932645
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26518.394649
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23619.565217
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 54987.312332
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42300.617031
+system.cpu0.l2cache.overall_avg_miss_latency::total 46083.932645
+system.cpu0.l2cache.blocked_cycles::no_mshrs 0
+system.cpu0.l2cache.blocked_cycles::no_targets 0
+system.cpu0.l2cache.blocked::no_mshrs 0
+system.cpu0.l2cache.blocked::no_targets 0
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu0.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu0.l2cache.unused_prefetches 10455
+system.cpu0.l2cache.writebacks::writebacks 227367
+system.cpu0.l2cache.writebacks::total 227367
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1570
+system.cpu0.l2cache.ReadExReq_mshr_hits::total 1570
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 31
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 31
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1601
+system.cpu0.l2cache.demand_mshr_hits::total 1601
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1601
+system.cpu0.l2cache.overall_mshr_hits::total 1601
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 299
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 184
+system.cpu0.l2cache.ReadReq_mshr_misses::total 483
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 261615
+system.cpu0.l2cache.HardPFReq_mshr_misses::total 261615
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 54615
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total 54615
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19569
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19569
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41389
+system.cpu0.l2cache.ReadExReq_mshr_misses::total 41389
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62344
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62344
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101087
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101087
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 299
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 184
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62344
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142476
+system.cpu0.l2cache.demand_mshr_misses::total 205303
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 299
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 184
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62344
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142476
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 261615
+system.cpu0.l2cache.overall_mshr_misses::total 466918
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31749
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40771
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28437
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28437
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60186
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69208
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 6135000
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3242000
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 9377000
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16780241511
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16780241511
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 936352000
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 936352000
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 293047000
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 293047000
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 827499
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 827499
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2230059000
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2230059000
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3054065000
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3054065000
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2721246000
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2721246000
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 6135000
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3242000
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3054065000
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4951305000
+system.cpu0.l2cache.demand_mshr_miss_latency::total 8014747000
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 6135000
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3242000
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3054065000
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4951305000
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16780241511
+system.cpu0.l2cache.overall_mshr_miss_latency::total 24794988511
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 795640500
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6373749000
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7169389500
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 795640500
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6373749000
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7169389500
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.029148
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.039630
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.032414
+system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf
+system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153527
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153527
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056899
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056899
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.212491
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.212491
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.029148
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.039630
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056899
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191163
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110621
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.029148
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.039630
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056899
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191163
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.251584
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20518.394649
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17619.565217
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 19414.078675
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64140.976286
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64140.976286
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17144.593976
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17144.593976
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14975.062599
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14975.062599
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 413749.500000
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 413749.500000
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53880.475489
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53880.475489
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 48987.312332
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 48987.312332
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26919.841325
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26919.841325
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20518.394649
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17619.565217
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 48987.312332
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34751.852944
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39038.625836
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20518.394649
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17619.565217
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 48987.312332
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34751.852944
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64140.976286
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53103.518200
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200754.322971
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175845.318977
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105900.857342
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103591.918564
+system.cpu0.toL2Bus.snoop_filter.tot_requests 3711991
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1871014
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27755
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 210749
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 209099
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1650
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu0.toL2Bus.trans_dist::ReadReq 61374
+system.cpu0.toL2Bus.trans_dist::ReadResp 1680590
+system.cpu0.toL2Bus.trans_dist::WriteReq 28437
+system.cpu0.toL2Bus.trans_dist::WriteResp 28437
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 701494
+system.cpu0.toL2Bus.trans_dist::WritebackClean 1311167
+system.cpu0.toL2Bus.trans_dist::CleanEvict 80057
+system.cpu0.toL2Bus.trans_dist::HardPFReq 307806
+system.cpu0.toL2Bus.trans_dist::HardPFResp 1
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 87002
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41728
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 111716
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 47
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 77
+system.cpu0.toL2Bus.trans_dist::ReadExReq 288659
+system.cpu0.toL2Bus.trans_dist::ReadExResp 285181
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1095700
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 562192
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 3242
+system.cpu0.toL2Bus.trans_dist::InvalidateResp 12
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3304623
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2550205
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11042
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24434
+system.cpu0.toL2Bus.pkt_count::total 5890304
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140252344
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96102318
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18572
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 41032
+system.cpu0.toL2Bus.pkt_size::total 236414266
+system.cpu0.toL2Bus.snoops 885649
+system.cpu0.toL2Bus.snoopTraffic 18655284
+system.cpu0.toL2Bus.snoop_fanout::samples 2783921
+system.cpu0.toL2Bus.snoop_fanout::mean 0.090513
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.288974
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu0.toL2Bus.snoop_fanout::0 2533590 91.01% 91.01%
+system.cpu0.toL2Bus.snoop_fanout::1 248681 8.93% 99.94%
+system.cpu0.toL2Bus.snoop_fanout::2 1650 0.06% 100.00%
+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu0.toL2Bus.snoop_fanout::min_value 0
+system.cpu0.toL2Bus.snoop_fanout::max_value 2
+system.cpu0.toL2Bus.snoop_fanout::total 2783921
+system.cpu0.toL2Bus.reqLayer0.occupancy 3694185498
+system.cpu0.toL2Bus.reqLayer0.utilization 0.1
+system.cpu0.toL2Bus.snoopLayer0.occupancy 114034527
+system.cpu0.toL2Bus.snoopLayer0.utilization 0.0
+system.cpu0.toL2Bus.respLayer0.occupancy 1652572000
+system.cpu0.toL2Bus.respLayer0.utilization 0.1
+system.cpu0.toL2Bus.respLayer1.occupancy 1201064489
+system.cpu0.toL2Bus.respLayer1.utilization 0.0
+system.cpu0.toL2Bus.respLayer2.occupancy 6399000
+system.cpu0.toL2Bus.respLayer2.utilization 0.0
+system.cpu0.toL2Bus.respLayer3.occupancy 14180491
+system.cpu0.toL2Bus.respLayer3.utilization 0.0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu1.dtb.walker.walks 3373
+system.cpu1.dtb.walker.walksShort 3373
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 671
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2702
+system.cpu1.dtb.walker.walkWaitTime::samples 3373
+system.cpu1.dtb.walker.walkWaitTime::0 3373 100.00% 100.00%
+system.cpu1.dtb.walker.walkWaitTime::total 3373
+system.cpu1.dtb.walker.walkCompletionTime::samples 2603
+system.cpu1.dtb.walker.walkCompletionTime::mean 12478.486362
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11546.344109
+system.cpu1.dtb.walker.walkCompletionTime::stdev 5610.903902
+system.cpu1.dtb.walker.walkCompletionTime::0-8191 607 23.32% 23.32%
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1682 64.62% 87.94%
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575 233 8.95% 96.89%
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767 66 2.54% 99.42%
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959 9 0.35% 99.77%
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.88%
+system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.08% 99.96%
+system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00%
+system.cpu1.dtb.walker.walkCompletionTime::total 2603
+system.cpu1.dtb.walker.walksPending::samples -1937787828
+system.cpu1.dtb.walker.walksPending::0 -1937787828 100.00% 100.00%
+system.cpu1.dtb.walker.walksPending::total -1937787828
+system.cpu1.dtb.walker.walkPageSizes::4K 1940 74.53% 74.53%
+system.cpu1.dtb.walker.walkPageSizes::1M 663 25.47% 100.00%
+system.cpu1.dtb.walker.walkPageSizes::total 2603
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3373
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3373
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2603
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2603
+system.cpu1.dtb.walker.walkRequestOrigin::total 5976
+system.cpu1.dtb.inst_hits 0
+system.cpu1.dtb.inst_misses 0
+system.cpu1.dtb.read_hits 3953610
+system.cpu1.dtb.read_misses 2858
+system.cpu1.dtb.write_hits 3430069
+system.cpu1.dtb.write_misses 515
+system.cpu1.dtb.flush_tlb 66
+system.cpu1.dtb.flush_tlb_mva 917
+system.cpu1.dtb.flush_tlb_mva_asid 0
+system.cpu1.dtb.flush_tlb_asid 0
+system.cpu1.dtb.flush_entries 1978
+system.cpu1.dtb.align_faults 0
+system.cpu1.dtb.prefetch_faults 342
+system.cpu1.dtb.domain_faults 0
+system.cpu1.dtb.perms_faults 163
+system.cpu1.dtb.read_accesses 3956468
+system.cpu1.dtb.write_accesses 3430584
+system.cpu1.dtb.inst_accesses 0
+system.cpu1.dtb.hits 7383679
+system.cpu1.dtb.misses 3373
+system.cpu1.dtb.accesses 7387052
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu1.istage2_mmu.stage2_tlb.hits 0
+system.cpu1.istage2_mmu.stage2_tlb.misses 0
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu1.itb.walker.walks 1746
+system.cpu1.itb.walker.walksShort 1746
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578
+system.cpu1.itb.walker.walkWaitTime::samples 1746
+system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00%
+system.cpu1.itb.walker.walkWaitTime::total 1746
+system.cpu1.itb.walker.walkCompletionTime::samples 1107
+system.cpu1.itb.walker.walkCompletionTime::mean 12838.301716
+system.cpu1.itb.walker.walkCompletionTime::gmean 11944.354322
+system.cpu1.itb.walker.walkCompletionTime::stdev 5752.116994
+system.cpu1.itb.walker.walkCompletionTime::4096-8191 161 14.54% 14.54%
+system.cpu1.itb.walker.walkCompletionTime::8192-12287 638 57.63% 72.18%
+system.cpu1.itb.walker.walkCompletionTime::12288-16383 160 14.45% 86.63%
+system.cpu1.itb.walker.walkCompletionTime::16384-20479 48 4.34% 90.97%
+system.cpu1.itb.walker.walkCompletionTime::20480-24575 40 3.61% 94.58%
+system.cpu1.itb.walker.walkCompletionTime::24576-28671 29 2.62% 97.20%
+system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.45% 98.64%
+system.cpu1.itb.walker.walkCompletionTime::32768-36863 6 0.54% 99.19%
+system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.46%
+system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82%
+system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 100.00%
+system.cpu1.itb.walker.walkCompletionTime::total 1107
+system.cpu1.itb.walker.walksPending::samples -1938367828
+system.cpu1.itb.walker.walksPending::0 -1938367828 100.00% 100.00%
+system.cpu1.itb.walker.walksPending::total -1938367828
+system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82%
+system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00%
+system.cpu1.itb.walker.walkPageSizes::total 1107
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107
+system.cpu1.itb.walker.walkRequestOrigin::total 2853
+system.cpu1.itb.inst_hits 16665543
+system.cpu1.itb.inst_misses 1746
+system.cpu1.itb.read_hits 0
+system.cpu1.itb.read_misses 0
+system.cpu1.itb.write_hits 0
+system.cpu1.itb.write_misses 0
+system.cpu1.itb.flush_tlb 66
+system.cpu1.itb.flush_tlb_mva 917
+system.cpu1.itb.flush_tlb_mva_asid 0
+system.cpu1.itb.flush_tlb_asid 0
+system.cpu1.itb.flush_entries 1084
+system.cpu1.itb.align_faults 0
+system.cpu1.itb.prefetch_faults 0
+system.cpu1.itb.domain_faults 0
+system.cpu1.itb.perms_faults 0
+system.cpu1.itb.read_accesses 0
+system.cpu1.itb.write_accesses 0
+system.cpu1.itb.inst_accesses 16667289
+system.cpu1.itb.hits 16665543
+system.cpu1.itb.misses 1746
+system.cpu1.itb.accesses 16667289
+system.cpu1.numPwrStateTransitions 5457
+system.cpu1.pwrStateClkGateDist::samples 2729
+system.cpu1.pwrStateClkGateDist::mean 1042331816.440454
+system.cpu1.pwrStateClkGateDist::stdev 25865412745.750839
+system.cpu1.pwrStateClkGateDist::underflows 1950 71.45% 71.45%
+system.cpu1.pwrStateClkGateDist::1000-5e+10 773 28.33% 99.78%
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85%
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89%
+system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93%
+system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96%
+system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00%
+system.cpu1.pwrStateClkGateDist::min_value 501
+system.cpu1.pwrStateClkGateDist::max_value 929980418584
+system.cpu1.pwrStateClkGateDist::total 2729
+system.cpu1.pwrStateResidencyTicks::ON 26488828434
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844523527066
+system.cpu1.numCycles 5741091540
+system.cpu1.numWorkItemsStarted 0
+system.cpu1.numWorkItemsCompleted 0
+system.cpu1.kern.inst.arm 0
+system.cpu1.kern.inst.quiesce 2729
+system.cpu1.committedInsts 16310250
+system.cpu1.committedOps 19861699
+system.cpu1.num_int_alu_accesses 17893275
+system.cpu1.num_fp_alu_accesses 1792
+system.cpu1.num_func_calls 1028889
+system.cpu1.num_conditional_control_insts 1844355
+system.cpu1.num_int_insts 17893275
+system.cpu1.num_fp_insts 1792
+system.cpu1.num_int_register_reads 32455374
+system.cpu1.num_int_register_writes 12541370
+system.cpu1.num_fp_register_reads 1276
+system.cpu1.num_fp_register_writes 516
+system.cpu1.num_cc_register_reads 72563559
+system.cpu1.num_cc_register_writes 6509295
+system.cpu1.num_mem_refs 7617254
+system.cpu1.num_load_insts 4064765
+system.cpu1.num_store_insts 3552489
+system.cpu1.num_idle_cycles 5688122492.849936
+system.cpu1.num_busy_cycles 52969047.150064
+system.cpu1.not_idle_fraction 0.009226
+system.cpu1.idle_fraction 0.990774
+system.cpu1.Branches 2953035
+system.cpu1.op_class::No_OpClass 66 0.00% 0.00%
+system.cpu1.op_class::IntAlu 12565444 62.17% 62.17%
+system.cpu1.op_class::IntMult 26315 0.13% 62.30%
+system.cpu1.op_class::IntDiv 0 0.00% 62.30%
+system.cpu1.op_class::FloatAdd 0 0.00% 62.30%
+system.cpu1.op_class::FloatCmp 0 0.00% 62.30%
+system.cpu1.op_class::FloatCvt 0 0.00% 62.30%
+system.cpu1.op_class::FloatMult 0 0.00% 62.30%
+system.cpu1.op_class::FloatMultAcc 0 0.00% 62.30%
+system.cpu1.op_class::FloatDiv 0 0.00% 62.30%
+system.cpu1.op_class::FloatMisc 0 0.00% 62.30%
+system.cpu1.op_class::FloatSqrt 0 0.00% 62.30%
+system.cpu1.op_class::SimdAdd 0 0.00% 62.30%
+system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30%
+system.cpu1.op_class::SimdAlu 0 0.00% 62.30%
+system.cpu1.op_class::SimdCmp 0 0.00% 62.30%
+system.cpu1.op_class::SimdCvt 0 0.00% 62.30%
+system.cpu1.op_class::SimdMisc 0 0.00% 62.30%
+system.cpu1.op_class::SimdMult 0 0.00% 62.30%
+system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30%
+system.cpu1.op_class::SimdShift 0 0.00% 62.30%
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30%
+system.cpu1.op_class::SimdSqrt 0 0.00% 62.30%
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30%
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30%
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30%
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30%
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30%
+system.cpu1.op_class::SimdFloatMisc 3279 0.02% 62.31%
+system.cpu1.op_class::SimdFloatMult 0 0.00% 62.31%
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.31%
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.31%
+system.cpu1.op_class::MemRead 4064249 20.11% 82.42%
+system.cpu1.op_class::MemWrite 3551213 17.57% 99.99%
+system.cpu1.op_class::FloatMemRead 516 0.00% 99.99%
+system.cpu1.op_class::FloatMemWrite 1276 0.01% 100.00%
+system.cpu1.op_class::IprAccess 0 0.00% 100.00%
+system.cpu1.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu1.op_class::total 20212358
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu1.dcache.tags.replacements 187431
+system.cpu1.dcache.tags.tagsinuse 470.676841
+system.cpu1.dcache.tags.total_refs 7112504
+system.cpu1.dcache.tags.sampled_refs 187790
+system.cpu1.dcache.tags.avg_refs 37.874775
+system.cpu1.dcache.tags.warmup_cycle 128171950500
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.676841
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.919291
+system.cpu1.dcache.tags.occ_percent::total 0.919291
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 359
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 326
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 33
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172
+system.cpu1.dcache.tags.tag_accesses 14986603
+system.cpu1.dcache.tags.data_accesses 14986603
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu1.dcache.ReadReq_hits::cpu1.data 3641806
+system.cpu1.dcache.ReadReq_hits::total 3641806
+system.cpu1.dcache.WriteReq_hits::cpu1.data 3241391
+system.cpu1.dcache.WriteReq_hits::total 3241391
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49016
+system.cpu1.dcache.SoftPFReq_hits::total 49016
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78939
+system.cpu1.dcache.LoadLockedReq_hits::total 78939
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70838
+system.cpu1.dcache.StoreCondReq_hits::total 70838
+system.cpu1.dcache.demand_hits::cpu1.data 6883197
+system.cpu1.dcache.demand_hits::total 6883197
+system.cpu1.dcache.overall_hits::cpu1.data 6932213
+system.cpu1.dcache.overall_hits::total 6932213
+system.cpu1.dcache.ReadReq_misses::cpu1.data 133558
+system.cpu1.dcache.ReadReq_misses::total 133558
+system.cpu1.dcache.WriteReq_misses::cpu1.data 91998
+system.cpu1.dcache.WriteReq_misses::total 91998
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30315
+system.cpu1.dcache.SoftPFReq_misses::total 30315
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16925
+system.cpu1.dcache.LoadLockedReq_misses::total 16925
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23216
+system.cpu1.dcache.StoreCondReq_misses::total 23216
+system.cpu1.dcache.demand_misses::cpu1.data 225556
+system.cpu1.dcache.demand_misses::total 225556
+system.cpu1.dcache.overall_misses::cpu1.data 255871
+system.cpu1.dcache.overall_misses::total 255871
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2046359000
+system.cpu1.dcache.ReadReq_miss_latency::total 2046359000
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2539064000
+system.cpu1.dcache.WriteReq_miss_latency::total 2539064000
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322888000
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 322888000
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544466000
+system.cpu1.dcache.StoreCondReq_miss_latency::total 544466000
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1954500
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1954500
+system.cpu1.dcache.demand_miss_latency::cpu1.data 4585423000
+system.cpu1.dcache.demand_miss_latency::total 4585423000
+system.cpu1.dcache.overall_miss_latency::cpu1.data 4585423000
+system.cpu1.dcache.overall_miss_latency::total 4585423000
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 3775364
+system.cpu1.dcache.ReadReq_accesses::total 3775364
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 3333389
+system.cpu1.dcache.WriteReq_accesses::total 3333389
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79331
+system.cpu1.dcache.SoftPFReq_accesses::total 79331
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95864
+system.cpu1.dcache.LoadLockedReq_accesses::total 95864
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94054
+system.cpu1.dcache.StoreCondReq_accesses::total 94054
+system.cpu1.dcache.demand_accesses::cpu1.data 7108753
+system.cpu1.dcache.demand_accesses::total 7108753
+system.cpu1.dcache.overall_accesses::cpu1.data 7188084
+system.cpu1.dcache.overall_accesses::total 7188084
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035376
+system.cpu1.dcache.ReadReq_miss_rate::total 0.035376
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027599
+system.cpu1.dcache.WriteReq_miss_rate::total 0.027599
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382133
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382133
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176552
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176552
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246837
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246837
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031729
+system.cpu1.dcache.demand_miss_rate::total 0.031729
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035597
+system.cpu1.dcache.overall_miss_rate::total 0.035597
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15321.875140
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15321.875140
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27599.121720
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 27599.121720
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19077.577548
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19077.577548
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23452.188146
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23452.188146
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20329.421518
+system.cpu1.dcache.demand_avg_miss_latency::total 20329.421518
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17920.839017
+system.cpu1.dcache.overall_avg_miss_latency::total 17920.839017
+system.cpu1.dcache.blocked_cycles::no_mshrs 0
+system.cpu1.dcache.blocked_cycles::no_targets 0
+system.cpu1.dcache.blocked::no_mshrs 0
+system.cpu1.dcache.blocked::no_targets 0
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan
+system.cpu1.dcache.writebacks::writebacks 187431
+system.cpu1.dcache.writebacks::total 187431
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 249
+system.cpu1.dcache.ReadReq_mshr_hits::total 249
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11949
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11949
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 249
+system.cpu1.dcache.demand_mshr_hits::total 249
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 249
+system.cpu1.dcache.overall_mshr_hits::total 249
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133309
+system.cpu1.dcache.ReadReq_mshr_misses::total 133309
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91998
+system.cpu1.dcache.WriteReq_mshr_misses::total 91998
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29631
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 29631
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4976
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4976
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23216
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 23216
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 225307
+system.cpu1.dcache.demand_mshr_misses::total 225307
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 254938
+system.cpu1.dcache.overall_mshr_misses::total 254938
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3078
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3078
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2433
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2433
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5511
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5511
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1902134500
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1902134500
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2447066000
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2447066000
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 508307000
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 508307000
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91230500
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91230500
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521295000
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521295000
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1909500
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1909500
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4349200500
+system.cpu1.dcache.demand_mshr_miss_latency::total 4349200500
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4857507500
+system.cpu1.dcache.overall_mshr_miss_latency::total 4857507500
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 442716500
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 442716500
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 442716500
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 442716500
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035310
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035310
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027599
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027599
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373511
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373511
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051907
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051907
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246837
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246837
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031694
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.031694
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035467
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.035467
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14268.612772
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14268.612772
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26599.121720
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26599.121720
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17154.567851
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17154.567851
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18334.103698
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18334.103698
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22454.126465
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22454.126465
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19303.441526
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19303.441526
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19053.681679
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19053.681679
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143832.521118
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143832.521118
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80333.242606
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80333.242606
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu1.icache.tags.replacements 503490
+system.cpu1.icache.tags.tagsinuse 498.455633
+system.cpu1.icache.tags.total_refs 16161536
+system.cpu1.icache.tags.sampled_refs 504002
+system.cpu1.icache.tags.avg_refs 32.066412
+system.cpu1.icache.tags.warmup_cycle 85409649000
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.455633
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973546
+system.cpu1.icache.tags.occ_percent::total 0.973546
+system.cpu1.icache.tags.occ_task_id_blocks::1024 512
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 390
+system.cpu1.icache.tags.age_task_id_blocks_1024::3 118
+system.cpu1.icache.tags.age_task_id_blocks_1024::4 4
+system.cpu1.icache.tags.occ_task_id_percent::1024 1
+system.cpu1.icache.tags.tag_accesses 33835078
+system.cpu1.icache.tags.data_accesses 33835078
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu1.icache.ReadReq_hits::cpu1.inst 16161536
+system.cpu1.icache.ReadReq_hits::total 16161536
+system.cpu1.icache.demand_hits::cpu1.inst 16161536
+system.cpu1.icache.demand_hits::total 16161536
+system.cpu1.icache.overall_hits::cpu1.inst 16161536
+system.cpu1.icache.overall_hits::total 16161536
+system.cpu1.icache.ReadReq_misses::cpu1.inst 504002
+system.cpu1.icache.ReadReq_misses::total 504002
+system.cpu1.icache.demand_misses::cpu1.inst 504002
+system.cpu1.icache.demand_misses::total 504002
+system.cpu1.icache.overall_misses::cpu1.inst 504002
+system.cpu1.icache.overall_misses::total 504002
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4763497000
+system.cpu1.icache.ReadReq_miss_latency::total 4763497000
+system.cpu1.icache.demand_miss_latency::cpu1.inst 4763497000
+system.cpu1.icache.demand_miss_latency::total 4763497000
+system.cpu1.icache.overall_miss_latency::cpu1.inst 4763497000
+system.cpu1.icache.overall_miss_latency::total 4763497000
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 16665538
+system.cpu1.icache.ReadReq_accesses::total 16665538
+system.cpu1.icache.demand_accesses::cpu1.inst 16665538
+system.cpu1.icache.demand_accesses::total 16665538
+system.cpu1.icache.overall_accesses::cpu1.inst 16665538
+system.cpu1.icache.overall_accesses::total 16665538
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030242
+system.cpu1.icache.ReadReq_miss_rate::total 0.030242
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030242
+system.cpu1.icache.demand_miss_rate::total 0.030242
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030242
+system.cpu1.icache.overall_miss_rate::total 0.030242
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9451.345431
+system.cpu1.icache.ReadReq_avg_miss_latency::total 9451.345431
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9451.345431
+system.cpu1.icache.demand_avg_miss_latency::total 9451.345431
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9451.345431
+system.cpu1.icache.overall_avg_miss_latency::total 9451.345431
+system.cpu1.icache.blocked_cycles::no_mshrs 0
+system.cpu1.icache.blocked_cycles::no_targets 0
+system.cpu1.icache.blocked::no_mshrs 0
+system.cpu1.icache.blocked::no_targets 0
+system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
+system.cpu1.icache.avg_blocked_cycles::no_targets nan
+system.cpu1.icache.writebacks::writebacks 503490
+system.cpu1.icache.writebacks::total 503490
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 504002
+system.cpu1.icache.ReadReq_mshr_misses::total 504002
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 504002
+system.cpu1.icache.demand_mshr_misses::total 504002
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 504002
+system.cpu1.icache.overall_mshr_misses::total 504002
+system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177
+system.cpu1.icache.ReadReq_mshr_uncacheable::total 177
+system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177
+system.cpu1.icache.overall_mshr_uncacheable_misses::total 177
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4511496000
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 4511496000
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4511496000
+system.cpu1.icache.demand_mshr_miss_latency::total 4511496000
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4511496000
+system.cpu1.icache.overall_mshr_miss_latency::total 4511496000
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17068500
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17068500
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17068500
+system.cpu1.icache.overall_mshr_uncacheable_latency::total 17068500
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030242
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030242
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030242
+system.cpu1.icache.demand_mshr_miss_rate::total 0.030242
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030242
+system.cpu1.icache.overall_mshr_miss_rate::total 0.030242
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8951.345431
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8951.345431
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8951.345431
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 8951.345431
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8951.345431
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 8951.345431
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96432.203390
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96432.203390
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu1.l2cache.prefetcher.num_hwpf_issued 202572
+system.cpu1.l2cache.prefetcher.pfIdentified 202572
+system.cpu1.l2cache.prefetcher.pfBufferHit 0
+system.cpu1.l2cache.prefetcher.pfInCache 0
+system.cpu1.l2cache.prefetcher.pfRemovedFull 0
+system.cpu1.l2cache.prefetcher.pfSpanPage 60748
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu1.l2cache.tags.replacements 44193
+system.cpu1.l2cache.tags.tagsinuse 14678.581969
+system.cpu1.l2cache.tags.total_refs 602717
+system.cpu1.l2cache.tags.sampled_refs 58543
+system.cpu1.l2cache.tags.avg_refs 10.295287
+system.cpu1.l2cache.tags.warmup_cycle 0
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14292.757866
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.261567
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.050949
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 381.511587
+system.cpu1.l2cache.tags.occ_percent::writebacks 0.872361
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000138
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023286
+system.cpu1.l2cache.tags.occ_percent::total 0.895910
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022 311
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14026
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 28
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 279
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 960
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2474
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10592
+system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.018982
+system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793
+system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.856079
+system.cpu1.l2cache.tags.tag_accesses 24270441
+system.cpu1.l2cache.tags.data_accesses 24270441
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3759
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1985
+system.cpu1.l2cache.ReadReq_hits::total 5744
+system.cpu1.l2cache.WritebackDirty_hits::writebacks 114489
+system.cpu1.l2cache.WritebackDirty_hits::total 114489
+system.cpu1.l2cache.WritebackClean_hits::writebacks 565349
+system.cpu1.l2cache.WritebackClean_hits::total 565349
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27975
+system.cpu1.l2cache.ReadExReq_hits::total 27975
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 482558
+system.cpu1.l2cache.ReadCleanReq_hits::total 482558
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98301
+system.cpu1.l2cache.ReadSharedReq_hits::total 98301
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3759
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1985
+system.cpu1.l2cache.demand_hits::cpu1.inst 482558
+system.cpu1.l2cache.demand_hits::cpu1.data 126276
+system.cpu1.l2cache.demand_hits::total 614578
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3759
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1985
+system.cpu1.l2cache.overall_hits::cpu1.inst 482558
+system.cpu1.l2cache.overall_hits::cpu1.data 126276
+system.cpu1.l2cache.overall_hits::total 614578
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 437
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 314
+system.cpu1.l2cache.ReadReq_misses::total 751
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29360
+system.cpu1.l2cache.UpgradeReq_misses::total 29360
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23211
+system.cpu1.l2cache.SCUpgradeReq_misses::total 23211
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34663
+system.cpu1.l2cache.ReadExReq_misses::total 34663
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21444
+system.cpu1.l2cache.ReadCleanReq_misses::total 21444
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69615
+system.cpu1.l2cache.ReadSharedReq_misses::total 69615
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 437
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker 314
+system.cpu1.l2cache.demand_misses::cpu1.inst 21444
+system.cpu1.l2cache.demand_misses::cpu1.data 104278
+system.cpu1.l2cache.demand_misses::total 126473
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 437
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker 314
+system.cpu1.l2cache.overall_misses::cpu1.inst 21444
+system.cpu1.l2cache.overall_misses::cpu1.data 104278
+system.cpu1.l2cache.overall_misses::total 126473
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8992000
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6332500
+system.cpu1.l2cache.ReadReq_miss_latency::total 15324500
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14822500
+system.cpu1.l2cache.UpgradeReq_miss_latency::total 14822500
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17672000
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17672000
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1842000
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1842000
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1499437000
+system.cpu1.l2cache.ReadExReq_miss_latency::total 1499437000
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 845964500
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total 845964500
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1606802500
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1606802500
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8992000
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6332500
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst 845964500
+system.cpu1.l2cache.demand_miss_latency::cpu1.data 3106239500
+system.cpu1.l2cache.demand_miss_latency::total 3967528500
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8992000
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6332500
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst 845964500
+system.cpu1.l2cache.overall_miss_latency::cpu1.data 3106239500
+system.cpu1.l2cache.overall_miss_latency::total 3967528500
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4196
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2299
+system.cpu1.l2cache.ReadReq_accesses::total 6495
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114489
+system.cpu1.l2cache.WritebackDirty_accesses::total 114489
+system.cpu1.l2cache.WritebackClean_accesses::writebacks 565349
+system.cpu1.l2cache.WritebackClean_accesses::total 565349
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29360
+system.cpu1.l2cache.UpgradeReq_accesses::total 29360
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23211
+system.cpu1.l2cache.SCUpgradeReq_accesses::total 23211
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62638
+system.cpu1.l2cache.ReadExReq_accesses::total 62638
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 504002
+system.cpu1.l2cache.ReadCleanReq_accesses::total 504002
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167916
+system.cpu1.l2cache.ReadSharedReq_accesses::total 167916
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4196
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2299
+system.cpu1.l2cache.demand_accesses::cpu1.inst 504002
+system.cpu1.l2cache.demand_accesses::cpu1.data 230554
+system.cpu1.l2cache.demand_accesses::total 741051
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4196
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2299
+system.cpu1.l2cache.overall_accesses::cpu1.inst 504002
+system.cpu1.l2cache.overall_accesses::cpu1.data 230554
+system.cpu1.l2cache.overall_accesses::total 741051
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.104147
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136581
+system.cpu1.l2cache.ReadReq_miss_rate::total 0.115627
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1
+system.cpu1.l2cache.UpgradeReq_miss_rate::total 1
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.553386
+system.cpu1.l2cache.ReadExReq_miss_rate::total 0.553386
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.042547
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.042547
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.414582
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.414582
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.104147
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136581
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.042547
+system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.452293
+system.cpu1.l2cache.demand_miss_rate::total 0.170667
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.104147
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136581
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.042547
+system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.452293
+system.cpu1.l2cache.overall_miss_rate::total 0.170667
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20576.659039
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20167.197452
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20405.459387
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 504.853542
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 504.853542
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 761.363147
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 761.363147
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 368400
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 368400
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43257.565704
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43257.565704
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39449.939377
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39449.939377
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23081.268405
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23081.268405
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20576.659039
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20167.197452
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39449.939377
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29788.061720
+system.cpu1.l2cache.demand_avg_miss_latency::total 31370.557352
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20576.659039
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20167.197452
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39449.939377
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29788.061720
+system.cpu1.l2cache.overall_avg_miss_latency::total 31370.557352
+system.cpu1.l2cache.blocked_cycles::no_mshrs 0
+system.cpu1.l2cache.blocked_cycles::no_targets 0
+system.cpu1.l2cache.blocked::no_mshrs 0
+system.cpu1.l2cache.blocked::no_targets 0
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu1.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu1.l2cache.unused_prefetches 793
+system.cpu1.l2cache.writebacks::writebacks 33199
+system.cpu1.l2cache.writebacks::total 33199
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 92
+system.cpu1.l2cache.ReadExReq_mshr_hits::total 92
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data 92
+system.cpu1.l2cache.demand_mshr_hits::total 92
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data 92
+system.cpu1.l2cache.overall_mshr_hits::total 92
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 437
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 314
+system.cpu1.l2cache.ReadReq_mshr_misses::total 751
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 26784
+system.cpu1.l2cache.HardPFReq_mshr_misses::total 26784
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29360
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29360
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23211
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23211
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34571
+system.cpu1.l2cache.ReadExReq_mshr_misses::total 34571
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21444
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21444
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69615
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69615
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 437
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 314
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21444
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104186
+system.cpu1.l2cache.demand_mshr_misses::total 126381
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 437
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 314
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21444
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104186
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 26784
+system.cpu1.l2cache.overall_mshr_misses::total 153165
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3078
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3255
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2433
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2433
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5511
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5688
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6370000
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4448500
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10818500
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 966158428
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 966158428
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 448928000
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 448928000
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347176000
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347176000
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1572000
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1572000
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1280853500
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1280853500
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 717300500
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 717300500
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1189112500
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1189112500
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6370000
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4448500
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 717300500
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2469966000
+system.cpu1.l2cache.demand_mshr_miss_latency::total 3198085000
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6370000
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4448500
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 717300500
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2469966000
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 966158428
+system.cpu1.l2cache.overall_mshr_miss_latency::total 4164243428
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15741000
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 417750000
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 433491000
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 15741000
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 417750000
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 433491000
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.104147
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.136581
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.115627
+system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf
+system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.551917
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.551917
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.042547
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042547
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.414582
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.414582
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.104147
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.136581
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.042547
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.451894
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170543
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.104147
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.136581
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.042547
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.451894
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.206686
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14576.659039
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14167.197452
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14405.459387
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36072.223268
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36072.223268
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15290.463215
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15290.463215
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14957.390892
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14957.390892
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 314400
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 314400
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37049.940702
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37049.940702
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33449.939377
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33449.939377
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17081.268405
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17081.268405
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14576.659039
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14167.197452
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33449.939377
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23707.273530
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25305.109154
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14576.659039
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14167.197452
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33449.939377
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23707.273530
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36072.223268
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27187.956961
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135721.247563
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133176.958525
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75802.939575
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76211.497890
+system.cpu1.toL2Bus.snoop_filter.tot_requests 1484455
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 749934
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11083
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 113020
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104758
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8262
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.cpu1.toL2Bus.trans_dist::ReadReq 12654
+system.cpu1.toL2Bus.trans_dist::ReadResp 721934
+system.cpu1.toL2Bus.trans_dist::WriteReq 2433
+system.cpu1.toL2Bus.trans_dist::WriteResp 2433
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 148951
+system.cpu1.toL2Bus.trans_dist::WritebackClean 576432
+system.cpu1.toL2Bus.trans_dist::CleanEvict 28565
+system.cpu1.toL2Bus.trans_dist::HardPFReq 31873
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 70743
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40968
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 85123
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 37
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 77
+system.cpu1.toL2Bus.trans_dist::ReadExReq 69812
+system.cpu1.toL2Bus.trans_dist::ReadExResp 67302
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 504002
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263233
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 286
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1511848
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839363
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5623
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10271
+system.cpu1.toL2Bus.pkt_count::total 2367105
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64480196
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29463938
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9196
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16784
+system.cpu1.toL2Bus.pkt_size::total 93970114
+system.cpu1.toL2Bus.snoops 334403
+system.cpu1.toL2Bus.snoopTraffic 4908896
+system.cpu1.toL2Bus.snoop_fanout::samples 1059068
+system.cpu1.toL2Bus.snoop_fanout::mean 0.131030
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.359811
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu1.toL2Bus.snoop_fanout::0 928560 87.68% 87.68%
+system.cpu1.toL2Bus.snoop_fanout::1 122246 11.54% 99.22%
+system.cpu1.toL2Bus.snoop_fanout::2 8262 0.78% 100.00%
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu1.toL2Bus.snoop_fanout::min_value 0
+system.cpu1.toL2Bus.snoop_fanout::max_value 2
+system.cpu1.toL2Bus.snoop_fanout::total 1059068
+system.cpu1.toL2Bus.reqLayer0.occupancy 1438707500
+system.cpu1.toL2Bus.reqLayer0.utilization 0.1
+system.cpu1.toL2Bus.snoopLayer0.occupancy 79416309
+system.cpu1.toL2Bus.snoopLayer0.utilization 0.0
+system.cpu1.toL2Bus.respLayer0.occupancy 756180000
+system.cpu1.toL2Bus.respLayer0.utilization 0.0
+system.cpu1.toL2Bus.respLayer1.occupancy 376458500
+system.cpu1.toL2Bus.respLayer1.utilization 0.0
+system.cpu1.toL2Bus.respLayer2.occupancy 3324000
+system.cpu1.toL2Bus.respLayer2.utilization 0.0
+system.cpu1.toL2Bus.respLayer3.occupancy 6075499
+system.cpu1.toL2Bus.respLayer3.utilization 0.0
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.iobus.trans_dist::ReadReq 31005
+system.iobus.trans_dist::ReadResp 31005
+system.iobus.trans_dist::WriteReq 59423
+system.iobus.trans_dist::WriteResp 59423
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268
+system.iobus.pkt_count_system.bridge.master::total 107898
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958
+system.iobus.pkt_count_system.realview.ide.dma::total 72958
+system.iobus.pkt_count::total 180856
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536
+system.iobus.pkt_size_system.bridge.master::total 162788
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272
+system.iobus.pkt_size_system.realview.ide.dma::total 2321272
+system.iobus.pkt_size::total 2484060
+system.iobus.reqLayer0.occupancy 48603000
+system.iobus.reqLayer0.utilization 0.0
+system.iobus.reqLayer1.occupancy 106000
+system.iobus.reqLayer1.utilization 0.0
+system.iobus.reqLayer2.occupancy 319500
+system.iobus.reqLayer2.utilization 0.0
+system.iobus.reqLayer3.occupancy 31000
+system.iobus.reqLayer3.utilization 0.0
+system.iobus.reqLayer4.occupancy 15000
+system.iobus.reqLayer4.utilization 0.0
+system.iobus.reqLayer7.occupancy 89500
+system.iobus.reqLayer7.utilization 0.0
+system.iobus.reqLayer8.occupancy 615500
+system.iobus.reqLayer8.utilization 0.0
+system.iobus.reqLayer10.occupancy 22500
+system.iobus.reqLayer10.utilization 0.0
+system.iobus.reqLayer13.occupancy 10500
+system.iobus.reqLayer13.utilization 0.0
+system.iobus.reqLayer14.occupancy 11000
+system.iobus.reqLayer14.utilization 0.0
+system.iobus.reqLayer15.occupancy 11000
+system.iobus.reqLayer15.utilization 0.0
+system.iobus.reqLayer16.occupancy 46500
+system.iobus.reqLayer16.utilization 0.0
+system.iobus.reqLayer17.occupancy 11000
+system.iobus.reqLayer17.utilization 0.0
+system.iobus.reqLayer18.occupancy 10500
+system.iobus.reqLayer18.utilization 0.0
+system.iobus.reqLayer19.occupancy 2500
+system.iobus.reqLayer19.utilization 0.0
+system.iobus.reqLayer20.occupancy 9000
+system.iobus.reqLayer20.utilization 0.0
+system.iobus.reqLayer21.occupancy 10500
+system.iobus.reqLayer21.utilization 0.0
+system.iobus.reqLayer23.occupancy 6211000
+system.iobus.reqLayer23.utilization 0.0
+system.iobus.reqLayer24.occupancy 32041500
+system.iobus.reqLayer24.utilization 0.0
+system.iobus.reqLayer25.occupancy 187899763
+system.iobus.reqLayer25.utilization 0.0
+system.iobus.respLayer0.occupancy 84699000
+system.iobus.respLayer0.utilization 0.0
+system.iobus.respLayer3.occupancy 36782000
+system.iobus.respLayer3.utilization 0.0
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.iocache.tags.replacements 36445
+system.iocache.tags.tagsinuse 14.377038
+system.iocache.tags.total_refs 0
+system.iocache.tags.sampled_refs 36461
+system.iocache.tags.avg_refs 0
+system.iocache.tags.warmup_cycle 290037968000
+system.iocache.tags.occ_blocks::realview.ide 14.377038
+system.iocache.tags.occ_percent::realview.ide 0.898565
+system.iocache.tags.occ_percent::total 0.898565
+system.iocache.tags.occ_task_id_blocks::1023 16
+system.iocache.tags.age_task_id_blocks_1023::3 16
+system.iocache.tags.occ_task_id_percent::1023 1
+system.iocache.tags.tag_accesses 328311
+system.iocache.tags.data_accesses 328311
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.iocache.ReadReq_misses::realview.ide 255
+system.iocache.ReadReq_misses::total 255
+system.iocache.WriteLineReq_misses::realview.ide 36224
+system.iocache.WriteLineReq_misses::total 36224
+system.iocache.demand_misses::realview.ide 36479
+system.iocache.demand_misses::total 36479
+system.iocache.overall_misses::realview.ide 36479
+system.iocache.overall_misses::total 36479
+system.iocache.ReadReq_miss_latency::realview.ide 41048377
+system.iocache.ReadReq_miss_latency::total 41048377
+system.iocache.WriteLineReq_miss_latency::realview.ide 4363745386
+system.iocache.WriteLineReq_miss_latency::total 4363745386
+system.iocache.demand_miss_latency::realview.ide 4404793763
+system.iocache.demand_miss_latency::total 4404793763
+system.iocache.overall_miss_latency::realview.ide 4404793763
+system.iocache.overall_miss_latency::total 4404793763
+system.iocache.ReadReq_accesses::realview.ide 255
+system.iocache.ReadReq_accesses::total 255
+system.iocache.WriteLineReq_accesses::realview.ide 36224
+system.iocache.WriteLineReq_accesses::total 36224
+system.iocache.demand_accesses::realview.ide 36479
+system.iocache.demand_accesses::total 36479
+system.iocache.overall_accesses::realview.ide 36479
+system.iocache.overall_accesses::total 36479
+system.iocache.ReadReq_miss_rate::realview.ide 1
+system.iocache.ReadReq_miss_rate::total 1
+system.iocache.WriteLineReq_miss_rate::realview.ide 1
+system.iocache.WriteLineReq_miss_rate::total 1
+system.iocache.demand_miss_rate::realview.ide 1
+system.iocache.demand_miss_rate::total 1
+system.iocache.overall_miss_rate::realview.ide 1
+system.iocache.overall_miss_rate::total 1
+system.iocache.ReadReq_avg_miss_latency::realview.ide 160974.027451
+system.iocache.ReadReq_avg_miss_latency::total 160974.027451
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120465.585965
+system.iocache.WriteLineReq_avg_miss_latency::total 120465.585965
+system.iocache.demand_avg_miss_latency::realview.ide 120748.753063
+system.iocache.demand_avg_miss_latency::total 120748.753063
+system.iocache.overall_avg_miss_latency::realview.ide 120748.753063
+system.iocache.overall_avg_miss_latency::total 120748.753063
+system.iocache.blocked_cycles::no_mshrs 96
+system.iocache.blocked_cycles::no_targets 0
+system.iocache.blocked::no_mshrs 6
+system.iocache.blocked::no_targets 0
+system.iocache.avg_blocked_cycles::no_mshrs 16
+system.iocache.avg_blocked_cycles::no_targets nan
+system.iocache.writebacks::writebacks 36190
+system.iocache.writebacks::total 36190
+system.iocache.ReadReq_mshr_misses::realview.ide 255
+system.iocache.ReadReq_mshr_misses::total 255
+system.iocache.WriteLineReq_mshr_misses::realview.ide 36224
+system.iocache.WriteLineReq_mshr_misses::total 36224
+system.iocache.demand_mshr_misses::realview.ide 36479
+system.iocache.demand_mshr_misses::total 36479
+system.iocache.overall_mshr_misses::realview.ide 36479
+system.iocache.overall_mshr_misses::total 36479
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 28298377
+system.iocache.ReadReq_mshr_miss_latency::total 28298377
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2550650079
+system.iocache.WriteLineReq_mshr_miss_latency::total 2550650079
+system.iocache.demand_mshr_miss_latency::realview.ide 2578948456
+system.iocache.demand_mshr_miss_latency::total 2578948456
+system.iocache.overall_mshr_miss_latency::realview.ide 2578948456
+system.iocache.overall_mshr_miss_latency::total 2578948456
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1
+system.iocache.ReadReq_mshr_miss_rate::total 1
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1
+system.iocache.WriteLineReq_mshr_miss_rate::total 1
+system.iocache.demand_mshr_miss_rate::realview.ide 1
+system.iocache.demand_mshr_miss_rate::total 1
+system.iocache.overall_mshr_miss_rate::realview.ide 1
+system.iocache.overall_mshr_miss_rate::total 1
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110974.027451
+system.iocache.ReadReq_avg_mshr_miss_latency::total 110974.027451
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70413.264107
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70413.264107
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 70696.796952
+system.iocache.demand_avg_mshr_miss_latency::total 70696.796952
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 70696.796952
+system.iocache.overall_avg_mshr_miss_latency::total 70696.796952
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.l2c.tags.replacements 137349
+system.l2c.tags.tagsinuse 65074.387852
+system.l2c.tags.total_refs 526623
+system.l2c.tags.sampled_refs 202715
+system.l2c.tags.avg_refs 2.597849
+system.l2c.tags.warmup_cycle 103119965000
+system.l2c.tags.occ_blocks::writebacks 6578.412108
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.009780
+system.l2c.tags.occ_blocks::cpu0.itb.walker 0.050992
+system.l2c.tags.occ_blocks::cpu0.inst 7069.334997
+system.l2c.tags.occ_blocks::cpu0.data 6925.851965
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37440.638295
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954844
+system.l2c.tags.occ_blocks::cpu1.inst 1513.332181
+system.l2c.tags.occ_blocks::cpu1.data 3159.920251
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2381.882439
+system.l2c.tags.occ_percent::writebacks 0.100379
+system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061
+system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001
+system.l2c.tags.occ_percent::cpu0.inst 0.107869
+system.l2c.tags.occ_percent::cpu0.data 0.105680
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.571299
+system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015
+system.l2c.tags.occ_percent::cpu1.inst 0.023092
+system.l2c.tags.occ_percent::cpu1.data 0.048217
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036345
+system.l2c.tags.occ_percent::total 0.992956
+system.l2c.tags.occ_task_id_blocks::1022 34273
+system.l2c.tags.occ_task_id_blocks::1023 8
+system.l2c.tags.occ_task_id_blocks::1024 31085
+system.l2c.tags.age_task_id_blocks_1022::2 136
+system.l2c.tags.age_task_id_blocks_1022::3 4607
+system.l2c.tags.age_task_id_blocks_1022::4 29530
+system.l2c.tags.age_task_id_blocks_1023::4 8
+system.l2c.tags.age_task_id_blocks_1024::0 1
+system.l2c.tags.age_task_id_blocks_1024::1 1
+system.l2c.tags.age_task_id_blocks_1024::2 77
+system.l2c.tags.age_task_id_blocks_1024::3 1172
+system.l2c.tags.age_task_id_blocks_1024::4 29834
+system.l2c.tags.occ_task_id_percent::1022 0.522964
+system.l2c.tags.occ_task_id_percent::1023 0.000122
+system.l2c.tags.occ_task_id_percent::1024 0.474319
+system.l2c.tags.tag_accesses 6115156
+system.l2c.tags.data_accesses 6115156
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.l2c.WritebackDirty_hits::writebacks 260566
+system.l2c.WritebackDirty_hits::total 260566
+system.l2c.UpgradeReq_hits::cpu0.data 39877
+system.l2c.UpgradeReq_hits::cpu1.data 4951
+system.l2c.UpgradeReq_hits::total 44828
+system.l2c.SCUpgradeReq_hits::cpu0.data 2380
+system.l2c.SCUpgradeReq_hits::cpu1.data 2211
+system.l2c.SCUpgradeReq_hits::total 4591
+system.l2c.ReadExReq_hits::cpu0.data 3935
+system.l2c.ReadExReq_hits::cpu1.data 1496
+system.l2c.ReadExReq_hits::total 5431
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 137
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker 102
+system.l2c.ReadSharedReq_hits::cpu0.inst 44443
+system.l2c.ReadSharedReq_hits::cpu0.data 52813
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45878
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 45
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker 28
+system.l2c.ReadSharedReq_hits::cpu1.inst 19063
+system.l2c.ReadSharedReq_hits::cpu1.data 11032
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5457
+system.l2c.ReadSharedReq_hits::total 178998
+system.l2c.demand_hits::cpu0.dtb.walker 137
+system.l2c.demand_hits::cpu0.itb.walker 102
+system.l2c.demand_hits::cpu0.inst 44443
+system.l2c.demand_hits::cpu0.data 56748
+system.l2c.demand_hits::cpu0.l2cache.prefetcher 45878
+system.l2c.demand_hits::cpu1.dtb.walker 45
+system.l2c.demand_hits::cpu1.itb.walker 28
+system.l2c.demand_hits::cpu1.inst 19063
+system.l2c.demand_hits::cpu1.data 12528
+system.l2c.demand_hits::cpu1.l2cache.prefetcher 5457
+system.l2c.demand_hits::total 184429
+system.l2c.overall_hits::cpu0.dtb.walker 137
+system.l2c.overall_hits::cpu0.itb.walker 102
+system.l2c.overall_hits::cpu0.inst 44443
+system.l2c.overall_hits::cpu0.data 56748
+system.l2c.overall_hits::cpu0.l2cache.prefetcher 45878
+system.l2c.overall_hits::cpu1.dtb.walker 45
+system.l2c.overall_hits::cpu1.itb.walker 28
+system.l2c.overall_hits::cpu1.inst 19063
+system.l2c.overall_hits::cpu1.data 12528
+system.l2c.overall_hits::cpu1.l2cache.prefetcher 5457
+system.l2c.overall_hits::total 184429
+system.l2c.UpgradeReq_misses::cpu0.data 621
+system.l2c.UpgradeReq_misses::cpu1.data 247
+system.l2c.UpgradeReq_misses::total 868
+system.l2c.SCUpgradeReq_misses::cpu0.data 91
+system.l2c.SCUpgradeReq_misses::cpu1.data 94
+system.l2c.SCUpgradeReq_misses::total 185
+system.l2c.ReadExReq_misses::cpu0.data 11316
+system.l2c.ReadExReq_misses::cpu1.data 8031
+system.l2c.ReadExReq_misses::total 19347
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2
+system.l2c.ReadSharedReq_misses::cpu0.inst 17901
+system.l2c.ReadSharedReq_misses::cpu0.data 9081
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133790
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1
+system.l2c.ReadSharedReq_misses::cpu1.inst 2381
+system.l2c.ReadSharedReq_misses::cpu1.data 942
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6464
+system.l2c.ReadSharedReq_misses::total 170569
+system.l2c.demand_misses::cpu0.dtb.walker 7
+system.l2c.demand_misses::cpu0.itb.walker 2
+system.l2c.demand_misses::cpu0.inst 17901
+system.l2c.demand_misses::cpu0.data 20397
+system.l2c.demand_misses::cpu0.l2cache.prefetcher 133790
+system.l2c.demand_misses::cpu1.dtb.walker 1
+system.l2c.demand_misses::cpu1.inst 2381
+system.l2c.demand_misses::cpu1.data 8973
+system.l2c.demand_misses::cpu1.l2cache.prefetcher 6464
+system.l2c.demand_misses::total 189916
+system.l2c.overall_misses::cpu0.dtb.walker 7
+system.l2c.overall_misses::cpu0.itb.walker 2
+system.l2c.overall_misses::cpu0.inst 17901
+system.l2c.overall_misses::cpu0.data 20397
+system.l2c.overall_misses::cpu0.l2cache.prefetcher 133790
+system.l2c.overall_misses::cpu1.dtb.walker 1
+system.l2c.overall_misses::cpu1.inst 2381
+system.l2c.overall_misses::cpu1.data 8973
+system.l2c.overall_misses::cpu1.l2cache.prefetcher 6464
+system.l2c.overall_misses::total 189916
+system.l2c.UpgradeReq_miss_latency::cpu0.data 10529500
+system.l2c.UpgradeReq_miss_latency::cpu1.data 873500
+system.l2c.UpgradeReq_miss_latency::total 11403000
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data 530500
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data 127000
+system.l2c.SCUpgradeReq_miss_latency::total 657500
+system.l2c.ReadExReq_miss_latency::cpu0.data 1663618000
+system.l2c.ReadExReq_miss_latency::cpu1.data 833998500
+system.l2c.ReadExReq_miss_latency::total 2497616500
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 1167000
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 185500
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1953183500
+system.l2c.ReadSharedReq_miss_latency::cpu0.data 1104956000
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15968852998
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 90000
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst 261942500
+system.l2c.ReadSharedReq_miss_latency::cpu1.data 124056500
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 846103917
+system.l2c.ReadSharedReq_miss_latency::total 20260537915
+system.l2c.demand_miss_latency::cpu0.dtb.walker 1167000
+system.l2c.demand_miss_latency::cpu0.itb.walker 185500
+system.l2c.demand_miss_latency::cpu0.inst 1953183500
+system.l2c.demand_miss_latency::cpu0.data 2768574000
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15968852998
+system.l2c.demand_miss_latency::cpu1.dtb.walker 90000
+system.l2c.demand_miss_latency::cpu1.inst 261942500
+system.l2c.demand_miss_latency::cpu1.data 958055000
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 846103917
+system.l2c.demand_miss_latency::total 22758154415
+system.l2c.overall_miss_latency::cpu0.dtb.walker 1167000
+system.l2c.overall_miss_latency::cpu0.itb.walker 185500
+system.l2c.overall_miss_latency::cpu0.inst 1953183500
+system.l2c.overall_miss_latency::cpu0.data 2768574000
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15968852998
+system.l2c.overall_miss_latency::cpu1.dtb.walker 90000
+system.l2c.overall_miss_latency::cpu1.inst 261942500
+system.l2c.overall_miss_latency::cpu1.data 958055000
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 846103917
+system.l2c.overall_miss_latency::total 22758154415
+system.l2c.WritebackDirty_accesses::writebacks 260566
+system.l2c.WritebackDirty_accesses::total 260566
+system.l2c.UpgradeReq_accesses::cpu0.data 40498
+system.l2c.UpgradeReq_accesses::cpu1.data 5198
+system.l2c.UpgradeReq_accesses::total 45696
+system.l2c.SCUpgradeReq_accesses::cpu0.data 2471
+system.l2c.SCUpgradeReq_accesses::cpu1.data 2305
+system.l2c.SCUpgradeReq_accesses::total 4776
+system.l2c.ReadExReq_accesses::cpu0.data 15251
+system.l2c.ReadExReq_accesses::cpu1.data 9527
+system.l2c.ReadExReq_accesses::total 24778
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 144
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 104
+system.l2c.ReadSharedReq_accesses::cpu0.inst 62344
+system.l2c.ReadSharedReq_accesses::cpu0.data 61894
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179668
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 46
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 28
+system.l2c.ReadSharedReq_accesses::cpu1.inst 21444
+system.l2c.ReadSharedReq_accesses::cpu1.data 11974
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11921
+system.l2c.ReadSharedReq_accesses::total 349567
+system.l2c.demand_accesses::cpu0.dtb.walker 144
+system.l2c.demand_accesses::cpu0.itb.walker 104
+system.l2c.demand_accesses::cpu0.inst 62344
+system.l2c.demand_accesses::cpu0.data 77145
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179668
+system.l2c.demand_accesses::cpu1.dtb.walker 46
+system.l2c.demand_accesses::cpu1.itb.walker 28
+system.l2c.demand_accesses::cpu1.inst 21444
+system.l2c.demand_accesses::cpu1.data 21501
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11921
+system.l2c.demand_accesses::total 374345
+system.l2c.overall_accesses::cpu0.dtb.walker 144
+system.l2c.overall_accesses::cpu0.itb.walker 104
+system.l2c.overall_accesses::cpu0.inst 62344
+system.l2c.overall_accesses::cpu0.data 77145
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179668
+system.l2c.overall_accesses::cpu1.dtb.walker 46
+system.l2c.overall_accesses::cpu1.itb.walker 28
+system.l2c.overall_accesses::cpu1.inst 21444
+system.l2c.overall_accesses::cpu1.data 21501
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11921
+system.l2c.overall_accesses::total 374345
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.015334
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.047518
+system.l2c.UpgradeReq_miss_rate::total 0.018995
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.036827
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.040781
+system.l2c.SCUpgradeReq_miss_rate::total 0.038735
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.741984
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.842973
+system.l2c.ReadExReq_miss_rate::total 0.780814
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.048611
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.019231
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.287133
+system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.146719
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744651
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.021739
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.111033
+system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078670
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.542236
+system.l2c.ReadSharedReq_miss_rate::total 0.487944
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.048611
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.019231
+system.l2c.demand_miss_rate::cpu0.inst 0.287133
+system.l2c.demand_miss_rate::cpu0.data 0.264398
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744651
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.021739
+system.l2c.demand_miss_rate::cpu1.inst 0.111033
+system.l2c.demand_miss_rate::cpu1.data 0.417329
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.542236
+system.l2c.demand_miss_rate::total 0.507329
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.048611
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.019231
+system.l2c.overall_miss_rate::cpu0.inst 0.287133
+system.l2c.overall_miss_rate::cpu0.data 0.264398
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744651
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.021739
+system.l2c.overall_miss_rate::cpu1.inst 0.111033
+system.l2c.overall_miss_rate::cpu1.data 0.417329
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.542236
+system.l2c.overall_miss_rate::total 0.507329
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16955.716586
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3536.437247
+system.l2c.UpgradeReq_avg_miss_latency::total 13137.096774
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5829.670330
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1351.063830
+system.l2c.SCUpgradeReq_avg_miss_latency::total 3554.054054
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 147014.669495
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103847.403810
+system.l2c.ReadExReq_avg_miss_latency::total 129095.802967
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 166714.285714
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92750
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109110.301100
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 121677.788790
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119357.597713
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90000
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 110013.649727
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131694.798301
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 130894.789140
+system.l2c.ReadSharedReq_avg_miss_latency::total 118782.064238
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 166714.285714
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92750
+system.l2c.demand_avg_miss_latency::cpu0.inst 109110.301100
+system.l2c.demand_avg_miss_latency::cpu0.data 135734.372702
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119357.597713
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90000
+system.l2c.demand_avg_miss_latency::cpu1.inst 110013.649727
+system.l2c.demand_avg_miss_latency::cpu1.data 106770.868160
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 130894.789140
+system.l2c.demand_avg_miss_latency::total 119832.738763
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 166714.285714
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92750
+system.l2c.overall_avg_miss_latency::cpu0.inst 109110.301100
+system.l2c.overall_avg_miss_latency::cpu0.data 135734.372702
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119357.597713
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90000
+system.l2c.overall_avg_miss_latency::cpu1.inst 110013.649727
+system.l2c.overall_avg_miss_latency::cpu1.data 106770.868160
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 130894.789140
+system.l2c.overall_avg_miss_latency::total 119832.738763
+system.l2c.blocked_cycles::no_mshrs 0
+system.l2c.blocked_cycles::no_targets 0
+system.l2c.blocked::no_mshrs 0
+system.l2c.blocked::no_targets 0
+system.l2c.avg_blocked_cycles::no_mshrs nan
+system.l2c.avg_blocked_cycles::no_targets nan
+system.l2c.writebacks::writebacks 100516
+system.l2c.writebacks::total 100516
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data 1
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 6
+system.l2c.ReadSharedReq_mshr_hits::total 11
+system.l2c.demand_mshr_hits::cpu0.inst 4
+system.l2c.demand_mshr_hits::cpu0.data 1
+system.l2c.demand_mshr_hits::cpu1.inst 6
+system.l2c.demand_mshr_hits::total 11
+system.l2c.overall_mshr_hits::cpu0.inst 4
+system.l2c.overall_mshr_hits::cpu0.data 1
+system.l2c.overall_mshr_hits::cpu1.inst 6
+system.l2c.overall_mshr_hits::total 11
+system.l2c.CleanEvict_mshr_misses::writebacks 3745
+system.l2c.CleanEvict_mshr_misses::total 3745
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 621
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 247
+system.l2c.UpgradeReq_mshr_misses::total 868
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 91
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 94
+system.l2c.SCUpgradeReq_mshr_misses::total 185
+system.l2c.ReadExReq_mshr_misses::cpu0.data 11316
+system.l2c.ReadExReq_mshr_misses::cpu1.data 8031
+system.l2c.ReadExReq_mshr_misses::total 19347
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7
+system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17897
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9080
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133790
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2375
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data 942
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6464
+system.l2c.ReadSharedReq_mshr_misses::total 170558
+system.l2c.demand_mshr_misses::cpu0.dtb.walker 7
+system.l2c.demand_mshr_misses::cpu0.itb.walker 2
+system.l2c.demand_mshr_misses::cpu0.inst 17897
+system.l2c.demand_mshr_misses::cpu0.data 20396
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133790
+system.l2c.demand_mshr_misses::cpu1.dtb.walker 1
+system.l2c.demand_mshr_misses::cpu1.inst 2375
+system.l2c.demand_mshr_misses::cpu1.data 8973
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6464
+system.l2c.demand_mshr_misses::total 189905
+system.l2c.overall_mshr_misses::cpu0.dtb.walker 7
+system.l2c.overall_mshr_misses::cpu0.itb.walker 2
+system.l2c.overall_mshr_misses::cpu0.inst 17897
+system.l2c.overall_mshr_misses::cpu0.data 20396
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133790
+system.l2c.overall_mshr_misses::cpu1.dtb.walker 1
+system.l2c.overall_mshr_misses::cpu1.inst 2375
+system.l2c.overall_mshr_misses::cpu1.data 8973
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6464
+system.l2c.overall_mshr_misses::total 189905
+system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31749
+system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3075
+system.l2c.ReadReq_mshr_uncacheable::total 44023
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28437
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2433
+system.l2c.WriteReq_mshr_uncacheable::total 30870
+system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60186
+system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5508
+system.l2c.overall_mshr_uncacheable_misses::total 74893
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14716000
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5403500
+system.l2c.UpgradeReq_mshr_miss_latency::total 20119500
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2406500
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2245000
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 4651500
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1550458000
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 753688500
+system.l2c.ReadExReq_mshr_miss_latency::total 2304146500
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1097000
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 165500
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1774101000
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1014092000
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14630948008
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 80000
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 237739500
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 114635502
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 781461422
+system.l2c.ReadSharedReq_mshr_miss_latency::total 18554319932
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1097000
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 165500
+system.l2c.demand_mshr_miss_latency::cpu0.inst 1774101000
+system.l2c.demand_mshr_miss_latency::cpu0.data 2564550000
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14630948008
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 80000
+system.l2c.demand_mshr_miss_latency::cpu1.inst 237739500
+system.l2c.demand_mshr_miss_latency::cpu1.data 868324002
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 781461422
+system.l2c.demand_mshr_miss_latency::total 20858466432
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1097000
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 165500
+system.l2c.overall_mshr_miss_latency::cpu0.inst 1774101000
+system.l2c.overall_mshr_miss_latency::cpu0.data 2564550000
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14630948008
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 80000
+system.l2c.overall_mshr_miss_latency::cpu1.inst 237739500
+system.l2c.overall_mshr_miss_latency::cpu1.data 868324002
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 781461422
+system.l2c.overall_mshr_miss_latency::total 20858466432
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 633244000
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5802252500
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12555000
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362346000
+system.l2c.ReadReq_mshr_uncacheable_latency::total 6810397500
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 633244000
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5802252500
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12555000
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362346000
+system.l2c.overall_mshr_uncacheable_latency::total 6810397500
+system.l2c.CleanEvict_mshr_miss_rate::writebacks inf
+system.l2c.CleanEvict_mshr_miss_rate::total inf
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.015334
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.047518
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.018995
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.036827
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.040781
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.038735
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.741984
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.842973
+system.l2c.ReadExReq_mshr_miss_rate::total 0.780814
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.048611
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.019231
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.287069
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146702
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744651
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.021739
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.110754
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078670
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542236
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.487912
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.048611
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.019231
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.287069
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.264385
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744651
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.021739
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.110754
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.417329
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542236
+system.l2c.demand_mshr_miss_rate::total 0.507299
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.048611
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.019231
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.287069
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.264385
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744651
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.021739
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.110754
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.417329
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542236
+system.l2c.overall_mshr_miss_rate::total 0.507299
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23697.262480
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21876.518219
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23179.147465
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26445.054945
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23882.978723
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25143.243243
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 137014.669495
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 93847.403810
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 119095.802967
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82750
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99128.401408
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 111684.140969
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109357.560416
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80000
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100100.842105
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121693.738854
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120894.403156
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108785.984428
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82750
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99128.401408
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125737.889782
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109357.560416
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80000
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100100.842105
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96770.756937
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120894.403156
+system.l2c.demand_avg_mshr_miss_latency::total 109836.320434
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82750
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99128.401408
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125737.889782
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109357.560416
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80000
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100100.842105
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96770.756937
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120894.403156
+system.l2c.overall_avg_mshr_miss_latency::total 109836.320434
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182753.866264
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117836.097561
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154700.894987
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96405.351743
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65785.403050
+system.l2c.overall_avg_mshr_uncacheable_latency::total 90935.033982
+system.membus.snoop_filter.tot_requests 502622
+system.membus.snoop_filter.hit_single_requests 282245
+system.membus.snoop_filter.hit_multi_requests 635
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.membus.trans_dist::ReadReq 44023
+system.membus.trans_dist::ReadResp 214836
+system.membus.trans_dist::WriteReq 30870
+system.membus.trans_dist::WriteResp 30870
+system.membus.trans_dist::WritebackDirty 136706
+system.membus.trans_dist::CleanEvict 16434
+system.membus.trans_dist::UpgradeReq 64435
+system.membus.trans_dist::SCUpgradeReq 38119
+system.membus.trans_dist::UpgradeResp 17
+system.membus.trans_dist::SCUpgradeFailReq 1
+system.membus.trans_dist::ReadExReq 39786
+system.membus.trans_dist::ReadExResp 19314
+system.membus.trans_dist::ReadSharedReq 170813
+system.membus.trans_dist::InvalidateReq 36224
+system.membus.trans_dist::InvalidateResp 4530
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107898
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13552
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 647420
+system.membus.pkt_count_system.l2c.mem_side::total 768904
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939
+system.membus.pkt_count_system.iocache.mem_side::total 72939
+system.membus.pkt_count::total 841843
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162788
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27104
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18619276
+system.membus.pkt_size_system.l2c.mem_side::total 18809236
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120
+system.membus.pkt_size_system.iocache.mem_side::total 2317120
+system.membus.pkt_size::total 21126356
+system.membus.snoops 127076
+system.membus.snoopTraffic 37632
+system.membus.snoop_fanout::samples 424271
+system.membus.snoop_fanout::mean 0.012216
+system.membus.snoop_fanout::stdev 0.109850
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 419088 98.78% 98.78%
+system.membus.snoop_fanout::1 5183 1.22% 100.00%
+system.membus.snoop_fanout::2 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 1
+system.membus.snoop_fanout::total 424271
+system.membus.reqLayer0.occupancy 88177000
+system.membus.reqLayer0.utilization 0.0
+system.membus.reqLayer1.occupancy 19000
+system.membus.reqLayer1.utilization 0.0
+system.membus.reqLayer2.occupancy 11309000
+system.membus.reqLayer2.utilization 0.0
+system.membus.reqLayer5.occupancy 970280052
+system.membus.reqLayer5.utilization 0.0
+system.membus.respLayer2.occupancy 1113160766
+system.membus.respLayer2.utilization 0.0
+system.membus.respLayer3.occupancy 7258187
+system.membus.respLayer3.utilization 0.0
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.dcc.osc_cpu.clock 16667
+system.realview.dcc.osc_ddr.clock 25000
+system.realview.dcc.osc_hsbm.clock 25000
+system.realview.dcc.osc_pxl.clock 42105
+system.realview.dcc.osc_smb.clock 20000
+system.realview.dcc.osc_sys.clock 16667
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.ethernet.descDMAReads 0
+system.realview.ethernet.descDMAWrites 0
+system.realview.ethernet.descDmaReadBytes 0
+system.realview.ethernet.descDmaWriteBytes 0
+system.realview.ethernet.postedSwi 0
+system.realview.ethernet.coalescedSwi nan
+system.realview.ethernet.totalSwi 0
+system.realview.ethernet.postedRxIdle 0
+system.realview.ethernet.coalescedRxIdle nan
+system.realview.ethernet.totalRxIdle 0
+system.realview.ethernet.postedRxOk 0
+system.realview.ethernet.coalescedRxOk nan
+system.realview.ethernet.totalRxOk 0
+system.realview.ethernet.postedRxDesc 0
+system.realview.ethernet.coalescedRxDesc nan
+system.realview.ethernet.totalRxDesc 0
+system.realview.ethernet.postedTxOk 0
+system.realview.ethernet.coalescedTxOk nan
+system.realview.ethernet.totalTxOk 0
+system.realview.ethernet.postedTxIdle 0
+system.realview.ethernet.coalescedTxIdle nan
+system.realview.ethernet.totalTxIdle 0
+system.realview.ethernet.postedTxDesc 0
+system.realview.ethernet.coalescedTxDesc nan
+system.realview.ethernet.totalTxDesc 0
+system.realview.ethernet.postedRxOrn 0
+system.realview.ethernet.coalescedRxOrn nan
+system.realview.ethernet.totalRxOrn 0
+system.realview.ethernet.coalescedTotal nan
+system.realview.ethernet.postedInterrupts 0
+system.realview.ethernet.droppedPackets 0
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.mcc.osc_clcd.clock 42105
+system.realview.mcc.osc_mcc.clock 20000
+system.realview.mcc.osc_peripheral.clock 41667
+system.realview.mcc.osc_system_bus.clock 41667
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.toL2Bus.snoop_filter.tot_requests 1013756
+system.toL2Bus.snoop_filter.hit_single_requests 527510
+system.toL2Bus.snoop_filter.hit_multi_requests 187290
+system.toL2Bus.snoop_filter.tot_snoops 29674
+system.toL2Bus.snoop_filter.hit_single_snoops 28443
+system.toL2Bus.snoop_filter.hit_multi_snoops 1231
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2871012355500
+system.toL2Bus.trans_dist::ReadReq 44026
+system.toL2Bus.trans_dist::ReadResp 511611
+system.toL2Bus.trans_dist::WriteReq 30870
+system.toL2Bus.trans_dist::WriteResp 30870
+system.toL2Bus.trans_dist::WritebackDirty 361082
+system.toL2Bus.trans_dist::CleanEvict 119910
+system.toL2Bus.trans_dist::UpgradeReq 109230
+system.toL2Bus.trans_dist::SCUpgradeReq 42710
+system.toL2Bus.trans_dist::UpgradeResp 151940
+system.toL2Bus.trans_dist::SCUpgradeFailReq 77
+system.toL2Bus.trans_dist::UpgradeFailResp 77
+system.toL2Bus.trans_dist::ReadExReq 50740
+system.toL2Bus.trans_dist::ReadExResp 50740
+system.toL2Bus.trans_dist::ReadSharedReq 467589
+system.toL2Bus.trans_dist::InvalidateReq 4574
+system.toL2Bus.trans_dist::InvalidateResp 3436
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1274602
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 317408
+system.toL2Bus.pkt_count::total 1592010
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35235610
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5660730
+system.toL2Bus.pkt_size::total 40896340
+system.toL2Bus.snoops 391148
+system.toL2Bus.snoopTraffic 15652684
+system.toL2Bus.snoop_fanout::samples 887182
+system.toL2Bus.snoop_fanout::mean 0.397329
+system.toL2Bus.snoop_fanout::stdev 0.492173
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.toL2Bus.snoop_fanout::0 535910 60.41% 60.41%
+system.toL2Bus.snoop_fanout::1 350041 39.46% 99.86%
+system.toL2Bus.snoop_fanout::2 1231 0.14% 100.00%
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.toL2Bus.snoop_fanout::min_value 0
+system.toL2Bus.snoop_fanout::max_value 2
+system.toL2Bus.snoop_fanout::total 887182
+system.toL2Bus.reqLayer0.occupancy 894578674
+system.toL2Bus.reqLayer0.utilization 0.0
+system.toL2Bus.snoopLayer0.occupancy 2158873
+system.toL2Bus.snoopLayer0.utilization 0.0
+system.toL2Bus.respLayer0.occupancy 676162622
+system.toL2Bus.respLayer0.utilization 0.0
+system.toL2Bus.respLayer1.occupancy 239095357
+system.toL2Bus.respLayer1.utilization 0.0
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/dist/m5/system/binaries/boot_emm.arm
+boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
-dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_panic=true
phys_addr_range_64=40
power_model=Null
-readfile=/z/powerjg/gem5-upstream/tests/testing/../halt.sh
+readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/m5/system/disks/linux-aarch32-ael.img
+image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80008000
+info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+info: Entering event queue @ 0. Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
+info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 29 2016 19:03:48
-gem5 started Nov 29 2016 19:06:57
-gem5 executing on zizzer, pid 5768
-command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing
+gem5 compiled Mar 29 2017 18:44:23
+gem5 started Mar 29 2017 18:44:38
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 53278
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2905317504500 because m5_exit instruction encountered
+Exiting @ tick 2905305537500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.905317 # Number of seconds simulated
-sim_ticks 2905316914500 # Number of ticks simulated
-final_tick 2905316914500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1074625 # Simulator instruction rate (inst/s)
-host_op_rate 1295669 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 27762631762 # Simulator tick rate (ticks/s)
-host_mem_usage 582724 # Number of bytes of host memory used
-host_seconds 104.65 # Real time elapsed on the host
-sim_insts 112457861 # Number of instructions simulated
-sim_ops 135589764 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 8969572 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10157640 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1186532 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1186532 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7562240 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7579764 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 26993 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 140669 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 167686 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 118160 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 122541 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 408400 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3087296 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3496224 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 408400 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 408400 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2602897 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 6032 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2608928 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2602897 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 408400 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3093327 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6105153 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 167686 # Number of read requests accepted
-system.physmem.writeReqs 122541 # Number of write requests accepted
-system.physmem.readBursts 167686 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 122541 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10724160 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7592640 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10157640 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7579764 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 9873 # Per bank write bursts
-system.physmem.perBankRdBursts::1 9614 # Per bank write bursts
-system.physmem.perBankRdBursts::2 9963 # Per bank write bursts
-system.physmem.perBankRdBursts::3 9595 # Per bank write bursts
-system.physmem.perBankRdBursts::4 18744 # Per bank write bursts
-system.physmem.perBankRdBursts::5 9936 # Per bank write bursts
-system.physmem.perBankRdBursts::6 10635 # Per bank write bursts
-system.physmem.perBankRdBursts::7 11205 # Per bank write bursts
-system.physmem.perBankRdBursts::8 9589 # Per bank write bursts
-system.physmem.perBankRdBursts::9 10033 # Per bank write bursts
-system.physmem.perBankRdBursts::10 9283 # Per bank write bursts
-system.physmem.perBankRdBursts::11 8863 # Per bank write bursts
-system.physmem.perBankRdBursts::12 10202 # Per bank write bursts
-system.physmem.perBankRdBursts::13 10190 # Per bank write bursts
-system.physmem.perBankRdBursts::14 10325 # Per bank write bursts
-system.physmem.perBankRdBursts::15 9515 # Per bank write bursts
-system.physmem.perBankWrBursts::0 7137 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7022 # Per bank write bursts
-system.physmem.perBankWrBursts::2 7742 # Per bank write bursts
-system.physmem.perBankWrBursts::3 7365 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7465 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7289 # Per bank write bursts
-system.physmem.perBankWrBursts::6 7716 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8300 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7184 # Per bank write bursts
-system.physmem.perBankWrBursts::9 7439 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6836 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6804 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7947 # Per bank write bursts
-system.physmem.perBankWrBursts::13 7681 # Per bank write bursts
-system.physmem.perBankWrBursts::14 7752 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6956 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 62 # Number of times write queue was full causing retry
-system.physmem.totGap 2905316552500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 9558 # Read request sizes (log2)
-system.physmem.readPktSize::3 14 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 158114 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 4381 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 118160 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 166731 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 559 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 263 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1867 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2821 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5995 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5894 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6231 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5852 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6236 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6586 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 7526 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 7121 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 8226 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 8867 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 7085 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 6554 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 6505 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 6306 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6131 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 6216 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 449 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 406 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 379 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 299 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 287 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 253 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 223 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 280 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 242 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 233 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 174 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 175 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 154 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 164 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 173 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 171 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 137 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 122 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 247 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 217 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 117 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 206 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 194 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 187 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 68 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 126 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 57707 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 317.409257 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 186.502400 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 335.930049 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 20577 35.66% 35.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 14716 25.50% 61.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5644 9.78% 70.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3157 5.47% 76.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2419 4.19% 80.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1386 2.40% 83.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1272 2.20% 85.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 912 1.58% 86.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7624 13.21% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 57707 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5794 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 28.920090 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 588.859251 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 5793 99.98% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5794 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5794 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.475492 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.528054 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 14.935092 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5069 87.49% 87.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 43 0.74% 88.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 41 0.71% 88.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 52 0.90% 89.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 288 4.97% 94.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 23 0.40% 95.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 16 0.28% 95.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 7 0.12% 95.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 5 0.09% 95.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 2 0.03% 95.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 1 0.02% 95.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 5 0.09% 95.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 158 2.73% 98.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 7 0.12% 98.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 5 0.09% 98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 5 0.09% 98.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 8 0.14% 98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 5 0.09% 99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 2 0.03% 99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 2 0.03% 99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 9 0.16% 99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 2 0.03% 99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 1 0.02% 99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 2 0.03% 99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 8 0.14% 99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 5 0.09% 99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 6 0.10% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 5 0.09% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 1 0.02% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 1 0.02% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 4 0.07% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183 2 0.03% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5794 # Writes before turning the bus around for reads
-system.physmem.totQLat 4572629500 # Total ticks spent queuing
-system.physmem.totMemAccLat 7714473250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 837825000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 27288.69 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 46038.69 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 3.69 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.61 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 3.50 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.61 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.05 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing
-system.physmem.readRowHits 138575 # Number of row buffer hits during reads
-system.physmem.writeRowHits 89917 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.70 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.78 # Row buffer hit rate for writes
-system.physmem.avgGap 10010497.14 # Average gap between requests
-system.physmem.pageHitRate 79.83 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 209944560 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 111588180 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 639494100 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 313387920 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 6674375760.000002 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 4793281050 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 418187520 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 13958691240 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 9415844160 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 682618118940 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 719155193400 # Total energy per rank (pJ)
-system.physmem_0.averagePower 247.530722 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 2893187924000 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 788400750 # Time in different power states
-system.physmem_0.memoryStateTime::REF 2838298000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 2838579624000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 24520427750 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 7978656750 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 30611507250 # Time in different power states
-system.physmem_1.actEnergy 202090560 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 107409885 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 556920000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 305886780 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 6670687920.000002 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 4519112190 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 410472000 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 13651117530 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 9526323840 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 682932964665 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 718884016170 # Total energy per rank (pJ)
-system.physmem_1.averagePower 247.437384 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 2894335317000 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 777922000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 2837434000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 2839590532250 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 24808008250 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 7366175500 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 29936842500 # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 9553 # Table walker walks requested
-system.cpu.dtb.walker.walksShort 9553 # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1256 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8297 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples 9553 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 9553 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 9553 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 7389 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 10013.601299 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 8464.254766 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 6610.467359 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-16383 6588 89.16% 89.16% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::16384-32767 796 10.77% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 7389 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 1003066500 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0 1003066500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 1003066500 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 6180 83.64% 83.64% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M 1209 16.36% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 7389 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9553 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9553 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7389 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7389 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 16942 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 24519746 # DTB read hits
-system.cpu.dtb.read_misses 8140 # DTB read misses
-system.cpu.dtb.write_hits 19605246 # DTB write hits
-system.cpu.dtb.write_misses 1413 # DTB write misses
-system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4209 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 1622 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 24527886 # DTB read accesses
-system.cpu.dtb.write_accesses 19606659 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 44124992 # DTB hits
-system.cpu.dtb.misses 9553 # DTB misses
-system.cpu.dtb.accesses 44134545 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 4763 # Table walker walks requested
-system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 10180.341055 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 8232.055098 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 7311.468363 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-8191 1821 58.59% 58.59% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::8192-16383 761 24.49% 83.08% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-24575 524 16.86% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::98304-106495 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 1002711000 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 1002711000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 1002711000 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 115555708 # ITB inst hits
-system.cpu.itb.inst_misses 4763 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 115560471 # ITB inst accesses
-system.cpu.itb.hits 115555708 # DTB hits
-system.cpu.itb.misses 4763 # DTB misses
-system.cpu.itb.accesses 115560471 # DTB accesses
-system.cpu.numPwrStateTransitions 6064 # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples 3032 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean 887473262.784960 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev 17466686239.333317 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows 2968 97.89% 97.89% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 499963437276 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total 3032 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON 214497981736 # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 2690818932764 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 5810633829 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed
-system.cpu.committedInsts 112457861 # Number of instructions committed
-system.cpu.committedOps 135589764 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 119894844 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses
-system.cpu.num_func_calls 9894754 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 15230835 # number of instructions that are conditional controls
-system.cpu.num_int_insts 119894844 # number of integer instructions
-system.cpu.num_fp_insts 11290 # number of float instructions
-system.cpu.num_int_register_reads 218056368 # number of times the integer registers were read
-system.cpu.num_int_register_writes 82647309 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 489747242 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 51895082 # number of times the CC registers were written
-system.cpu.num_mem_refs 45405279 # number of memory refs
-system.cpu.num_load_insts 24842044 # Number of load instructions
-system.cpu.num_store_insts 20563235 # Number of store instructions
-system.cpu.num_idle_cycles 5381637865.526148 # Number of idle cycles
-system.cpu.num_busy_cycles 428995963.473852 # Number of busy cycles
-system.cpu.not_idle_fraction 0.073829 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.926171 # Percentage of idle cycles
-system.cpu.Branches 25919556 # Number of branches fetched
-system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 93179861 67.18% 67.18% # Class of executed instruction
-system.cpu.op_class::IntMult 114520 0.08% 67.26% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 8439 0.01% 67.27% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction
-system.cpu.op_class::MemRead 24839336 17.91% 85.17% # Class of executed instruction
-system.cpu.op_class::MemWrite 20554657 14.82% 99.99% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 2708 0.00% 99.99% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 8578 0.01% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 138710436 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 821157 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.816175 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 43232042 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 821669 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 52.614912 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 1078145500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.816175 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999641 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999641 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 177104694 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 177104694 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 23110946 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23110946 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18822565 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18822565 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 392473 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 392473 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 443108 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 443108 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 460141 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 460141 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 41933511 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 41933511 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 42325984 # number of overall hits
-system.cpu.dcache.overall_hits::total 42325984 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 401142 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 401142 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 298882 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 298882 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 118684 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 118684 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 22806 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 22806 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 700024 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 700024 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 818708 # number of overall misses
-system.cpu.dcache.overall_misses::total 818708 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 6437831500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 6437831500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 14440805000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 14440805000 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297461000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 297461000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 20878636500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 20878636500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 20878636500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 20878636500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 23512088 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 23512088 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19121447 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 19121447 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 511157 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 511157 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465914 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 465914 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 460143 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 460143 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 42633535 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 42633535 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 43144692 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 43144692 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017061 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.017061 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.232187 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.232187 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048949 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048949 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.016420 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.016420 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.018976 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.018976 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16048.759542 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16048.759542 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48316.074571 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48316.074571 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13043.102692 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13043.102692 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29825.600979 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29825.600979 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 25501.932924 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 25501.932924 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 685616 # number of writebacks
-system.cpu.dcache.writebacks::total 685616 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 708 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 708 # number of ReadReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14278 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 14278 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 708 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 708 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 708 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 708 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400434 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 400434 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298882 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 298882 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116661 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 116661 # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8528 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 8528 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 699316 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 699316 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 815977 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 815977 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6012304000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 6012304000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14141923000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 14141923000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1586831500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1586831500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118977500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118977500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20154227000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 20154227000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21741058500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 21741058500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6284829000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6284829000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6284829000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 6284829000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017031 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017031 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228229 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228229 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018304 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018304 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016403 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.016403 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018913 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.018913 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15014.469301 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15014.469301 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47316.074571 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47316.074571 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13602.073529 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13602.073529 # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13951.395403 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13951.395403 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28819.914030 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28819.914030 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26644.205045 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26644.205045 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201837.915088 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201837.915088 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107017.709061 # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107017.709061 # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 1700062 # number of replacements
-system.cpu.icache.tags.tagsinuse 510.693087 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 113855128 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1700574 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 66.950999 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 26307743500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 510.693087 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.997447 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.997447 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 117256288 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 117256288 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 113855128 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 113855128 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 113855128 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 113855128 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 113855128 # number of overall hits
-system.cpu.icache.overall_hits::total 113855128 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1700580 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1700580 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1700580 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1700580 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1700580 # number of overall misses
-system.cpu.icache.overall_misses::total 1700580 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 24044969500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 24044969500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 24044969500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 24044969500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 24044969500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 24044969500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 115555708 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 115555708 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 115555708 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 115555708 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 115555708 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 115555708 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014717 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.014717 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.014717 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.014717 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.014717 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.014717 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14139.275718 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14139.275718 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14139.275718 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14139.275718 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14139.275718 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14139.275718 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks 1700062 # number of writebacks
-system.cpu.icache.writebacks::total 1700062 # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700580 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1700580 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1700580 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1700580 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1700580 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1700580 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22344389500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 22344389500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22344389500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 22344389500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22344389500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 22344389500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 745203000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 745203000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 745203000 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total 745203000 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014717 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.014717 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.014717 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13139.275718 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13139.275718 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13139.275718 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13139.275718 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13139.275718 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13139.275718 # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82598.426070 # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82598.426070 # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 88598 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 65011.992508 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 4854149 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 154025 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 31.515332 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 147534324000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.050681 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.041157 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 9634.969504 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 55373.931167 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000047 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.147018 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.844939 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.992004 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 65422 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4349 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60996 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998260 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 40276408 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 40276408 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5063 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2684 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 7747 # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks 685616 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 685616 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 1667781 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 1667781 # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 2789 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 2789 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 167648 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 167648 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682586 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 1682586 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513551 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 513551 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 5063 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 2684 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 1682586 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 681199 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2371532 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 5063 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 2684 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 1682586 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 681199 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2371532 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 128427 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 128427 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17978 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 17978 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12072 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 12072 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 17978 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 140499 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 158486 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 17978 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 140499 # number of overall misses
-system.cpu.l2cache.overall_misses::total 158486 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1154000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 180000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 1334000 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 525000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 525000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 161000 # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total 161000 # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11899913500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 11899913500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2066366000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 2066366000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1520063000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 1520063000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1154000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 180000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 2066366000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 13419976500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 15487676500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1154000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 180000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 2066366000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 13419976500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 15487676500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5070 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2686 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 7756 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 685616 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 685616 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks 1667781 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 1667781 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2807 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 2807 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 296075 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 296075 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700564 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 1700564 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525623 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 525623 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5070 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 2686 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 1700564 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 821698 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2530018 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5070 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 2686 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1700564 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 821698 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2530018 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001381 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000745 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.001160 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.006413 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.006413 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.433765 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.433765 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010572 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010572 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.022967 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.022967 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001381 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000745 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010572 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.170986 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.062642 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001381 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000745 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010572 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.170986 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.062642 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 164857.142857 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 90000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 148222.222222 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29166.666667 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29166.666667 # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92658.969687 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92658.969687 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114938.591612 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114938.591612 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125916.418158 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125916.418158 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 164857.142857 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114938.591612 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95516.526808 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 97722.678975 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 164857.142857 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114938.591612 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95516.526808 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 97722.678975 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks 81970 # number of writebacks
-system.cpu.l2cache.writebacks::total 81970 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128427 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 128427 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17978 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17978 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12072 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12072 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 17978 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 140499 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 158486 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 17978 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 140499 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 158486 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1084000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 160000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1244000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 345000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 345000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 141000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 141000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10615643500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10615643500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1886586000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1886586000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1399343000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1399343000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1084000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 160000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1886586000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12014986500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 13902816500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1084000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 160000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1886586000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12014986500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 13902816500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 632428000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5895484000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6527912000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 632428000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5895484000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6527912000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001160 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.006413 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.006413 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.433765 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.433765 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010572 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.022967 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.022967 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170986 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.062642 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170986 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.062642 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 80000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138222.222222 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19166.666667 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19166.666667 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82658.969687 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82658.969687 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104938.591612 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104938.591612 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115916.418158 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115916.418158 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104938.591612 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85516.526808 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87722.678975 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104938.591612 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85516.526808 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87722.678975 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189334.061276 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162547.609562 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100387.964650 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96354.366854 # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 5065624 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543358 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39299 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 227 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 227 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq 67226 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2293620 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 767586 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 1700062 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 142169 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2807 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2809 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 296075 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 296075 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700580 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 525822 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 4351 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp 14 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119250 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2587830 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11902 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22920 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7741902 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217676152 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96663453 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10744 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 20280 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 314370629 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 112679 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 5336568 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 2713050 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.021694 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.145681 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 2654194 97.83% 97.83% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 58856 2.17% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 2713050 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4970033000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 354876 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 2559892000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1278884000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 17850000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 30159 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30159 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72868 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72868 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178346 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320912 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2320912 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480037 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 46336500 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 642500 # Layer occupancy (ticks)
-system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 52500 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6289000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 187507137 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36692000 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 36400 # number of replacements
-system.iocache.tags.tagsinuse 1.079862 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 36416 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 310617748000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 1.079862 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.067491 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.067491 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 327906 # Number of tag accesses
-system.iocache.tags.data_accesses 327906 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ide 210 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 210 # number of ReadReq misses
-system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide 36434 # number of demand (read+write) misses
-system.iocache.demand_misses::total 36434 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide 36434 # number of overall misses
-system.iocache.overall_misses::total 36434 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 34066376 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 34066376 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 4377262761 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 4377262761 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 4411329137 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 4411329137 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 4411329137 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 4411329137 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide 210 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 210 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide 36434 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 36434 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide 36434 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 36434 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 162220.838095 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120838.746715 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 120838.746715 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 121077.266756 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 121077.266756 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 121077.266756 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 121077.266756 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 52 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 36190 # number of writebacks
-system.iocache.writebacks::total 36190 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide 210 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 210 # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 36434 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 36434 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 36434 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 36434 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 23566376 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 23566376 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2564294505 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 2564294505 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 2587860881 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 2587860881 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 2587860881 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 2587860881 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70789.932227 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70789.932227 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 71028.733628 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 71028.733628 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 71028.733628 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 71028.733628 # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests 320000 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 129537 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 496 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 40160 # Transaction distribution
-system.membus.trans_dist::ReadResp 70429 # Transaction distribution
-system.membus.trans_dist::WriteReq 27589 # Transaction distribution
-system.membus.trans_dist::WriteResp 27589 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 118160 # Transaction distribution
-system.membus.trans_dist::CleanEvict 6838 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 128 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::ReadExReq 128317 # Transaction distribution
-system.membus.trans_dist::ReadExResp 128317 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 30269 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 4315 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 433109 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 540701 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72849 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72849 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 613550 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15420284 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15583637 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 17900757 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 4789 # Total snoops (count)
-system.membus.snoopTraffic 30208 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 262689 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.018383 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.134332 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 257860 98.16% 98.16% # Request fanout histogram
-system.membus.snoop_fanout::1 4829 1.84% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 262689 # Request fanout histogram
-system.membus.reqLayer0.occupancy 90467000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1724500 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 822822299 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 948652750 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 5614930 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
+sim_seconds 2.905306
+sim_ticks 2905305537500
+final_tick 2905305537500
+sim_freq 1000000000000
+host_inst_rate 1111245
+host_op_rate 1339819
+host_tick_rate 28710628480
+host_mem_usage 591900
+host_seconds 101.19
+sim_insts 112449853
+sim_ops 135579871
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.physmem.bytes_read::cpu.dtb.walker 448
+system.physmem.bytes_read::cpu.itb.walker 128
+system.physmem.bytes_read::cpu.inst 1186468
+system.physmem.bytes_read::cpu.data 8969572
+system.physmem.bytes_read::realview.ide 960
+system.physmem.bytes_read::total 10157576
+system.physmem.bytes_inst_read::cpu.inst 1186468
+system.physmem.bytes_inst_read::total 1186468
+system.physmem.bytes_written::writebacks 7562240
+system.physmem.bytes_written::cpu.data 17524
+system.physmem.bytes_written::total 7579764
+system.physmem.num_reads::cpu.dtb.walker 7
+system.physmem.num_reads::cpu.itb.walker 2
+system.physmem.num_reads::cpu.inst 26992
+system.physmem.num_reads::cpu.data 140669
+system.physmem.num_reads::realview.ide 15
+system.physmem.num_reads::total 167685
+system.physmem.num_writes::writebacks 118160
+system.physmem.num_writes::cpu.data 4381
+system.physmem.num_writes::total 122541
+system.physmem.bw_read::cpu.dtb.walker 154
+system.physmem.bw_read::cpu.itb.walker 44
+system.physmem.bw_read::cpu.inst 408380
+system.physmem.bw_read::cpu.data 3087308
+system.physmem.bw_read::realview.ide 330
+system.physmem.bw_read::total 3496216
+system.physmem.bw_inst_read::cpu.inst 408380
+system.physmem.bw_inst_read::total 408380
+system.physmem.bw_write::writebacks 2602907
+system.physmem.bw_write::cpu.data 6032
+system.physmem.bw_write::total 2608939
+system.physmem.bw_total::writebacks 2602907
+system.physmem.bw_total::cpu.dtb.walker 154
+system.physmem.bw_total::cpu.itb.walker 44
+system.physmem.bw_total::cpu.inst 408380
+system.physmem.bw_total::cpu.data 3093339
+system.physmem.bw_total::realview.ide 330
+system.physmem.bw_total::total 6105155
+system.physmem.readReqs 167685
+system.physmem.writeReqs 122541
+system.physmem.readBursts 167685
+system.physmem.writeBursts 122541
+system.physmem.bytesReadDRAM 10724672
+system.physmem.bytesReadWrQ 7168
+system.physmem.bytesWritten 7592640
+system.physmem.bytesReadSys 10157576
+system.physmem.bytesWrittenSys 7579764
+system.physmem.servicedByWrQ 112
+system.physmem.mergedWrBursts 3887
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 9873
+system.physmem.perBankRdBursts::1 9614
+system.physmem.perBankRdBursts::2 9963
+system.physmem.perBankRdBursts::3 9595
+system.physmem.perBankRdBursts::4 18744
+system.physmem.perBankRdBursts::5 9936
+system.physmem.perBankRdBursts::6 10635
+system.physmem.perBankRdBursts::7 11205
+system.physmem.perBankRdBursts::8 9589
+system.physmem.perBankRdBursts::9 10032
+system.physmem.perBankRdBursts::10 9283
+system.physmem.perBankRdBursts::11 8863
+system.physmem.perBankRdBursts::12 10211
+system.physmem.perBankRdBursts::13 10190
+system.physmem.perBankRdBursts::14 10325
+system.physmem.perBankRdBursts::15 9515
+system.physmem.perBankWrBursts::0 7137
+system.physmem.perBankWrBursts::1 7022
+system.physmem.perBankWrBursts::2 7742
+system.physmem.perBankWrBursts::3 7365
+system.physmem.perBankWrBursts::4 7465
+system.physmem.perBankWrBursts::5 7289
+system.physmem.perBankWrBursts::6 7716
+system.physmem.perBankWrBursts::7 8300
+system.physmem.perBankWrBursts::8 7184
+system.physmem.perBankWrBursts::9 7439
+system.physmem.perBankWrBursts::10 6836
+system.physmem.perBankWrBursts::11 6804
+system.physmem.perBankWrBursts::12 7947
+system.physmem.perBankWrBursts::13 7681
+system.physmem.perBankWrBursts::14 7752
+system.physmem.perBankWrBursts::15 6956
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 63
+system.physmem.totGap 2905305175500
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 9558
+system.physmem.readPktSize::3 14
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 158113
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 4381
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 118160
+system.physmem.rdQLenPdf::0 166739
+system.physmem.rdQLenPdf::1 559
+system.physmem.rdQLenPdf::2 263
+system.physmem.rdQLenPdf::3 1
+system.physmem.rdQLenPdf::4 1
+system.physmem.rdQLenPdf::5 1
+system.physmem.rdQLenPdf::6 1
+system.physmem.rdQLenPdf::7 1
+system.physmem.rdQLenPdf::8 1
+system.physmem.rdQLenPdf::9 1
+system.physmem.rdQLenPdf::10 1
+system.physmem.rdQLenPdf::11 1
+system.physmem.rdQLenPdf::12 1
+system.physmem.rdQLenPdf::13 1
+system.physmem.rdQLenPdf::14 1
+system.physmem.rdQLenPdf::15 0
+system.physmem.rdQLenPdf::16 0
+system.physmem.rdQLenPdf::17 0
+system.physmem.rdQLenPdf::18 0
+system.physmem.rdQLenPdf::19 0
+system.physmem.rdQLenPdf::20 0
+system.physmem.rdQLenPdf::21 0
+system.physmem.rdQLenPdf::22 0
+system.physmem.rdQLenPdf::23 0
+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
+system.physmem.rdQLenPdf::26 0
+system.physmem.rdQLenPdf::27 0
+system.physmem.rdQLenPdf::28 0
+system.physmem.rdQLenPdf::29 0
+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 1
+system.physmem.wrQLenPdf::1 1
+system.physmem.wrQLenPdf::2 1
+system.physmem.wrQLenPdf::3 1
+system.physmem.wrQLenPdf::4 1
+system.physmem.wrQLenPdf::5 1
+system.physmem.wrQLenPdf::6 1
+system.physmem.wrQLenPdf::7 1
+system.physmem.wrQLenPdf::8 1
+system.physmem.wrQLenPdf::9 1
+system.physmem.wrQLenPdf::10 1
+system.physmem.wrQLenPdf::11 1
+system.physmem.wrQLenPdf::12 1
+system.physmem.wrQLenPdf::13 1
+system.physmem.wrQLenPdf::14 1
+system.physmem.wrQLenPdf::15 1874
+system.physmem.wrQLenPdf::16 2840
+system.physmem.wrQLenPdf::17 5990
+system.physmem.wrQLenPdf::18 5890
+system.physmem.wrQLenPdf::19 6230
+system.physmem.wrQLenPdf::20 5856
+system.physmem.wrQLenPdf::21 6225
+system.physmem.wrQLenPdf::22 6586
+system.physmem.wrQLenPdf::23 7530
+system.physmem.wrQLenPdf::24 7116
+system.physmem.wrQLenPdf::25 8216
+system.physmem.wrQLenPdf::26 8865
+system.physmem.wrQLenPdf::27 7091
+system.physmem.wrQLenPdf::28 6561
+system.physmem.wrQLenPdf::29 6513
+system.physmem.wrQLenPdf::30 6308
+system.physmem.wrQLenPdf::31 6117
+system.physmem.wrQLenPdf::32 6210
+system.physmem.wrQLenPdf::33 449
+system.physmem.wrQLenPdf::34 397
+system.physmem.wrQLenPdf::35 386
+system.physmem.wrQLenPdf::36 303
+system.physmem.wrQLenPdf::37 299
+system.physmem.wrQLenPdf::38 283
+system.physmem.wrQLenPdf::39 257
+system.physmem.wrQLenPdf::40 228
+system.physmem.wrQLenPdf::41 270
+system.physmem.wrQLenPdf::42 247
+system.physmem.wrQLenPdf::43 240
+system.physmem.wrQLenPdf::44 228
+system.physmem.wrQLenPdf::45 174
+system.physmem.wrQLenPdf::46 175
+system.physmem.wrQLenPdf::47 154
+system.physmem.wrQLenPdf::48 169
+system.physmem.wrQLenPdf::49 180
+system.physmem.wrQLenPdf::50 174
+system.physmem.wrQLenPdf::51 137
+system.physmem.wrQLenPdf::52 121
+system.physmem.wrQLenPdf::53 122
+system.physmem.wrQLenPdf::54 117
+system.physmem.wrQLenPdf::55 150
+system.physmem.wrQLenPdf::56 246
+system.physmem.wrQLenPdf::57 214
+system.physmem.wrQLenPdf::58 117
+system.physmem.wrQLenPdf::59 199
+system.physmem.wrQLenPdf::60 201
+system.physmem.wrQLenPdf::61 189
+system.physmem.wrQLenPdf::62 68
+system.physmem.wrQLenPdf::63 127
+system.physmem.bytesPerActivate::samples 57696
+system.physmem.bytesPerActivate::mean 317.478647
+system.physmem.bytesPerActivate::gmean 186.529934
+system.physmem.bytesPerActivate::stdev 335.962495
+system.physmem.bytesPerActivate::0-127 20572 35.66% 35.66%
+system.physmem.bytesPerActivate::128-255 14702 25.48% 61.14%
+system.physmem.bytesPerActivate::256-383 5653 9.80% 70.94%
+system.physmem.bytesPerActivate::384-511 3146 5.45% 76.39%
+system.physmem.bytesPerActivate::512-639 2423 4.20% 80.59%
+system.physmem.bytesPerActivate::640-767 1393 2.41% 83.00%
+system.physmem.bytesPerActivate::768-895 1271 2.20% 85.21%
+system.physmem.bytesPerActivate::896-1023 917 1.59% 86.79%
+system.physmem.bytesPerActivate::1024-1151 7619 13.21% 100.00%
+system.physmem.bytesPerActivate::total 57696
+system.physmem.rdPerTurnAround::samples 5793
+system.physmem.rdPerTurnAround::mean 28.926463
+system.physmem.rdPerTurnAround::stdev 588.910199
+system.physmem.rdPerTurnAround::0-2047 5792 99.98% 99.98%
+system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00%
+system.physmem.rdPerTurnAround::total 5793
+system.physmem.wrPerTurnAround::samples 5793
+system.physmem.wrPerTurnAround::mean 20.479026
+system.physmem.wrPerTurnAround::gmean 18.531275
+system.physmem.wrPerTurnAround::stdev 14.943169
+system.physmem.wrPerTurnAround::16-19 5068 87.48% 87.48%
+system.physmem.wrPerTurnAround::20-23 43 0.74% 88.23%
+system.physmem.wrPerTurnAround::24-27 40 0.69% 88.92%
+system.physmem.wrPerTurnAround::28-31 53 0.91% 89.83%
+system.physmem.wrPerTurnAround::32-35 289 4.99% 94.82%
+system.physmem.wrPerTurnAround::36-39 23 0.40% 95.22%
+system.physmem.wrPerTurnAround::40-43 16 0.28% 95.49%
+system.physmem.wrPerTurnAround::44-47 6 0.10% 95.60%
+system.physmem.wrPerTurnAround::48-51 5 0.09% 95.68%
+system.physmem.wrPerTurnAround::52-55 2 0.03% 95.72%
+system.physmem.wrPerTurnAround::56-59 1 0.02% 95.74%
+system.physmem.wrPerTurnAround::60-63 5 0.09% 95.82%
+system.physmem.wrPerTurnAround::64-67 158 2.73% 98.55%
+system.physmem.wrPerTurnAround::68-71 7 0.12% 98.67%
+system.physmem.wrPerTurnAround::72-75 5 0.09% 98.76%
+system.physmem.wrPerTurnAround::76-79 5 0.09% 98.84%
+system.physmem.wrPerTurnAround::80-83 8 0.14% 98.98%
+system.physmem.wrPerTurnAround::84-87 5 0.09% 99.07%
+system.physmem.wrPerTurnAround::96-99 2 0.03% 99.10%
+system.physmem.wrPerTurnAround::104-107 2 0.03% 99.14%
+system.physmem.wrPerTurnAround::108-111 9 0.16% 99.29%
+system.physmem.wrPerTurnAround::116-119 2 0.03% 99.33%
+system.physmem.wrPerTurnAround::120-123 1 0.02% 99.34%
+system.physmem.wrPerTurnAround::124-127 2 0.03% 99.38%
+system.physmem.wrPerTurnAround::128-131 8 0.14% 99.52%
+system.physmem.wrPerTurnAround::132-135 5 0.09% 99.60%
+system.physmem.wrPerTurnAround::136-139 5 0.09% 99.69%
+system.physmem.wrPerTurnAround::140-143 6 0.10% 99.79%
+system.physmem.wrPerTurnAround::144-147 1 0.02% 99.81%
+system.physmem.wrPerTurnAround::156-159 1 0.02% 99.83%
+system.physmem.wrPerTurnAround::160-163 4 0.07% 99.90%
+system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93%
+system.physmem.wrPerTurnAround::180-183 2 0.03% 99.97%
+system.physmem.wrPerTurnAround::184-187 1 0.02% 99.98%
+system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00%
+system.physmem.wrPerTurnAround::total 5793
+system.physmem.totQLat 4571022000
+system.physmem.totMemAccLat 7713015750
+system.physmem.totBusLat 837865000
+system.physmem.avgQLat 27277.80
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 46027.80
+system.physmem.avgRdBW 3.69
+system.physmem.avgWrBW 2.61
+system.physmem.avgRdBWSys 3.50
+system.physmem.avgWrBWSys 2.61
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 0.05
+system.physmem.busUtilRead 0.03
+system.physmem.busUtilWrite 0.02
+system.physmem.avgRdQLen 1.00
+system.physmem.avgWrQLen 24.59
+system.physmem.readRowHits 138588
+system.physmem.writeRowHits 89923
+system.physmem.readRowHitRate 82.70
+system.physmem.writeRowHitRate 75.79
+system.physmem.avgGap 10010492.43
+system.physmem.pageHitRate 79.84
+system.physmem_0.actEnergy 209923140
+system.physmem_0.preEnergy 111576795
+system.physmem_0.readEnergy 639494100
+system.physmem_0.writeEnergy 313387920
+system.physmem_0.refreshEnergy 6670687920.000002
+system.physmem_0.actBackEnergy 4809422880
+system.physmem_0.preBackEnergy 413752800
+system.physmem_0.actPowerDownEnergy 13946789640
+system.physmem_0.prePowerDownEnergy 9398763360
+system.physmem_0.selfRefreshEnergy 682626603840
+system.physmem_0.totalEnergy 719142677895
+system.physmem_0.averagePower 247.527383
+system.physmem_0.totalIdleTime 2893152718000
+system.physmem_0.memoryStateTime::IDLE 777067000
+system.physmem_0.memoryStateTime::REF 2836732000
+system.physmem_0.memoryStateTime::SREF 2838614964500
+system.physmem_0.memoryStateTime::PRE_PDN 24475941750
+system.physmem_0.memoryStateTime::ACT 8015385500
+system.physmem_0.memoryStateTime::ACT_PDN 30585446750
+system.physmem_1.actEnergy 202033440
+system.physmem_1.preEnergy 107379525
+system.physmem_1.readEnergy 556977120
+system.physmem_1.writeEnergy 305886780
+system.physmem_1.refreshEnergy 6674990400.000002
+system.physmem_1.actBackEnergy 4528240170
+system.physmem_1.preBackEnergy 413409600
+system.physmem_1.actPowerDownEnergy 13646578620
+system.physmem_1.prePowerDownEnergy 9540468000
+system.physmem_1.selfRefreshEnergy 682917113460
+system.physmem_1.totalEnergy 718894076985
+system.physmem_1.averagePower 247.441816
+system.physmem_1.totalIdleTime 2894296337500
+system.physmem_1.memoryStateTime::IDLE 785533000
+system.physmem_1.memoryStateTime::REF 2839260000
+system.physmem_1.memoryStateTime::SREF 2839524651500
+system.physmem_1.memoryStateTime::PRE_PDN 24844849250
+system.physmem_1.memoryStateTime::ACT 7384341000
+system.physmem_1.memoryStateTime::ACT_PDN 29926902750
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.nvmem.bytes_read::cpu.inst 20
+system.realview.nvmem.bytes_read::total 20
+system.realview.nvmem.bytes_inst_read::cpu.inst 20
+system.realview.nvmem.bytes_inst_read::total 20
+system.realview.nvmem.num_reads::cpu.inst 5
+system.realview.nvmem.num_reads::total 5
+system.realview.nvmem.bw_read::cpu.inst 7
+system.realview.nvmem.bw_read::total 7
+system.realview.nvmem.bw_inst_read::cpu.inst 7
+system.realview.nvmem.bw_inst_read::total 7
+system.realview.nvmem.bw_total::cpu.inst 7
+system.realview.nvmem.bw_total::total 7
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.cf0.dma_read_full_pages 0
+system.cf0.dma_read_bytes 1024
+system.cf0.dma_read_txs 1
+system.cf0.dma_write_full_pages 540
+system.cf0.dma_write_bytes 2318336
+system.cf0.dma_write_txs 631
+system.cpu_clk_domain.clock 500
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.hits 0
+system.cpu.dstage2_mmu.stage2_tlb.misses 0
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.cpu.dtb.walker.walks 9552
+system.cpu.dtb.walker.walksShort 9552
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1256
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8296
+system.cpu.dtb.walker.walkWaitTime::samples 9552
+system.cpu.dtb.walker.walkWaitTime::0 9552 100.00% 100.00%
+system.cpu.dtb.walker.walkWaitTime::total 9552
+system.cpu.dtb.walker.walkCompletionTime::samples 7388
+system.cpu.dtb.walker.walkCompletionTime::mean 10012.994044
+system.cpu.dtb.walker.walkCompletionTime::gmean 8463.653638
+system.cpu.dtb.walker.walkCompletionTime::stdev 6610.616521
+system.cpu.dtb.walker.walkCompletionTime::0-16383 6587 89.16% 89.16%
+system.cpu.dtb.walker.walkCompletionTime::16384-32767 796 10.77% 99.93%
+system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99%
+system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00%
+system.cpu.dtb.walker.walkCompletionTime::total 7388
+system.cpu.dtb.walker.walksPending::samples 1003066500
+system.cpu.dtb.walker.walksPending::0 1003066500 100.00% 100.00%
+system.cpu.dtb.walker.walksPending::total 1003066500
+system.cpu.dtb.walker.walkPageSizes::4K 6179 83.64% 83.64%
+system.cpu.dtb.walker.walkPageSizes::1M 1209 16.36% 100.00%
+system.cpu.dtb.walker.walkPageSizes::total 7388
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9552
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9552
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7388
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7388
+system.cpu.dtb.walker.walkRequestOrigin::total 16940
+system.cpu.dtb.inst_hits 0
+system.cpu.dtb.inst_misses 0
+system.cpu.dtb.read_hits 24517545
+system.cpu.dtb.read_misses 8139
+system.cpu.dtb.write_hits 19603622
+system.cpu.dtb.write_misses 1413
+system.cpu.dtb.flush_tlb 64
+system.cpu.dtb.flush_tlb_mva 917
+system.cpu.dtb.flush_tlb_mva_asid 0
+system.cpu.dtb.flush_tlb_asid 0
+system.cpu.dtb.flush_entries 4209
+system.cpu.dtb.align_faults 0
+system.cpu.dtb.prefetch_faults 1622
+system.cpu.dtb.domain_faults 0
+system.cpu.dtb.perms_faults 445
+system.cpu.dtb.read_accesses 24525684
+system.cpu.dtb.write_accesses 19605035
+system.cpu.dtb.inst_accesses 0
+system.cpu.dtb.hits 44121167
+system.cpu.dtb.misses 9552
+system.cpu.dtb.accesses 44130719
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.hits 0
+system.cpu.istage2_mmu.stage2_tlb.misses 0
+system.cpu.istage2_mmu.stage2_tlb.accesses 0
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.cpu.itb.walker.walks 4763
+system.cpu.itb.walker.walksShort 4763
+system.cpu.itb.walker.walksShortTerminationLevel::Level1 310
+system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453
+system.cpu.itb.walker.walkWaitTime::samples 4763
+system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00%
+system.cpu.itb.walker.walkWaitTime::total 4763
+system.cpu.itb.walker.walkCompletionTime::samples 3108
+system.cpu.itb.walker.walkCompletionTime::mean 10180.019305
+system.cpu.itb.walker.walkCompletionTime::gmean 8231.944722
+system.cpu.itb.walker.walkCompletionTime::stdev 7310.859984
+system.cpu.itb.walker.walkCompletionTime::0-8191 1821 58.59% 58.59%
+system.cpu.itb.walker.walkCompletionTime::8192-16383 761 24.49% 83.08%
+system.cpu.itb.walker.walkCompletionTime::16384-24575 524 16.86% 99.94%
+system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 99.97%
+system.cpu.itb.walker.walkCompletionTime::98304-106495 1 0.03% 100.00%
+system.cpu.itb.walker.walkCompletionTime::total 3108
+system.cpu.itb.walker.walksPending::samples 1002711000
+system.cpu.itb.walker.walksPending::0 1002711000 100.00% 100.00%
+system.cpu.itb.walker.walksPending::total 1002711000
+system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03%
+system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00%
+system.cpu.itb.walker.walkPageSizes::total 3108
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108
+system.cpu.itb.walker.walkRequestOrigin::total 7871
+system.cpu.itb.inst_hits 115547653
+system.cpu.itb.inst_misses 4763
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.flush_tlb 64
+system.cpu.itb.flush_tlb_mva 917
+system.cpu.itb.flush_tlb_mva_asid 0
+system.cpu.itb.flush_tlb_asid 0
+system.cpu.itb.flush_entries 2849
+system.cpu.itb.align_faults 0
+system.cpu.itb.prefetch_faults 0
+system.cpu.itb.domain_faults 0
+system.cpu.itb.perms_faults 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.inst_accesses 115552416
+system.cpu.itb.hits 115547653
+system.cpu.itb.misses 4763
+system.cpu.itb.accesses 115552416
+system.cpu.numPwrStateTransitions 6064
+system.cpu.pwrStateClkGateDist::samples 3032
+system.cpu.pwrStateClkGateDist::mean 887476232.352243
+system.cpu.pwrStateClkGateDist::stdev 17466728085.198059
+system.cpu.pwrStateClkGateDist::underflows 2968 97.89% 97.89%
+system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80%
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84%
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87%
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90%
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00%
+system.cpu.pwrStateClkGateDist::min_value 501
+system.cpu.pwrStateClkGateDist::max_value 499964549884
+system.cpu.pwrStateClkGateDist::total 3032
+system.cpu.pwrStateResidencyTicks::ON 214477601008
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2690827936492
+system.cpu.numCycles 5810611075
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.kern.inst.arm 0
+system.cpu.kern.inst.quiesce 3032
+system.cpu.committedInsts 112449853
+system.cpu.committedOps 135579871
+system.cpu.num_int_alu_accesses 119885571
+system.cpu.num_fp_alu_accesses 11290
+system.cpu.num_func_calls 9894238
+system.cpu.num_conditional_control_insts 15230085
+system.cpu.num_int_insts 119885571
+system.cpu.num_fp_insts 11290
+system.cpu.num_int_register_reads 218040023
+system.cpu.num_int_register_writes 82640385
+system.cpu.num_fp_register_reads 8578
+system.cpu.num_fp_register_writes 2716
+system.cpu.num_cc_register_reads 489710218
+system.cpu.num_cc_register_writes 51892450
+system.cpu.num_mem_refs 45401283
+system.cpu.num_load_insts 24839682
+system.cpu.num_store_insts 20561601
+system.cpu.num_idle_cycles 5381655872.982148
+system.cpu.num_busy_cycles 428955202.017852
+system.cpu.not_idle_fraction 0.073823
+system.cpu.idle_fraction 0.926177
+system.cpu.Branches 25918317
+system.cpu.op_class::No_OpClass 2337 0.00% 0.00%
+system.cpu.op_class::IntAlu 93173741 67.18% 67.18%
+system.cpu.op_class::IntMult 114521 0.08% 67.26%
+system.cpu.op_class::IntDiv 0 0.00% 67.26%
+system.cpu.op_class::FloatAdd 0 0.00% 67.26%
+system.cpu.op_class::FloatCmp 0 0.00% 67.26%
+system.cpu.op_class::FloatCvt 0 0.00% 67.26%
+system.cpu.op_class::FloatMult 0 0.00% 67.26%
+system.cpu.op_class::FloatMultAcc 0 0.00% 67.26%
+system.cpu.op_class::FloatDiv 0 0.00% 67.26%
+system.cpu.op_class::FloatMisc 0 0.00% 67.26%
+system.cpu.op_class::FloatSqrt 0 0.00% 67.26%
+system.cpu.op_class::SimdAdd 0 0.00% 67.26%
+system.cpu.op_class::SimdAddAcc 0 0.00% 67.26%
+system.cpu.op_class::SimdAlu 0 0.00% 67.26%
+system.cpu.op_class::SimdCmp 0 0.00% 67.26%
+system.cpu.op_class::SimdCvt 0 0.00% 67.26%
+system.cpu.op_class::SimdMisc 0 0.00% 67.26%
+system.cpu.op_class::SimdMult 0 0.00% 67.26%
+system.cpu.op_class::SimdMultAcc 0 0.00% 67.26%
+system.cpu.op_class::SimdShift 0 0.00% 67.26%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26%
+system.cpu.op_class::SimdSqrt 0 0.00% 67.26%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26%
+system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26%
+system.cpu.op_class::SimdFloatMisc 8435 0.01% 67.27%
+system.cpu.op_class::SimdFloatMult 0 0.00% 67.27%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.27%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.27%
+system.cpu.op_class::MemRead 24836974 17.91% 85.17%
+system.cpu.op_class::MemWrite 20553023 14.82% 99.99%
+system.cpu.op_class::FloatMemRead 2708 0.00% 99.99%
+system.cpu.op_class::FloatMemWrite 8578 0.01% 100.00%
+system.cpu.op_class::IprAccess 0 0.00% 100.00%
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class::total 138700317
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.cpu.dcache.tags.replacements 821089
+system.cpu.dcache.tags.tagsinuse 511.816170
+system.cpu.dcache.tags.total_refs 43228313
+system.cpu.dcache.tags.sampled_refs 821601
+system.cpu.dcache.tags.avg_refs 52.614728
+system.cpu.dcache.tags.warmup_cycle 1078145500
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.816170
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999641
+system.cpu.dcache.tags.occ_percent::total 0.999641
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 59
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 356
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 96
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 1
+system.cpu.dcache.tags.occ_task_id_percent::1024 1
+system.cpu.dcache.tags.tag_accesses 177089446
+system.cpu.dcache.tags.data_accesses 177089446
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.cpu.dcache.ReadReq_hits::cpu.data 23108878
+system.cpu.dcache.ReadReq_hits::total 23108878
+system.cpu.dcache.WriteReq_hits::cpu.data 18821001
+system.cpu.dcache.WriteReq_hits::total 18821001
+system.cpu.dcache.SoftPFReq_hits::cpu.data 392443
+system.cpu.dcache.SoftPFReq_hits::total 392443
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 443073
+system.cpu.dcache.LoadLockedReq_hits::total 443073
+system.cpu.dcache.StoreCondReq_hits::cpu.data 460108
+system.cpu.dcache.StoreCondReq_hits::total 460108
+system.cpu.dcache.demand_hits::cpu.data 41929879
+system.cpu.dcache.demand_hits::total 41929879
+system.cpu.dcache.overall_hits::cpu.data 42322322
+system.cpu.dcache.overall_hits::total 42322322
+system.cpu.dcache.ReadReq_misses::cpu.data 401094
+system.cpu.dcache.ReadReq_misses::total 401094
+system.cpu.dcache.WriteReq_misses::cpu.data 298865
+system.cpu.dcache.WriteReq_misses::total 298865
+system.cpu.dcache.SoftPFReq_misses::cpu.data 118684
+system.cpu.dcache.SoftPFReq_misses::total 118684
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 22806
+system.cpu.dcache.LoadLockedReq_misses::total 22806
+system.cpu.dcache.StoreCondReq_misses::cpu.data 2
+system.cpu.dcache.StoreCondReq_misses::total 2
+system.cpu.dcache.demand_misses::cpu.data 699959
+system.cpu.dcache.demand_misses::total 699959
+system.cpu.dcache.overall_misses::cpu.data 818643
+system.cpu.dcache.overall_misses::total 818643
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 6435554000
+system.cpu.dcache.ReadReq_miss_latency::total 6435554000
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 14440564500
+system.cpu.dcache.WriteReq_miss_latency::total 14440564500
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297902000
+system.cpu.dcache.LoadLockedReq_miss_latency::total 297902000
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000
+system.cpu.dcache.StoreCondReq_miss_latency::total 166000
+system.cpu.dcache.demand_miss_latency::cpu.data 20876118500
+system.cpu.dcache.demand_miss_latency::total 20876118500
+system.cpu.dcache.overall_miss_latency::cpu.data 20876118500
+system.cpu.dcache.overall_miss_latency::total 20876118500
+system.cpu.dcache.ReadReq_accesses::cpu.data 23509972
+system.cpu.dcache.ReadReq_accesses::total 23509972
+system.cpu.dcache.WriteReq_accesses::cpu.data 19119866
+system.cpu.dcache.WriteReq_accesses::total 19119866
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 511127
+system.cpu.dcache.SoftPFReq_accesses::total 511127
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465879
+system.cpu.dcache.LoadLockedReq_accesses::total 465879
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 460110
+system.cpu.dcache.StoreCondReq_accesses::total 460110
+system.cpu.dcache.demand_accesses::cpu.data 42629838
+system.cpu.dcache.demand_accesses::total 42629838
+system.cpu.dcache.overall_accesses::cpu.data 43140965
+system.cpu.dcache.overall_accesses::total 43140965
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017061
+system.cpu.dcache.ReadReq_miss_rate::total 0.017061
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631
+system.cpu.dcache.WriteReq_miss_rate::total 0.015631
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.232201
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.232201
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048953
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048953
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004
+system.cpu.dcache.demand_miss_rate::cpu.data 0.016419
+system.cpu.dcache.demand_miss_rate::total 0.016419
+system.cpu.dcache.overall_miss_rate::cpu.data 0.018976
+system.cpu.dcache.overall_miss_rate::total 0.018976
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16045.001920
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16045.001920
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48318.018169
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48318.018169
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13062.439709
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13062.439709
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29824.773308
+system.cpu.dcache.demand_avg_miss_latency::total 29824.773308
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25500.881947
+system.cpu.dcache.overall_avg_miss_latency::total 25500.881947
+system.cpu.dcache.blocked_cycles::no_mshrs 76
+system.cpu.dcache.blocked_cycles::no_targets 0
+system.cpu.dcache.blocked::no_mshrs 19
+system.cpu.dcache.blocked::no_targets 0
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 4
+system.cpu.dcache.avg_blocked_cycles::no_targets nan
+system.cpu.dcache.writebacks::writebacks 685560
+system.cpu.dcache.writebacks::total 685560
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 708
+system.cpu.dcache.ReadReq_mshr_hits::total 708
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14280
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 14280
+system.cpu.dcache.demand_mshr_hits::cpu.data 708
+system.cpu.dcache.demand_mshr_hits::total 708
+system.cpu.dcache.overall_mshr_hits::cpu.data 708
+system.cpu.dcache.overall_mshr_hits::total 708
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400386
+system.cpu.dcache.ReadReq_mshr_misses::total 400386
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298865
+system.cpu.dcache.WriteReq_mshr_misses::total 298865
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116661
+system.cpu.dcache.SoftPFReq_mshr_misses::total 116661
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8526
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 8526
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2
+system.cpu.dcache.StoreCondReq_mshr_misses::total 2
+system.cpu.dcache.demand_mshr_misses::cpu.data 699251
+system.cpu.dcache.demand_mshr_misses::total 699251
+system.cpu.dcache.overall_mshr_misses::cpu.data 815912
+system.cpu.dcache.overall_mshr_misses::total 815912
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31118
+system.cpu.dcache.ReadReq_mshr_uncacheable::total 31118
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27579
+system.cpu.dcache.WriteReq_mshr_uncacheable::total 27579
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58697
+system.cpu.dcache.overall_mshr_uncacheable_misses::total 58697
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6009948500
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 6009948500
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14141699500
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 14141699500
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1587332500
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1587332500
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118971500
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118971500
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20151648000
+system.cpu.dcache.demand_mshr_miss_latency::total 20151648000
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21738980500
+system.cpu.dcache.overall_mshr_miss_latency::total 21738980500
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281996500
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281996500
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281996500
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281996500
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017030
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017030
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228243
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228243
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018301
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018301
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016403
+system.cpu.dcache.demand_mshr_miss_rate::total 0.016403
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018913
+system.cpu.dcache.overall_mshr_miss_rate::total 0.018913
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15010.386227
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15010.386227
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47318.018169
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47318.018169
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13606.368024
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13606.368024
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13953.964344
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13953.964344
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28818.904800
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28818.904800
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26643.780824
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26643.780824
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201876.614821
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201876.614821
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107024.149445
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107024.149445
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.cpu.icache.tags.replacements 1699808
+system.cpu.icache.tags.tagsinuse 510.693082
+system.cpu.icache.tags.total_refs 113847327
+system.cpu.icache.tags.sampled_refs 1700320
+system.cpu.icache.tags.avg_refs 66.956412
+system.cpu.icache.tags.warmup_cycle 26307743500
+system.cpu.icache.tags.occ_blocks::cpu.inst 510.693082
+system.cpu.icache.tags.occ_percent::cpu.inst 0.997447
+system.cpu.icache.tags.occ_percent::total 0.997447
+system.cpu.icache.tags.occ_task_id_blocks::1024 512
+system.cpu.icache.tags.age_task_id_blocks_1024::0 45
+system.cpu.icache.tags.age_task_id_blocks_1024::1 212
+system.cpu.icache.tags.age_task_id_blocks_1024::2 246
+system.cpu.icache.tags.age_task_id_blocks_1024::3 9
+system.cpu.icache.tags.occ_task_id_percent::1024 1
+system.cpu.icache.tags.tag_accesses 117247979
+system.cpu.icache.tags.data_accesses 117247979
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.cpu.icache.ReadReq_hits::cpu.inst 113847327
+system.cpu.icache.ReadReq_hits::total 113847327
+system.cpu.icache.demand_hits::cpu.inst 113847327
+system.cpu.icache.demand_hits::total 113847327
+system.cpu.icache.overall_hits::cpu.inst 113847327
+system.cpu.icache.overall_hits::total 113847327
+system.cpu.icache.ReadReq_misses::cpu.inst 1700326
+system.cpu.icache.ReadReq_misses::total 1700326
+system.cpu.icache.demand_misses::cpu.inst 1700326
+system.cpu.icache.demand_misses::total 1700326
+system.cpu.icache.overall_misses::cpu.inst 1700326
+system.cpu.icache.overall_misses::total 1700326
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 24041505000
+system.cpu.icache.ReadReq_miss_latency::total 24041505000
+system.cpu.icache.demand_miss_latency::cpu.inst 24041505000
+system.cpu.icache.demand_miss_latency::total 24041505000
+system.cpu.icache.overall_miss_latency::cpu.inst 24041505000
+system.cpu.icache.overall_miss_latency::total 24041505000
+system.cpu.icache.ReadReq_accesses::cpu.inst 115547653
+system.cpu.icache.ReadReq_accesses::total 115547653
+system.cpu.icache.demand_accesses::cpu.inst 115547653
+system.cpu.icache.demand_accesses::total 115547653
+system.cpu.icache.overall_accesses::cpu.inst 115547653
+system.cpu.icache.overall_accesses::total 115547653
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014715
+system.cpu.icache.ReadReq_miss_rate::total 0.014715
+system.cpu.icache.demand_miss_rate::cpu.inst 0.014715
+system.cpu.icache.demand_miss_rate::total 0.014715
+system.cpu.icache.overall_miss_rate::cpu.inst 0.014715
+system.cpu.icache.overall_miss_rate::total 0.014715
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14139.350336
+system.cpu.icache.ReadReq_avg_miss_latency::total 14139.350336
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14139.350336
+system.cpu.icache.demand_avg_miss_latency::total 14139.350336
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14139.350336
+system.cpu.icache.overall_avg_miss_latency::total 14139.350336
+system.cpu.icache.blocked_cycles::no_mshrs 0
+system.cpu.icache.blocked_cycles::no_targets 0
+system.cpu.icache.blocked::no_mshrs 0
+system.cpu.icache.blocked::no_targets 0
+system.cpu.icache.avg_blocked_cycles::no_mshrs nan
+system.cpu.icache.avg_blocked_cycles::no_targets nan
+system.cpu.icache.writebacks::writebacks 1699808
+system.cpu.icache.writebacks::total 1699808
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700326
+system.cpu.icache.ReadReq_mshr_misses::total 1700326
+system.cpu.icache.demand_mshr_misses::cpu.inst 1700326
+system.cpu.icache.demand_mshr_misses::total 1700326
+system.cpu.icache.overall_mshr_misses::cpu.inst 1700326
+system.cpu.icache.overall_mshr_misses::total 1700326
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022
+system.cpu.icache.ReadReq_mshr_uncacheable::total 9022
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022
+system.cpu.icache.overall_mshr_uncacheable_misses::total 9022
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22341179000
+system.cpu.icache.ReadReq_mshr_miss_latency::total 22341179000
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22341179000
+system.cpu.icache.demand_mshr_miss_latency::total 22341179000
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22341179000
+system.cpu.icache.overall_mshr_miss_latency::total 22341179000
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 745203000
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 745203000
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 745203000
+system.cpu.icache.overall_mshr_uncacheable_latency::total 745203000
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014715
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014715
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014715
+system.cpu.icache.demand_mshr_miss_rate::total 0.014715
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014715
+system.cpu.icache.overall_mshr_miss_rate::total 0.014715
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13139.350336
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13139.350336
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13139.350336
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13139.350336
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13139.350336
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13139.350336
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82598.426070
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82598.426070
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82598.426070
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82598.426070
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.cpu.l2cache.tags.replacements 88597
+system.cpu.l2cache.tags.tagsinuse 65011.983372
+system.cpu.l2cache.tags.total_refs 4853512
+system.cpu.l2cache.tags.sampled_refs 154024
+system.cpu.l2cache.tags.avg_refs 31.511401
+system.cpu.l2cache.tags.warmup_cycle 147534324000
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.050681
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.041156
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 9633.139334
+system.cpu.l2cache.tags.occ_blocks::cpu.data 55375.752201
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000047
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.146990
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.844967
+system.cpu.l2cache.tags.occ_percent::total 0.992004
+system.cpu.l2cache.tags.occ_task_id_blocks::1023 5
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 65422
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 76
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4348
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60997
+system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998260
+system.cpu.l2cache.tags.tag_accesses 40271303
+system.cpu.l2cache.tags.data_accesses 40271303
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5062
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2684
+system.cpu.l2cache.ReadReq_hits::total 7746
+system.cpu.l2cache.WritebackDirty_hits::writebacks 685560
+system.cpu.l2cache.WritebackDirty_hits::total 685560
+system.cpu.l2cache.WritebackClean_hits::writebacks 1667530
+system.cpu.l2cache.WritebackClean_hits::total 1667530
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 2789
+system.cpu.l2cache.UpgradeReq_hits::total 2789
+system.cpu.l2cache.ReadExReq_hits::cpu.data 167631
+system.cpu.l2cache.ReadExReq_hits::total 167631
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682332
+system.cpu.l2cache.ReadCleanReq_hits::total 1682332
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513501
+system.cpu.l2cache.ReadSharedReq_hits::total 513501
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 5062
+system.cpu.l2cache.demand_hits::cpu.itb.walker 2684
+system.cpu.l2cache.demand_hits::cpu.inst 1682332
+system.cpu.l2cache.demand_hits::cpu.data 681132
+system.cpu.l2cache.demand_hits::total 2371210
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 5062
+system.cpu.l2cache.overall_hits::cpu.itb.walker 2684
+system.cpu.l2cache.overall_hits::cpu.inst 1682332
+system.cpu.l2cache.overall_hits::cpu.data 681132
+system.cpu.l2cache.overall_hits::total 2371210
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2
+system.cpu.l2cache.ReadReq_misses::total 9
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 19
+system.cpu.l2cache.UpgradeReq_misses::total 19
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2
+system.cpu.l2cache.SCUpgradeReq_misses::total 2
+system.cpu.l2cache.ReadExReq_misses::cpu.data 128426
+system.cpu.l2cache.ReadExReq_misses::total 128426
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17977
+system.cpu.l2cache.ReadCleanReq_misses::total 17977
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12072
+system.cpu.l2cache.ReadSharedReq_misses::total 12072
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 7
+system.cpu.l2cache.demand_misses::cpu.itb.walker 2
+system.cpu.l2cache.demand_misses::cpu.inst 17977
+system.cpu.l2cache.demand_misses::cpu.data 140498
+system.cpu.l2cache.demand_misses::total 158484
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 7
+system.cpu.l2cache.overall_misses::cpu.itb.walker 2
+system.cpu.l2cache.overall_misses::cpu.inst 17977
+system.cpu.l2cache.overall_misses::cpu.data 140498
+system.cpu.l2cache.overall_misses::total 158484
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1154000
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 180000
+system.cpu.l2cache.ReadReq_miss_latency::total 1334000
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 553500
+system.cpu.l2cache.UpgradeReq_miss_latency::total 553500
+system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 161000
+system.cpu.l2cache.SCUpgradeReq_miss_latency::total 161000
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11899868500
+system.cpu.l2cache.ReadExReq_miss_latency::total 11899868500
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2066210500
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 2066210500
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1518806000
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 1518806000
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1154000
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 180000
+system.cpu.l2cache.demand_miss_latency::cpu.inst 2066210500
+system.cpu.l2cache.demand_miss_latency::cpu.data 13418674500
+system.cpu.l2cache.demand_miss_latency::total 15486219000
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1154000
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 180000
+system.cpu.l2cache.overall_miss_latency::cpu.inst 2066210500
+system.cpu.l2cache.overall_miss_latency::cpu.data 13418674500
+system.cpu.l2cache.overall_miss_latency::total 15486219000
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5069
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2686
+system.cpu.l2cache.ReadReq_accesses::total 7755
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 685560
+system.cpu.l2cache.WritebackDirty_accesses::total 685560
+system.cpu.l2cache.WritebackClean_accesses::writebacks 1667530
+system.cpu.l2cache.WritebackClean_accesses::total 1667530
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2808
+system.cpu.l2cache.UpgradeReq_accesses::total 2808
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2
+system.cpu.l2cache.SCUpgradeReq_accesses::total 2
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 296057
+system.cpu.l2cache.ReadExReq_accesses::total 296057
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700309
+system.cpu.l2cache.ReadCleanReq_accesses::total 1700309
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525573
+system.cpu.l2cache.ReadSharedReq_accesses::total 525573
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5069
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 2686
+system.cpu.l2cache.demand_accesses::cpu.inst 1700309
+system.cpu.l2cache.demand_accesses::cpu.data 821630
+system.cpu.l2cache.demand_accesses::total 2529694
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5069
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 2686
+system.cpu.l2cache.overall_accesses::cpu.inst 1700309
+system.cpu.l2cache.overall_accesses::cpu.data 821630
+system.cpu.l2cache.overall_accesses::total 2529694
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001381
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000745
+system.cpu.l2cache.ReadReq_miss_rate::total 0.001161
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.006766
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.006766
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.433788
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.433788
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010573
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010573
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.022969
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.022969
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001381
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000745
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010573
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.170999
+system.cpu.l2cache.demand_miss_rate::total 0.062649
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001381
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000745
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010573
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.170999
+system.cpu.l2cache.overall_miss_rate::total 0.062649
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 164857.142857
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 90000
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 148222.222222
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29131.578947
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29131.578947
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92659.340788
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92659.340788
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114936.335317
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114936.335317
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125812.292909
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125812.292909
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 164857.142857
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 90000
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114936.335317
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95507.939615
+system.cpu.l2cache.demand_avg_miss_latency::total 97714.715681
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 164857.142857
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 90000
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114936.335317
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95507.939615
+system.cpu.l2cache.overall_avg_miss_latency::total 97714.715681
+system.cpu.l2cache.blocked_cycles::no_mshrs 0
+system.cpu.l2cache.blocked_cycles::no_targets 0
+system.cpu.l2cache.blocked::no_mshrs 0
+system.cpu.l2cache.blocked::no_targets 0
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu.l2cache.writebacks::writebacks 81970
+system.cpu.l2cache.writebacks::total 81970
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2
+system.cpu.l2cache.ReadReq_mshr_misses::total 9
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 19
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 19
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128426
+system.cpu.l2cache.ReadExReq_mshr_misses::total 128426
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17977
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17977
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12072
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12072
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 17977
+system.cpu.l2cache.demand_mshr_misses::cpu.data 140498
+system.cpu.l2cache.demand_mshr_misses::total 158484
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 17977
+system.cpu.l2cache.overall_mshr_misses::cpu.data 140498
+system.cpu.l2cache.overall_mshr_misses::total 158484
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31118
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40140
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27579
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27579
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58697
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67719
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1084000
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 160000
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1244000
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 363500
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 363500
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 141000
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 141000
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10615608500
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10615608500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1886440500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1886440500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1398086000
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1398086000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1084000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 160000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1886440500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12013694500
+system.cpu.l2cache.demand_mshr_miss_latency::total 13901379000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1084000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 160000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1886440500
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12013694500
+system.cpu.l2cache.overall_mshr_miss_latency::total 13901379000
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 632428000
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5892901500
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6525329500
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 632428000
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5892901500
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6525329500
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001381
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000745
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001161
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.006766
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.006766
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.433788
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.433788
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010573
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010573
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.022969
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.022969
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001381
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000745
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010573
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170999
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.062649
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001381
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000745
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010573
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170999
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.062649
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 80000
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138222.222222
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19131.578947
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19131.578947
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82659.340788
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82659.340788
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104936.335317
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104936.335317
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115812.292909
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115812.292909
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 80000
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104936.335317
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85507.939615
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87714.715681
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 80000
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104936.335317
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85507.939615
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87714.715681
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70098.426070
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189372.758532
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162564.262581
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70098.426070
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100395.275738
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96358.916995
+system.cpu.toL2Bus.snoop_filter.tot_requests 5064980
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543036
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39292
+system.cpu.toL2Bus.snoop_filter.tot_snoops 227
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 227
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.cpu.toL2Bus.trans_dist::ReadReq 67204
+system.cpu.toL2Bus.trans_dist::ReadResp 2293294
+system.cpu.toL2Bus.trans_dist::WriteReq 27579
+system.cpu.toL2Bus.trans_dist::WriteResp 27579
+system.cpu.toL2Bus.trans_dist::WritebackDirty 767530
+system.cpu.toL2Bus.trans_dist::WritebackClean 1699808
+system.cpu.toL2Bus.trans_dist::CleanEvict 142156
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2808
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2810
+system.cpu.toL2Bus.trans_dist::ReadExReq 296057
+system.cpu.toL2Bus.trans_dist::ReadExResp 296057
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700326
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 525772
+system.cpu.toL2Bus.trans_dist::InvalidateReq 4351
+system.cpu.toL2Bus.trans_dist::InvalidateResp 14
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5118487
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2587568
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11902
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22917
+system.cpu.toL2Bus.pkt_count::total 7740874
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217643576
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96655427
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10744
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 20276
+system.cpu.toL2Bus.pkt_size::total 314330023
+system.cpu.toL2Bus.snoops 112678
+system.cpu.toL2Bus.snoopTraffic 5336628
+system.cpu.toL2Bus.snoop_fanout::samples 2712696
+system.cpu.toL2Bus.snoop_fanout::mean 0.021694
+system.cpu.toL2Bus.snoop_fanout::stdev 0.145681
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 2653848 97.83% 97.83%
+system.cpu.toL2Bus.snoop_fanout::1 58848 2.17% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 1
+system.cpu.toL2Bus.snoop_fanout::total 2712696
+system.cpu.toL2Bus.reqLayer0.occupancy 4969380500
+system.cpu.toL2Bus.reqLayer0.utilization 0.2
+system.cpu.toL2Bus.snoopLayer0.occupancy 354876
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer0.occupancy 2559511000
+system.cpu.toL2Bus.respLayer0.utilization 0.1
+system.cpu.toL2Bus.respLayer1.occupancy 1278757500
+system.cpu.toL2Bus.respLayer1.utilization 0.0
+system.cpu.toL2Bus.respLayer2.occupancy 9216000
+system.cpu.toL2Bus.respLayer2.utilization 0.0
+system.cpu.toL2Bus.respLayer3.occupancy 17848000
+system.cpu.toL2Bus.respLayer3.utilization 0.0
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.iobus.trans_dist::ReadReq 30149
+system.iobus.trans_dist::ReadResp 30149
+system.iobus.trans_dist::WriteReq 59014
+system.iobus.trans_dist::WriteResp 59014
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268
+system.iobus.pkt_count_system.bridge.master::total 105458
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72868
+system.iobus.pkt_count_system.realview.ide.dma::total 72868
+system.iobus.pkt_count::total 178326
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536
+system.iobus.pkt_size_system.bridge.master::total 159115
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320912
+system.iobus.pkt_size_system.realview.ide.dma::total 2320912
+system.iobus.pkt_size::total 2480027
+system.iobus.reqLayer0.occupancy 46336500
+system.iobus.reqLayer0.utilization 0.0
+system.iobus.reqLayer1.occupancy 97000
+system.iobus.reqLayer1.utilization 0.0
+system.iobus.reqLayer2.occupancy 338000
+system.iobus.reqLayer2.utilization 0.0
+system.iobus.reqLayer3.occupancy 29500
+system.iobus.reqLayer3.utilization 0.0
+system.iobus.reqLayer4.occupancy 15500
+system.iobus.reqLayer4.utilization 0.0
+system.iobus.reqLayer7.occupancy 91500
+system.iobus.reqLayer7.utilization 0.0
+system.iobus.reqLayer8.occupancy 630500
+system.iobus.reqLayer8.utilization 0.0
+system.iobus.reqLayer10.occupancy 21000
+system.iobus.reqLayer10.utilization 0.0
+system.iobus.reqLayer13.occupancy 11500
+system.iobus.reqLayer13.utilization 0.0
+system.iobus.reqLayer14.occupancy 12000
+system.iobus.reqLayer14.utilization 0.0
+system.iobus.reqLayer15.occupancy 12000
+system.iobus.reqLayer15.utilization 0.0
+system.iobus.reqLayer16.occupancy 52500
+system.iobus.reqLayer16.utilization 0.0
+system.iobus.reqLayer17.occupancy 12000
+system.iobus.reqLayer17.utilization 0.0
+system.iobus.reqLayer18.occupancy 11500
+system.iobus.reqLayer18.utilization 0.0
+system.iobus.reqLayer19.occupancy 2000
+system.iobus.reqLayer19.utilization 0.0
+system.iobus.reqLayer20.occupancy 9000
+system.iobus.reqLayer20.utilization 0.0
+system.iobus.reqLayer21.occupancy 11500
+system.iobus.reqLayer21.utilization 0.0
+system.iobus.reqLayer23.occupancy 6289000
+system.iobus.reqLayer23.utilization 0.0
+system.iobus.reqLayer24.occupancy 36469500
+system.iobus.reqLayer24.utilization 0.0
+system.iobus.reqLayer25.occupancy 187505138
+system.iobus.reqLayer25.utilization 0.0
+system.iobus.respLayer0.occupancy 82668000
+system.iobus.respLayer0.utilization 0.0
+system.iobus.respLayer3.occupancy 36692000
+system.iobus.respLayer3.utilization 0.0
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.iocache.tags.replacements 36400
+system.iocache.tags.tagsinuse 1.079831
+system.iocache.tags.total_refs 0
+system.iocache.tags.sampled_refs 36416
+system.iocache.tags.avg_refs 0
+system.iocache.tags.warmup_cycle 310617748000
+system.iocache.tags.occ_blocks::realview.ide 1.079831
+system.iocache.tags.occ_percent::realview.ide 0.067489
+system.iocache.tags.occ_percent::total 0.067489
+system.iocache.tags.occ_task_id_blocks::1023 16
+system.iocache.tags.age_task_id_blocks_1023::3 16
+system.iocache.tags.occ_task_id_percent::1023 1
+system.iocache.tags.tag_accesses 327906
+system.iocache.tags.data_accesses 327906
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.iocache.ReadReq_misses::realview.ide 210
+system.iocache.ReadReq_misses::total 210
+system.iocache.WriteLineReq_misses::realview.ide 36224
+system.iocache.WriteLineReq_misses::total 36224
+system.iocache.demand_misses::realview.ide 36434
+system.iocache.demand_misses::total 36434
+system.iocache.overall_misses::realview.ide 36434
+system.iocache.overall_misses::total 36434
+system.iocache.ReadReq_miss_latency::realview.ide 34066376
+system.iocache.ReadReq_miss_latency::total 34066376
+system.iocache.WriteLineReq_miss_latency::realview.ide 4376106762
+system.iocache.WriteLineReq_miss_latency::total 4376106762
+system.iocache.demand_miss_latency::realview.ide 4410173138
+system.iocache.demand_miss_latency::total 4410173138
+system.iocache.overall_miss_latency::realview.ide 4410173138
+system.iocache.overall_miss_latency::total 4410173138
+system.iocache.ReadReq_accesses::realview.ide 210
+system.iocache.ReadReq_accesses::total 210
+system.iocache.WriteLineReq_accesses::realview.ide 36224
+system.iocache.WriteLineReq_accesses::total 36224
+system.iocache.demand_accesses::realview.ide 36434
+system.iocache.demand_accesses::total 36434
+system.iocache.overall_accesses::realview.ide 36434
+system.iocache.overall_accesses::total 36434
+system.iocache.ReadReq_miss_rate::realview.ide 1
+system.iocache.ReadReq_miss_rate::total 1
+system.iocache.WriteLineReq_miss_rate::realview.ide 1
+system.iocache.WriteLineReq_miss_rate::total 1
+system.iocache.demand_miss_rate::realview.ide 1
+system.iocache.demand_miss_rate::total 1
+system.iocache.overall_miss_rate::realview.ide 1
+system.iocache.overall_miss_rate::total 1
+system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095
+system.iocache.ReadReq_avg_miss_latency::total 162220.838095
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120806.834198
+system.iocache.WriteLineReq_avg_miss_latency::total 120806.834198
+system.iocache.demand_avg_miss_latency::realview.ide 121045.538179
+system.iocache.demand_avg_miss_latency::total 121045.538179
+system.iocache.overall_avg_miss_latency::realview.ide 121045.538179
+system.iocache.overall_avg_miss_latency::total 121045.538179
+system.iocache.blocked_cycles::no_mshrs 208
+system.iocache.blocked_cycles::no_targets 0
+system.iocache.blocked::no_mshrs 4
+system.iocache.blocked::no_targets 0
+system.iocache.avg_blocked_cycles::no_mshrs 52
+system.iocache.avg_blocked_cycles::no_targets nan
+system.iocache.writebacks::writebacks 36190
+system.iocache.writebacks::total 36190
+system.iocache.ReadReq_mshr_misses::realview.ide 210
+system.iocache.ReadReq_mshr_misses::total 210
+system.iocache.WriteLineReq_mshr_misses::realview.ide 36224
+system.iocache.WriteLineReq_mshr_misses::total 36224
+system.iocache.demand_mshr_misses::realview.ide 36434
+system.iocache.demand_mshr_misses::total 36434
+system.iocache.overall_mshr_misses::realview.ide 36434
+system.iocache.overall_mshr_misses::total 36434
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 23566376
+system.iocache.ReadReq_mshr_miss_latency::total 23566376
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2563140504
+system.iocache.WriteLineReq_mshr_miss_latency::total 2563140504
+system.iocache.demand_mshr_miss_latency::realview.ide 2586706880
+system.iocache.demand_mshr_miss_latency::total 2586706880
+system.iocache.overall_mshr_miss_latency::realview.ide 2586706880
+system.iocache.overall_mshr_miss_latency::total 2586706880
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1
+system.iocache.ReadReq_mshr_miss_rate::total 1
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1
+system.iocache.WriteLineReq_mshr_miss_rate::total 1
+system.iocache.demand_mshr_miss_rate::realview.ide 1
+system.iocache.demand_mshr_miss_rate::total 1
+system.iocache.overall_mshr_miss_rate::realview.ide 1
+system.iocache.overall_mshr_miss_rate::total 1
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095
+system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70758.074867
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70758.074867
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 70997.059889
+system.iocache.demand_avg_mshr_miss_latency::total 70997.059889
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 70997.059889
+system.iocache.overall_avg_mshr_miss_latency::total 70997.059889
+system.membus.snoop_filter.tot_requests 319999
+system.membus.snoop_filter.hit_single_requests 129537
+system.membus.snoop_filter.hit_multi_requests 496
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.membus.trans_dist::ReadReq 40140
+system.membus.trans_dist::ReadResp 70408
+system.membus.trans_dist::WriteReq 27579
+system.membus.trans_dist::WriteResp 27579
+system.membus.trans_dist::WritebackDirty 118160
+system.membus.trans_dist::CleanEvict 6837
+system.membus.trans_dist::UpgradeReq 128
+system.membus.trans_dist::SCUpgradeReq 2
+system.membus.trans_dist::UpgradeResp 2
+system.membus.trans_dist::ReadExReq 128317
+system.membus.trans_dist::ReadExResp 128317
+system.membus.trans_dist::ReadSharedReq 30268
+system.membus.trans_dist::InvalidateReq 36224
+system.membus.trans_dist::InvalidateResp 4315
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105458
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2064
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 433106
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 540638
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72849
+system.membus.pkt_count_system.iocache.mem_side::total 72849
+system.membus.pkt_count::total 613487
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159115
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4128
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15420220
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15583483
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120
+system.membus.pkt_size_system.iocache.mem_side::total 2317120
+system.membus.pkt_size::total 17900603
+system.membus.snoops 4789
+system.membus.snoopTraffic 30208
+system.membus.snoop_fanout::samples 262658
+system.membus.snoop_fanout::mean 0.018385
+system.membus.snoop_fanout::stdev 0.134340
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 257829 98.16% 98.16%
+system.membus.snoop_fanout::1 4829 1.84% 100.00%
+system.membus.snoop_fanout::2 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 1
+system.membus.snoop_fanout::total 262658
+system.membus.reqLayer0.occupancy 90452000
+system.membus.reqLayer0.utilization 0.0
+system.membus.reqLayer1.occupancy 7500
+system.membus.reqLayer1.utilization 0.0
+system.membus.reqLayer2.occupancy 1690500
+system.membus.reqLayer2.utilization 0.0
+system.membus.reqLayer5.occupancy 822823297
+system.membus.reqLayer5.utilization 0.0
+system.membus.respLayer2.occupancy 948595750
+system.membus.respLayer2.utilization 0.0
+system.membus.respLayer3.occupancy 5614930
+system.membus.respLayer3.utilization 0.0
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.dcc.osc_cpu.clock 16667
+system.realview.dcc.osc_ddr.clock 25000
+system.realview.dcc.osc_hsbm.clock 25000
+system.realview.dcc.osc_pxl.clock 42105
+system.realview.dcc.osc_smb.clock 20000
+system.realview.dcc.osc_sys.clock 16667
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.ethernet.descDMAReads 0
+system.realview.ethernet.descDMAWrites 0
+system.realview.ethernet.descDmaReadBytes 0
+system.realview.ethernet.descDmaWriteBytes 0
+system.realview.ethernet.postedSwi 0
+system.realview.ethernet.coalescedSwi nan
+system.realview.ethernet.totalSwi 0
+system.realview.ethernet.postedRxIdle 0
+system.realview.ethernet.coalescedRxIdle nan
+system.realview.ethernet.totalRxIdle 0
+system.realview.ethernet.postedRxOk 0
+system.realview.ethernet.coalescedRxOk nan
+system.realview.ethernet.totalRxOk 0
+system.realview.ethernet.postedRxDesc 0
+system.realview.ethernet.coalescedRxDesc nan
+system.realview.ethernet.totalRxDesc 0
+system.realview.ethernet.postedTxOk 0
+system.realview.ethernet.coalescedTxOk nan
+system.realview.ethernet.totalTxOk 0
+system.realview.ethernet.postedTxIdle 0
+system.realview.ethernet.coalescedTxIdle nan
+system.realview.ethernet.totalTxIdle 0
+system.realview.ethernet.postedTxDesc 0
+system.realview.ethernet.coalescedTxDesc nan
+system.realview.ethernet.totalTxDesc 0
+system.realview.ethernet.postedRxOrn 0
+system.realview.ethernet.coalescedRxOrn nan
+system.realview.ethernet.totalRxOrn 0
+system.realview.ethernet.coalescedTotal nan
+system.realview.ethernet.postedInterrupts 0
+system.realview.ethernet.droppedPackets 0
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.mcc.osc_clcd.clock 42105
+system.realview.mcc.osc_mcc.clock 20000
+system.realview.mcc.osc_peripheral.clock 41667
+system.realview.mcc.osc_system_bus.clock 41667
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905305537500
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff