Fix handling of Verilog ~& and ~| operators
authorClifford Wolf <clifford@clifford.at>
Thu, 1 Jun 2017 10:43:21 +0000 (12:43 +0200)
committerClifford Wolf <clifford@clifford.at>
Thu, 1 Jun 2017 10:43:21 +0000 (12:43 +0200)
frontends/verilog/verilog_parser.y

index 26201d6187db9e3807094d1f78046923dca90503..154b59ebc9c8ff3631b0d5b3cf60cf291d68cbe7 100644 (file)
@@ -1537,10 +1537,18 @@ basic_expr:
                $$ = new AstNode(AST_BIT_AND, $1, $4);
                append_attr($$, $3);
        } |
+       basic_expr OP_NAND attr basic_expr {
+               $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
+               append_attr($$, $3);
+       } |
        basic_expr '|' attr basic_expr {
                $$ = new AstNode(AST_BIT_OR, $1, $4);
                append_attr($$, $3);
        } |
+       basic_expr OP_NOR attr basic_expr {
+               $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
+               append_attr($$, $3);
+       } |
        basic_expr '^' attr basic_expr {
                $$ = new AstNode(AST_BIT_XOR, $1, $4);
                append_attr($$, $3);