Add Inorder CPU model
authorTaeho Kgil <tkgil@umich.edu>
Wed, 3 Nov 2004 22:56:26 +0000 (17:56 -0500)
committerTaeho Kgil <tkgil@umich.edu>
Wed, 3 Nov 2004 22:56:26 +0000 (17:56 -0500)
SConscript:
arch/isa_parser.py:
cpu/static_inst.hh:
    Add inorderCPU

--HG--
extra : convert_revision : 141372808fac5f6d125f9051ee0be982d21683aa

SConscript
arch/isa_parser.py
cpu/static_inst.hh

index a41680ed40cf3e2d5f570b34cff7f2f6967ac615..a2b1c44fa162bcb8c8f59970b498a36757273f48 100644 (file)
@@ -46,6 +46,7 @@ base_sources = Split('''
        arch/alpha/decoder.cc
        arch/alpha/fast_cpu_exec.cc
        arch/alpha/simple_cpu_exec.cc
+       arch/alpha/inorder_cpu_exec.cc
        arch/alpha/full_cpu_exec.cc
        arch/alpha/faults.cc
        arch/alpha/isa_traits.cc
@@ -127,6 +128,7 @@ base_sources = Split('''
        cpu/full_cpu/iq/standard/iq_standard.cc
        cpu/sampling_cpu/sampling_cpu.cc
        cpu/simple_cpu/simple_cpu.cc
+       cpu/inorder_cpu/inorder_cpu.cc
        cpu/trace/reader/mem_trace_reader.cc
        cpu/trace/reader/ibm_reader.cc
        cpu/trace/reader/itx_reader.cc
@@ -210,6 +212,7 @@ base_obj_desc_files = Split('''
         cpu/full_cpu/PipeTrace.od
         cpu/sampling_cpu/SamplingCPU.od
         cpu/simple_cpu/SimpleCPU.od
+        cpu/inorder_cpu/InorderCPU.od
         cpu/BaseCPU.od
         cpu/IntrControl.od
         mem/bus/Bus.od
@@ -437,6 +440,7 @@ env.Command(Split('''arch/alpha/decoder.cc
                     arch/alpha/decoder.hh
                     arch/alpha/fast_cpu_exec.cc
                      arch/alpha/simple_cpu_exec.cc
+                     arch/alpha/inorder_cpu_exec.cc
                      arch/alpha/full_cpu_exec.cc'''),
             Split('''arch/alpha/isa_desc
                     arch/isa_parser.py'''),
index 011ce762333af2fafd3a43aa1f17cb4aa302d597..c0b5131de103c64969b1adf1834e3ef44963aca2 100755 (executable)
@@ -627,6 +627,9 @@ class CpuModel:
 # Define CPU models.  The following lines should contain the only
 # CPU-model-specific information in this file.  Note that the ISA
 # description itself should have *no* CPU-model-specific content.
+CpuModel('InorderCPU', 'inorder_cpu_exec.cc',
+         '#include "cpu/inorder_cpu/inorder_cpu.hh"',
+         { 'CPU_exec_context': 'InorderCPU' })
 CpuModel('SimpleCPU', 'simple_cpu_exec.cc',
          '#include "cpu/simple_cpu/simple_cpu.hh"',
          { 'CPU_exec_context': 'SimpleCPU' })
index 0315ab7a9a47a82cfb7b1a894b2dcf8c1f563ae1..46b2e4b19f660622f949cd2c8425a3f58a1de5e8 100644 (file)
@@ -44,6 +44,7 @@ class ExecContext;
 class DynInst;
 class FastCPU;
 class SimpleCPU;
+class InorderCPU;
 class SymbolTable;
 
 namespace Trace {
@@ -312,6 +313,12 @@ class StaticInst : public StaticInstBase
      */
     virtual Fault execute(SimpleCPU *xc, Trace::InstRecord *traceData) = 0;
 
+         /**
+     * Execute this instruction under InorderCPU model.
+     */
+    virtual Fault execute(InorderCPU *xc, Trace::InstRecord *traceData) = 0;
+
+
     /**
      * Execute this instruction under FastCPU model.
      */