arch/alpha/decoder.cc
arch/alpha/fast_cpu_exec.cc
arch/alpha/simple_cpu_exec.cc
+ arch/alpha/inorder_cpu_exec.cc
arch/alpha/full_cpu_exec.cc
arch/alpha/faults.cc
arch/alpha/isa_traits.cc
cpu/full_cpu/iq/standard/iq_standard.cc
cpu/sampling_cpu/sampling_cpu.cc
cpu/simple_cpu/simple_cpu.cc
+ cpu/inorder_cpu/inorder_cpu.cc
cpu/trace/reader/mem_trace_reader.cc
cpu/trace/reader/ibm_reader.cc
cpu/trace/reader/itx_reader.cc
cpu/full_cpu/PipeTrace.od
cpu/sampling_cpu/SamplingCPU.od
cpu/simple_cpu/SimpleCPU.od
+ cpu/inorder_cpu/InorderCPU.od
cpu/BaseCPU.od
cpu/IntrControl.od
mem/bus/Bus.od
arch/alpha/decoder.hh
arch/alpha/fast_cpu_exec.cc
arch/alpha/simple_cpu_exec.cc
+ arch/alpha/inorder_cpu_exec.cc
arch/alpha/full_cpu_exec.cc'''),
Split('''arch/alpha/isa_desc
arch/isa_parser.py'''),
# Define CPU models. The following lines should contain the only
# CPU-model-specific information in this file. Note that the ISA
# description itself should have *no* CPU-model-specific content.
+CpuModel('InorderCPU', 'inorder_cpu_exec.cc',
+ '#include "cpu/inorder_cpu/inorder_cpu.hh"',
+ { 'CPU_exec_context': 'InorderCPU' })
CpuModel('SimpleCPU', 'simple_cpu_exec.cc',
'#include "cpu/simple_cpu/simple_cpu.hh"',
{ 'CPU_exec_context': 'SimpleCPU' })
class DynInst;
class FastCPU;
class SimpleCPU;
+class InorderCPU;
class SymbolTable;
namespace Trace {
*/
virtual Fault execute(SimpleCPU *xc, Trace::InstRecord *traceData) = 0;
+ /**
+ * Execute this instruction under InorderCPU model.
+ */
+ virtual Fault execute(InorderCPU *xc, Trace::InstRecord *traceData) = 0;
+
+
/**
* Execute this instruction under FastCPU model.
*/