Update to new $__ICE40_CARRY_WRAPPER
authorEddie Hung <eddie@fpgeh.com>
Thu, 29 Aug 2019 00:07:07 +0000 (17:07 -0700)
committerEddie Hung <eddie@fpgeh.com>
Thu, 29 Aug 2019 00:07:07 +0000 (17:07 -0700)
techlibs/ice40/cells_sim.v

index c7f3bdad255bb9b1675aedab5c5a2b10d0799cb6..02726605f60a785fdda364722d1f98854d9a018f 100644 (file)
@@ -142,15 +142,16 @@ module SB_CARRY (output CO, input I0, I1, CI);
 endmodule
 
 (* abc_box_id = 1, lib_whitebox *)
-module \$__ICE40_FULL_ADDER (
+module \$__ICE40_CARRY_WRAPPER (
        (* abc_carry *)
        output CO,
        output O,
-       input A,
-       input B,
+       input A, B,
        (* abc_carry *)
-       input CI
+       input CI,
+       input I0, I3,
 );
+       parameter LUT = 0;
        SB_CARRY carry (
                .I0(A),
                .I1(B),
@@ -158,16 +159,12 @@ module \$__ICE40_FULL_ADDER (
                .CO(CO)
        );
        SB_LUT4 #(
-               //         I0: 1010 1010 1010 1010
-               //         I1: 1100 1100 1100 1100
-               //         I2: 1111 0000 1111 0000
-               //         I3: 1111 1111 0000 0000
-               .LUT_INIT(16'b 0110_1001_1001_0110)
+               .LUT_INIT(LUT)
        ) adder (
-               .I0(1'b0),
+               .I0(I0),
                .I1(A),
                .I2(B),
-               .I3(CI),
+               .I3(I3),
                .O(O)
        );
 endmodule