struct pipe_fence_handle **fence,
enum pipe_flush_flags flags)
{
- r300_flush(pipe, 0, fence);
+ r300_flush(pipe,
+ flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0,
+ fence);
}
void r300_init_flush_functions(struct r300_context* r300)
struct pipe_fence_handle **fence,
enum pipe_flush_flags flags)
{
- r600_flush(ctx, fence, 0);
+ r600_flush(ctx, fence,
+ flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
}
static void r600_flush_from_winsys(void *ctx, unsigned flags)
struct pipe_fence_handle **fence,
enum pipe_flush_flags flags)
{
- radeonsi_flush(ctx, fence, 0);
+ radeonsi_flush(ctx, fence,
+ flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
}
static void r600_flush_from_winsys(void *ctx, unsigned flags)
/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
#define RADEON_CS_KEEP_TILING_FLAGS 0x01
-
-
#endif
#ifndef RADEON_CS_USE_VM
#define RADEON_CS_RING_COMPUTE 1
#endif
+#ifndef RADEON_CS_END_OF_FRAME
+#define RADEON_CS_END_OF_FRAME 0x04
+#endif
+
#define RELOC_DWORDS (sizeof(struct drm_radeon_cs_reloc) / sizeof(uint32_t))
cs->cst->flags[0] |= RADEON_CS_USE_VM;
cs->cst->cs.num_chunks = 3;
}
+ if (flags & RADEON_FLUSH_END_OF_FRAME) {
+ cs->cst->flags[0] |= RADEON_CS_END_OF_FRAME;
+ cs->cst->cs.num_chunks = 3;
+ }
if (flags & RADEON_FLUSH_COMPUTE) {
cs->cst->flags[1] = RADEON_CS_RING_COMPUTE;
cs->cst->cs.num_chunks = 3;
#define RADEON_FLUSH_ASYNC (1 << 0)
#define RADEON_FLUSH_KEEP_TILING_FLAGS (1 << 1) /* needs DRM 2.12.0 */
#define RADEON_FLUSH_COMPUTE (1 << 2)
+#define RADEON_FLUSH_END_OF_FRAME (1 << 3)
/* Tiling flags. */
enum radeon_bo_layout {