gallium/radeon: send the END_OF_FRAME flag to the DRM
authorMarek Olšák <maraeo@gmail.com>
Fri, 21 Dec 2012 16:15:56 +0000 (17:15 +0100)
committerMarek Olšák <maraeo@gmail.com>
Fri, 4 Jan 2013 12:18:50 +0000 (13:18 +0100)
src/gallium/drivers/r300/r300_flush.c
src/gallium/drivers/r600/r600_pipe.c
src/gallium/drivers/radeonsi/radeonsi_pipe.c
src/gallium/winsys/radeon/drm/radeon_drm_cs.c
src/gallium/winsys/radeon/drm/radeon_winsys.h

index 978a5d93ccf81a88ea59bdcd6c6b13886020080d..6d51ee5d528522824586c08479313b997f4cca78 100644 (file)
@@ -136,7 +136,9 @@ static void r300_flush_wrapped(struct pipe_context *pipe,
                                struct pipe_fence_handle **fence,
                                enum pipe_flush_flags flags)
 {
-    r300_flush(pipe, 0, fence);
+    r300_flush(pipe,
+               flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0,
+               fence);
 }
 
 void r300_init_flush_functions(struct r300_context* r300)
index e33ea13f996f99b5b7f75b3381936eedb6ba4266..f6db3bf9699711b1ca10556c8b4844ca1c433d4f 100644 (file)
@@ -146,7 +146,8 @@ static void r600_flush_from_st(struct pipe_context *ctx,
                               struct pipe_fence_handle **fence,
                               enum pipe_flush_flags flags)
 {
-       r600_flush(ctx, fence, 0);
+       r600_flush(ctx, fence,
+                  flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
 }
 
 static void r600_flush_from_winsys(void *ctx, unsigned flags)
index 6f32a376d7013247ad482ac9513bc9362b242581..d66e30f9995f647623066f596c2f8838a5e40cd0 100644 (file)
@@ -161,7 +161,8 @@ static void r600_flush_from_st(struct pipe_context *ctx,
                               struct pipe_fence_handle **fence,
                                enum pipe_flush_flags flags)
 {
-       radeonsi_flush(ctx, fence, 0);
+       radeonsi_flush(ctx, fence,
+                       flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
 }
 
 static void r600_flush_from_winsys(void *ctx, unsigned flags)
index f9be96186e6c599d06b173d1548c01cb437af23c..c5e7f1e44c2935537a6146aea27aef9d2ae9a6e0 100644 (file)
@@ -81,8 +81,6 @@
 
 /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
 #define RADEON_CS_KEEP_TILING_FLAGS 0x01
-
-
 #endif
 
 #ifndef RADEON_CS_USE_VM
 #define RADEON_CS_RING_COMPUTE      1
 #endif
 
+#ifndef RADEON_CS_END_OF_FRAME
+#define RADEON_CS_END_OF_FRAME      0x04
+#endif
+
 
 #define RELOC_DWORDS (sizeof(struct drm_radeon_cs_reloc) / sizeof(uint32_t))
 
@@ -473,6 +475,10 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs, unsigned flags)
             cs->cst->flags[0] |= RADEON_CS_USE_VM;
             cs->cst->cs.num_chunks = 3;
         }
+        if (flags & RADEON_FLUSH_END_OF_FRAME) {
+            cs->cst->flags[0] |= RADEON_CS_END_OF_FRAME;
+            cs->cst->cs.num_chunks = 3;
+        }
         if (flags & RADEON_FLUSH_COMPUTE) {
             cs->cst->flags[1] = RADEON_CS_RING_COMPUTE;
             cs->cst->cs.num_chunks = 3;
index b7eac3cfc1bb29609345df29baaa65cb2d12eaf4..5bcbf8d16cdfbaea65cf530b6664d9bcdd6e89ae 100644 (file)
@@ -48,6 +48,7 @@
 #define RADEON_FLUSH_ASYNC             (1 << 0)
 #define RADEON_FLUSH_KEEP_TILING_FLAGS (1 << 1) /* needs DRM 2.12.0 */
 #define RADEON_FLUSH_COMPUTE           (1 << 2)
+#define RADEON_FLUSH_END_OF_FRAME       (1 << 3)
 
 /* Tiling flags. */
 enum radeon_bo_layout {