* opcodes/ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,

	efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
	efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
	efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
	efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2dde35383cd93f38d6945b4a8e8b4209879c0a89..342c2f34846e1fc7791b530df816b10b5c849376 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
+
+       * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
+       efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
+       efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
+       efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
+       efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
+
 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
 
        * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index af70ae6ac2a853ad28eb8144c0f701502a9480ef..4cc5191c3d74c80483b6e5dd6875f5b949ee4a0c 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1958,6 +1958,41 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "nmaclhwso.",        XO(4,494,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
 { "mfvscr",  VX(4, 1540), VX_MASK,     PPCVEC,         { VD } },
 { "mtvscr",  VX(4, 1604), VX_MASK,     PPCVEC,         { VB } },
+
+  /* Double-precision opcodes.  */
+  /* Some of these conflict with AltiVec, so move them before, since
+     PPCVEC includes the PPC_OPCODE_PPC set.  */
+{ "efscfd",   VX(4, 719), VX_MASK,     PPCEFS,         { RS, RA } },
+{ "efdabs",   VX(4, 740), VX_MASK,     PPCEFS,         { RS, RA } },
+{ "efdnabs",  VX(4, 741), VX_MASK,     PPCEFS,         { RS, RA } },
+{ "efdneg",   VX(4, 742), VX_MASK,     PPCEFS,         { RS, RA } },
+{ "efdadd",   VX(4, 736), VX_MASK,     PPCEFS,         { RS, RA, RB } },
+{ "efdsub",   VX(4, 737), VX_MASK,     PPCEFS,         { RS, RA, RB } },
+{ "efdmul",   VX(4, 744), VX_MASK,     PPCEFS,         { RS, RA, RB } },
+{ "efddiv",   VX(4, 745), VX_MASK,     PPCEFS,         { RS, RA, RB } },
+{ "efdcmpgt", VX(4, 748), VX_MASK,     PPCEFS,         { CRFD, RA, RB } },
+{ "efdcmplt", VX(4, 749), VX_MASK,     PPCEFS,         { CRFD, RA, RB } },
+{ "efdcmpeq", VX(4, 750), VX_MASK,     PPCEFS,         { CRFD, RA, RB } },
+{ "efdtstgt", VX(4, 764), VX_MASK,     PPCEFS,         { CRFD, RA, RB } },
+{ "efdtstlt", VX(4, 765), VX_MASK,     PPCEFS,         { CRFD, RA, RB } },
+{ "efdtsteq", VX(4, 766), VX_MASK,     PPCEFS,         { CRFD, RA, RB } },
+{ "efdcfsi",  VX(4, 753), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efdcfsid", VX(4, 739), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efdcfui",  VX(4, 752), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efdcfuid", VX(4, 738), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efdcfsf",  VX(4, 755), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efdcfuf",  VX(4, 754), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efdctsi",  VX(4, 757), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efdctsidz",VX(4, 747), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efdctsiz", VX(4, 762), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efdctui",  VX(4, 756), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efdctuidz",VX(4, 746), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efdctuiz", VX(4, 760), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efdctsf",  VX(4, 759), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efdctuf",  VX(4, 758), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efdcfs",   VX(4, 751), VX_MASK,     PPCEFS,         { RS, RB } },
+  /* End of double-precision opcodes.  */
+
 { "vaddcuw", VX(4,  384), VX_MASK,     PPCVEC,         { VD, VA, VB } },
 { "vaddfp",  VX(4,   10), VX_MASK,     PPCVEC,         { VD, VA, VB } },
 { "vaddsbs", VX(4,  768), VX_MASK,     PPCVEC,         { VD, VA, VB } },