vendor: fix a few issues in commit 2f8669ca.

diff --git a/nmigen/lib/cdc.py b/nmigen/lib/cdc.py
index 5c680cd8a32ef3c5915f350cc437849c994265c1..09cdd95d613facdb41e44368c0e303c0aeaf999a 100644 (file)
--- a/nmigen/lib/cdc.py
+++ b/nmigen/lib/cdc.py
@@ -127,7 +127,8 @@ class AsyncFFSynchronizer(Elaboratable):
         self._stages = stages
 
         if async_edge not in ("pos", "neg"):
-            raise ValueError("AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', not {!r}"
+            raise ValueError("AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', "
+                             "not {!r}"
                              .format(async_edge))
         self._edge = async_edge
 

diff --git a/nmigen/vendor/intel.py b/nmigen/vendor/intel.py
index 35f94ad883078627c135e12905ab232bd1f7e5d5..2f0c81f4a80711b65fed5c170a1d0094287e0ddc 100644 (file)
--- a/nmigen/vendor/intel.py
+++ b/nmigen/vendor/intel.py
@@ -403,7 +403,7 @@ class IntelPlatform(TemplatedPlatform):
     def get_async_ff_sync(self, async_ff_sync):
         m = Module()
         sync_output = Signal()
-        if async_ff_sync.edge == "pos":
+        if async_ff_sync._edge == "pos":
             m.submodules += Instance("altera_std_synchronizer",
                 p_depth=async_ff_sync._stages,
                 i_clk=ClockSignal(async_ff_sync._domain),

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 37ebdcff66a5f51c4af55c82eee22741b190f4c7..25bfa2853b134db5b8e2f85e13b14c02e5f87ec8 100644 (file)
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -420,7 +420,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         for i, o in zip((0, *flops), flops):
             m.d.async_ff += o.eq(i)
 
-        if self._edge == "pos":
+        if async_ff_sync._edge == "pos":
             m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i)
         else:
             m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i)

diff --git a/nmigen/vendor/xilinx_spartan_3_6.py b/nmigen/vendor/xilinx_spartan_3_6.py
index 9fd9b33d8c273037bb66342f9a5f96c50dfdfbdb..c7d37d123ca73d023ba0f2b5917db1f0b9de3599 100644 (file)
--- a/nmigen/vendor/xilinx_spartan_3_6.py
+++ b/nmigen/vendor/xilinx_spartan_3_6.py
@@ -451,7 +451,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
         for i, o in zip((0, *flops), flops):
             m.d.async_ff += o.eq(i)
 
-        if self._edge == "pos":
+        if async_ff_sync._edge == "pos":
             m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i)
         else:
             m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i)

diff --git a/nmigen/vendor/xilinx_ultrascale.py b/nmigen/vendor/xilinx_ultrascale.py
index 671b7c9d4cb5bd4bd44bfa2c4c8365368021cebf..6598f0a2f6e44b40a91bba50a41c13336ef76432 100644 (file)
--- a/nmigen/vendor/xilinx_ultrascale.py
+++ b/nmigen/vendor/xilinx_ultrascale.py
@@ -416,7 +416,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
         for i, o in zip((0, *flops), flops):
             m.d.async_ff += o.eq(i)
 
-        if self._edge == "pos":
+        if async_ff_sync._edge == "pos":
             m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i)
         else:
             m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i)