xilinx: improve specify functionality

diff --git a/README.md b/README.md
index 8cd347497c6504b8c4f07be5c7b8220c90d6c2b7..08d4cb0d770c859003542f9c2f1930f5cbde6178 100644 (file)
--- a/README.md
+++ b/README.md
@@ -364,8 +364,13 @@ Verilog Attributes and non-standard features
   it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
   from inserting another pad cell on it.
 
+- The module attribute ``abc9_lut`` is an integer attribute marking to `abc9`
+  that this module describes a LUT with propagation delays described using
+  `specify` statements.
+
 - The module attribute ``abc9_box`` is a boolean specifying a blackbox or
-  whitebox definition for use by `abc9`.
+  whitebox definition, with propagation delays described using `specify`
+  statements, for use by `abc9`.
 
 - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and
   carry-out (if output port) ports of a box. This information is necessary for

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 3cf36aca8b80a7896c3f4501a490f2621e21e659..c996b07763f1f62a2d76cbca8dec7d5df24fb31d 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -227,6 +227,9 @@ struct XAigerWriter
                                        continue;
                                }
 
+                               if (cell->type.in("$specify2", "$specify3", "$specrule"))
+                                       continue;
+
                                if (inst_module) {
                                        bool abc9_flop = false;
                                        auto it = cell->attributes.find("\\abc9_box_seq");

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 9abe6af9fdb0b085092e225d25c80c5790be13e5..c48cd5c86394a1411ba50eace9423efc680a2ef2 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -380,8 +380,10 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 
 void prep_delays(RTLIL::Design *design)
 {
-       // Derive and collect all blackbox modules, and collect all blackbox instantiations
-       pool<Module*> derived;
+       // Derive and collect all Yosys blackbox modules that are not combinatorial abc9 boxes
+       //   (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
+       pool<Module*> blackboxes;
+       pool<Module*> flops;
        std::vector<Cell*> cells;
        for (auto module : design->selected_modules()) {
                if (module->processes.size() > 0) {
@@ -400,42 +402,38 @@ void prep_delays(RTLIL::Design *design)
                                continue;
                        if (inst_module->attributes.count(ID(abc9_box)))
                                continue;
-                       IdString derived_type = inst_module->derive(design, cell->parameters);
-                       inst_module = design->module(derived_type);
+                       IdString blackboxes_type = inst_module->derive(design, cell->parameters);
+                       inst_module = design->module(blackboxes_type);
                        log_assert(inst_module);
-                       derived.insert(inst_module);
+                       blackboxes.insert(inst_module);
+
+                       if (inst_module->get_bool_attribute(ID(abc9_flop))) {
+                               flops.insert(inst_module);
+                               continue; // do not add $__ABC9_DELAY boxes to flops
+                                         //   as delays will be captured in the flop box
+                       }
 
                        cells.emplace_back(cell);
                }
        }
 
        // Transform all $specify3 and $specrule to abc9_{arrival,required} attributes
-       std::vector<Module*> flops;
        dict<SigBit, int> arrivals, requireds;
        pool<Wire*> ports;
        std::stringstream ss;
-       for (auto module : derived) {
-               if (module->get_bool_attribute(ID(abc9_flop)))
-                       flops.push_back(module);
-
+       for (auto module : blackboxes) {
                arrivals.clear();
                requireds.clear();
                for (auto cell : module->cells()) {
                        if (cell->type == ID($specify3)) {
                                auto src = cell->getPort(ID(SRC));
-                               auto dat = cell->getPort(ID(DAT));
                                auto dst = cell->getPort(ID(DST));
                                for (const auto &c : src.chunks())
                                        if (!c.wire->port_input)
                                                log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
-                               for (const auto &c : dat.chunks())
-                                       if (!c.wire->port_input)
-                                               log_error("Module '%s' contains specify cell '%s' where DAT '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dat));
                                for (const auto &c : dst.chunks())
                                        if (!c.wire->port_output)
                                                log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
-                               if (!cell->getParam(ID(EDGE_EN)).as_bool())
-                                       continue;
                                int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
                                int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
                                int max = std::max(rise_max,fall_max);
@@ -443,7 +441,7 @@ void prep_delays(RTLIL::Design *design)
                                        log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
                                        continue;
                                }
-                               for (auto d : dst)
+                               for (const auto &d : dst)
                                        arrivals[d] = std::max(arrivals[d], max);
                        }
                        else if (cell->type == ID($specrule)) {
@@ -472,8 +470,10 @@ void prep_delays(RTLIL::Design *design)
                        continue;
 
                ports.clear();
-               for (const auto &i : arrivals)
+               for (const auto &i : arrivals) {
+                       log_dump(i.first, i.first.wire->name);
                        ports.insert(i.first.wire);
+               }
                for (auto wire : ports) {
                        log_assert(wire->port_output);
                        ss.str("");
@@ -1239,7 +1239,7 @@ struct Abc9OpsPass : public Pass {
                log("\n");
                log("    -prep_box\n");
                log("        pre-compute the box library by analysing all modules marked with\n");
-               log("        (* abc9_box *)\n");
+               log("        (* abc9_box *).\n");
                log("\n");
                log("    -write_box <dst>\n");
                log("        write the pre-computed box library to <dst>.\n");

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index f2c401d66b92901a206c59f66dfb0d013bb24445..53d9a3c9a2ece76fd8a74a7e2a3f26ac0ffc6ae9 100644 (file)
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -398,8 +398,8 @@ module RAM32X1D (
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
   );
-  $__ABC9_LUT6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
-  $__ABC9_LUT6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
+  $__ABC9_RAM6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
+  $__ABC9_RAM6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
 endmodule
 
 module RAM64X1D (
@@ -421,8 +421,8 @@ module RAM64X1D (
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
   );
-  $__ABC9_LUT6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
-  $__ABC9_LUT6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
+  $__ABC9_RAM6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
+  $__ABC9_RAM6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
 endmodule
 
 module RAM128X1D (
@@ -443,8 +443,8 @@ module RAM128X1D (
     .A(A),
     .DPRA(DPRA)
   );
-  $__ABC9_LUT7 spo (.A($SPO), .S(A), .Y(SPO));
-  $__ABC9_LUT7 dpo (.A($DPO), .S(DPRA), .Y(DPO));
+  $__ABC9_RAM7 spo (.A($SPO), .S(A), .Y(SPO));
+  $__ABC9_RAM7 dpo (.A($DPO), .S(DPRA), .Y(DPO));
 endmodule
 
 module RAM32M (
@@ -478,14 +478,14 @@ module RAM32M (
     .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
     .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
   );
-  $__ABC9_LUT6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
-  $__ABC9_LUT6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
-  $__ABC9_LUT6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
-  $__ABC9_LUT6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
-  $__ABC9_LUT6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
-  $__ABC9_LUT6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
-  $__ABC9_LUT6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
-  $__ABC9_LUT6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
+  $__ABC9_RAM6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
+  $__ABC9_RAM6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
+  $__ABC9_RAM6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
+  $__ABC9_RAM6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
+  $__ABC9_RAM6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
+  $__ABC9_RAM6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
+  $__ABC9_RAM6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
+  $__ABC9_RAM6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
 endmodule
 
 module RAM64M (
@@ -519,10 +519,25 @@ module RAM64M (
     .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
     .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
   );
-  $__ABC9_LUT6 doa (.A($DOA), .S(ADDRA), .Y(DOA));
-  $__ABC9_LUT6 dob (.A($DOB), .S(ADDRB), .Y(DOB));
-  $__ABC9_LUT6 doc (.A($DOC), .S(ADDRC), .Y(DOC));
-  $__ABC9_LUT6 dod (.A($DOD), .S(ADDRD), .Y(DOD));
+  $__ABC9_RAM6 doa (.A($DOA), .S(ADDRA), .Y(DOA));
+  $__ABC9_RAM6 dob (.A($DOB), .S(ADDRB), .Y(DOB));
+  $__ABC9_RAM6 doc (.A($DOC), .S(ADDRC), .Y(DOC));
+  $__ABC9_RAM6 dod (.A($DOD), .S(ADDRD), .Y(DOD));
+endmodule
+
+module SRL16 (
+  output Q,
+  (* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
+);
+  parameter [15:0] INIT = 16'h0000;
+  wire $Q;
+  SRL16 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .Q($Q),
+    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
+  );
+  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
 endmodule
 
 module SRL16E (
@@ -538,7 +553,38 @@ module SRL16E (
     .Q($Q),
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
   );
-  $__ABC9_LUT6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
+  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
+endmodule
+
+module SRLC16 (
+  output Q, Q15,
+  (* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
+);
+  parameter [15:0] INIT = 16'h0000;
+  wire $Q;
+  SRLC16 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .Q($Q), .Q(Q15),
+    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
+  );
+  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
+endmodule
+
+module SRLC16E (
+  output Q, Q15,
+  (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
+);
+  parameter [15:0] INIT = 16'h0000;
+  parameter [0:0] IS_CLK_INVERTED = 1'b0;
+  wire $Q;
+  SRLC16E #(
+    .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .Q($Q), .Q(Q15),
+    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
+  );
+  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
 endmodule
 
 module SRLC32E (
@@ -556,7 +602,7 @@ module SRLC32E (
     .Q($Q), .Q31(Q31),
     .A(A), .CE(CE), .CLK(CLK), .D(D)
   );
-  $__ABC9_LUT6 q (.A($Q), .S({1'b1, A}), .Y(Q));
+  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A}), .Y(Q));
 endmodule
 
 module DSP48E1 (

diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index 4373191eab65d215644a7b55a8af5b0eb100492c..6beff30baa3adfac49f8c41d931c9e6391f60057 100644 (file)
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -55,6 +55,7 @@ module \$__ABC9_ASYNC0 (input A, S, output Y);
   assign Y = S ? 1'b0 : A;
   specify
     (A => Y) = 0;
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
     (S => Y) = 764;
   endspecify
 endmodule
@@ -65,6 +66,7 @@ module \$__ABC9_ASYNC1 (input A, S, output Y);
   assign Y = S ? 1'b1 : A;
   specify
     (A => Y) = 0;
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
     (S => Y) = 764;
   endspecify
 endmodule
@@ -76,7 +78,7 @@ endmodule
 //   To model the combinatorial path, such cells have to be split
 //   into comb and seq parts, with this box modelling only the former.
 (* abc9_box *)
-module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
+module \$__ABC9_RAM6 (input A, input [5:0] S, output Y);
   specify
     (S[0] => Y) = 642;
     (S[1] => Y) = 631;
@@ -88,7 +90,7 @@ module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
 endmodule
 // Box to emulate comb/seq behaviour of RAM128
 (* abc9_box *)
-module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
+module \$__ABC9_RAM7 (input A, input [6:0] S, output Y);
   specify
     (S[0] => Y) = 1028;
     (S[1] => Y) = 1017;

diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v
index f2342ce620dc79e2791bb2ed641090afbe022ec0..c02cc196a1299172e3ba9de028b5c790bab1e04d 100644 (file)
--- a/techlibs/xilinx/abc9_unmap.v
+++ b/techlibs/xilinx/abc9_unmap.v
@@ -29,10 +29,10 @@ module $__ABC9_FF_(input D, output Q);
   assign Q = D;
 endmodule
 
-module $__ABC9_LUT6(input A, input [5:0] S, output Y);
+module $__ABC9_RAM6(input A, input [5:0] S, output Y);
   assign Y = A;
 endmodule
-module $__ABC9_LUT7(input A, input [6:0] S, output Y);
+module $__ABC9_RAM7(input A, input [6:0] S, output Y);
   assign Y = A;
 endmodule
 

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index f9d837e4cda1505bbb8a2240f664ca7d02056d38..08142b37f1fe20db360f840f9bd529f6d95a115d 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -263,46 +263,31 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
 endmodule
 
 (* abc9_lut=10 *)
-module $__ABC9_LUT7(output O, input I0, I1, I2, I3, I4, I5, I6);
-  parameter [127:0] INIT = 0;
-  wire [63: 0] s6 = I6 ? INIT[127:64] : INIT[63: 0];
-  wire [31: 0] s5 = I5 ?    s6[63:32] :   s6[31: 0];
-  wire [15: 0] s4 = I4 ?    s5[31:16] :   s5[15: 0];
-  wire [ 7: 0] s3 = I3 ?    s4[15: 8] :   s4[ 7: 0];
-  wire [ 3: 0] s2 = I2 ?    s3[ 7: 4] :   s3[ 3: 0];
-  wire [ 1: 0] s1 = I1 ?    s2[ 3: 2] :   s2[ 1: 0];
-  assign O = I0 ? s1[1] : s1[0];
+module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6);
   specify
-    (I0 => O) = 1028;
-    (I1 => O) = 1017;
-    (I2 => O) =  858;
-    (I3 => O) =  793;
-    (I4 => O) =  624;
-    (I5 => O) =  513;
-    (I6 => O) =  464;
+                                                 // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867
+    (I0 => O) = 642 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (I1 => O) = 631 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (I2 => O) = 472 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (I3 => O) = 407 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (I4 => O) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (I5 => O) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (I6 => O) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */;
   endspecify
 endmodule
 
 (* abc9_lut=20 *)
-module $__ABC9_LUT8(output O, input I0, I1, I2, I3, I4, I5, I6, I7);
-  parameter [255:0] INIT = 0;
-  wire [127: 0] s7 = I7 ? INIT[255:128] : INIT[127: 0];
-  wire [ 63: 0] s6 = I6 ?   s7[127:63]  :   s7[ 64: 0];
-  wire [ 31: 0] s5 = I5 ?   s6[ 63:32]  :   s6[ 31: 0];
-  wire [ 15: 0] s4 = I4 ?   s5[ 31:16]  :   s5[ 15: 0];
-  wire [  7: 0] s3 = I3 ?   s4[ 15: 8]  :   s4[  7: 0];
-  wire [  3: 0] s2 = I2 ?   s3[  7: 4]  :   s3[  3: 0];
-  wire [  1: 0] s1 = I1 ?   s2[  3: 2]  :   s2[  1: 0];
-  assign O = I0 ? s1[1] : s1[0];
+module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7);
   specify
-    (I0 => O) = 1149;
-    (I1 => O) = 1138;
-    (I2 => O) =  979;
-    (I3 => O) =  914;
-    (I4 => O) =  745;
-    (I5 => O) =  634;
-    (I6 => O) =  585;
-    (I7 => O) =  468;
+                                                                             // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L716
+    (I0 => O) = 642 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
+    (I1 => O) = 631 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
+    (I2 => O) = 472 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
+    (I3 => O) = 407 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
+    (I4 => O) = 238 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
+    (I5 => O) = 127 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
+    (I6 => O) = 0 + 296 /* to select F7BMUX */  + 104 /* to cross F8MUX */ + 192 /* BMUX */;
+    (I7 => O) = 0 + 0 + 273 /* to select F8MUX */ + 192 /* BMUX */;
   endspecify
 endmodule
 
@@ -323,9 +308,9 @@ module MUXF7(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
   specify
     // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L451-L453
-    (I0 => O) = 204;
-    (I1 => O) = 208;
-    (S => O) = 286;
+    (I0 => O) = 217;
+    (I1 => O) = 223;
+    (S => O) = 296;
   endspecify
 endmodule
 
@@ -497,21 +482,23 @@ module FDRE (
     1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase
-  if (!IS_C_INVERTED)
-    specify
-      if (CE) (posedge C => (Q : D)) = 303;
-      //$setup(D , posedge C, -46); // Negative times not currently supported
-      $setup(CE, posedge C, 109);
-      $setup(R , posedge C, 404);
-    endspecify
-  else
-    specify
-      if (CE) (negedge C => (Q : D)) = 303;
-      //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
-      $setup(CE, negedge C, 109);
-      $setup(R , negedge C, 404);
-    endspecify
   endgenerate
+  specify
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , posedge C &&& CE &&& !IS_C_INVERTED , -46); // Negative times not currently supported
+    //$setup(D , negedge C &&& CE &&&  IS_C_INVERTED , -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
+    $setup(CE, posedge C &&& !IS_C_INVERTED, 109);
+    $setup(CE, negedge C &&&  IS_C_INVERTED , 109);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
+    $setup(R , posedge C &&& !IS_C_INVERTED, 404);
+    $setup(R , negedge C &&&  IS_C_INVERTED, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
+    if (!IS_C_INVERTED && R ^ IS_R_INVERTED)        (posedge C => (Q : 1'b0)) = 303;
+    if ( IS_C_INVERTED && R ^ IS_R_INVERTED)        (negedge C => (Q : 1'b0)) = 303;
+    if (!IS_C_INVERTED && R ~^ IS_R_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if ( IS_C_INVERTED && R ~^ IS_R_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+  endspecify
 endmodule
 
 (* abc9_flop, lib_whitebox *)
@@ -527,10 +514,14 @@ module FDRE_1 (
   initial Q <= INIT;
   always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
   specify
-    if (CE) (negedge C => (Q : D)) = 303;
-    //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE, negedge C, 109);
-    $setup(R , negedge C, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
+    $setup(R , negedge C, 404);    // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
+    if (R)        (negedge C => (Q : 1'b0)) = 303;
+    if (!R && CE) (negedge C => (Q : D)) = 303;
   endspecify
 endmodule
 
@@ -556,21 +547,23 @@ module FDSE (
     1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase
-  if (!IS_C_INVERTED)
-    specify
-      if (CE) (posedge C => (Q : D)) = 303;
-      //if (CE) $setup(D , posedge C, -46); // Negative times not currently supported
-      $setup(CE, posedge C, 109);
-      $setup(S , posedge C, 404);
-    endspecify
-  else
-    specify
-        if (CE) (negedge C => (Q : D)) = 303;
-        //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
-        $setup(CE, negedge C, 109);
-        $setup(S , negedge C, 404);
-    endspecify
   endgenerate
+  specify
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , posedge C &&& !IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
+    //$setup(D , negedge C &&&  IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
+    $setup(CE, posedge C &&& !IS_C_INVERTED, 109);
+    $setup(CE, negedge C &&&  IS_C_INVERTED, 109);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
+    $setup(S , posedge C &&& !IS_C_INVERTED, 404);
+    $setup(S , negedge C &&&  IS_C_INVERTED, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
+    if (!IS_C_INVERTED && S ^ IS_S_INVERTED)        (posedge C => (Q : 1'b1)) = 303;
+    if ( IS_C_INVERTED && S ^ IS_S_INVERTED)        (negedge C => (Q : 1'b1)) = 303;
+    if (!IS_C_INVERTED && S ~^ IS_S_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if ( IS_C_INVERTED && S ~^ IS_S_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+  endspecify
 endmodule
 
 (* abc9_flop, lib_whitebox *)
@@ -586,10 +579,15 @@ module FDSE_1 (
   initial Q <= INIT;
   always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
   specify
-    if (CE) (negedge C => (Q : D)) = 303;
-    //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE, negedge C, 109);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
     $setup(S , negedge C, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
+    if (S)        (negedge C => (Q : 1'b1)) = 303;
+    if (!S && CE) (negedge C => (Q : D)) = 303;
   endspecify
 endmodule
 
@@ -652,21 +650,22 @@ module FDCE (
     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase
-  if (!IS_C_INVERTED)
-    specify
-      if (CE) (posedge C => (Q : D)) = 303;
-      //if (CE) $setup(D  , posedge C, -46); // Negative times not currently supported
-      $setup(CE , posedge C, 109);
-      $setup(CLR, posedge C, 764);
-    endspecify
-  else
-    specify
-        if (CE) (negedge C => (Q : D)) = 303;
-        //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
-        $setup(CE , negedge C, 109);
-        $setup(CLR, negedge C, 764);
-    endspecify
- endgenerate
+  endgenerate
+  specify
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , posedge C &&& !IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
+    //$setup(D , negedge C &&&  IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
+    $setup(CE , posedge C &&& !IS_C_INVERTED, 109);
+    $setup(CE , negedge C &&&  IS_C_INVERTED, 109);
+    $setup(CLR, posedge C &&& !IS_C_INVERTED, 404);
+    $setup(CLR, negedge C &&&  IS_C_INVERTED, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
+    //if (!IS_CLR_INVERTED) (posedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
+    //if ( IS_CLR_INVERTED) (negedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
+    if (!IS_C_INVERTED && CLR ~^ IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if ( IS_C_INVERTED && CLR ~^ IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+  endspecify
 endmodule
 
 (* abc9_flop, lib_whitebox *)
@@ -682,10 +681,14 @@ module FDCE_1 (
   initial Q <= INIT;
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
   specify
-    if (CE) (negedge C => (Q : D)) = 303;
-    //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE , negedge C, 109);
-    $setup(CLR, negedge C, 764);
+    $setup(CLR, negedge C, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
+    //(posedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
+    if (!CLR && CE) (negedge C => (Q : D)) = 303;
   endspecify
 endmodule
 
@@ -712,21 +715,22 @@ module FDPE (
     2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase
-  if (!IS_C_INVERTED)
-    specify
-      if (CE) (posedge C => (Q : D)) = 303;
-      //if (CE) $setup(D  , posedge C, -46); // Negative times not currently supported
-      $setup(CE , posedge C, 109);
-      $setup(PRE, posedge C, 764);
-    endspecify
-  else
-    specify
-        if (CE) (negedge C => (Q : D)) = 303;
-        //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
-        $setup(CE , negedge C, 109);
-        $setup(PRE, negedge C, 764);
-    endspecify
   endgenerate
+  specify
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , posedge C &&& !IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
+    //$setup(D , negedge C &&&  IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
+    $setup(CE , posedge C &&& !IS_C_INVERTED, 109);
+    $setup(CE , negedge C &&&  IS_C_INVERTED, 109);
+    $setup(PRE, posedge C &&& !IS_C_INVERTED, 404);
+    $setup(PRE, negedge C &&&  IS_C_INVERTED, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
+    //if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
+    //if ( IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
+    if (!IS_C_INVERTED && PRE ~^ IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if ( IS_C_INVERTED && PRE ~^ IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+  endspecify
 endmodule
 
 (* abc9_flop, lib_whitebox *)
@@ -742,10 +746,15 @@ module FDPE_1 (
   initial Q <= INIT;
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
   specify
-    if (CE) (negedge C => (Q : D)) = 303;
-    //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE , negedge C, 109);
-    $setup(PRE, negedge C, 764);
+    $setup(PRE, negedge C, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
+    //if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
+    //if (IS_PRE_INVERTED)  (negedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
+    if (!PRE && CE) (negedge C => (Q : D)) = 303;
   endspecify
 endmodule
 
@@ -1375,48 +1384,38 @@ module RAM32X1D (
   assign DPO = mem[dpra];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[a] <= D;
-  generate
-    if (!IS_WCLK_INVERTED)
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-        if (WE) (posedge WCLK => (SPO : D)) = 1153;
-        if (WE) (posedge WCLK => (DPO : D)) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(D , posedge WCLK, 453);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, posedge WCLK, 654);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
-        $setup(A0, posedge WCLK, 245);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
-        $setup(A1, posedge WCLK, 208);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
-        $setup(A2, posedge WCLK, 147);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
-        $setup(A3, posedge WCLK, 68);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
-        $setup(A4, posedge WCLK, 66);
-      endspecify
-    else
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-        if (WE) (negedge WCLK => (SPO : D)) = 1153;
-        if (WE) (negedge WCLK => (DPO : D)) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(D , negedge WCLK, 453);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, negedge WCLK, 654);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
-        $setup(A0, negedge WCLK, 245);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
-        $setup(A1, negedge WCLK, 208);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
-        $setup(A2, negedge WCLK, 147);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
-        $setup(A3, negedge WCLK, 68);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
-        $setup(A4, negedge WCLK, 66);
-      endspecify
-  endgenerate
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+    $setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
+    $setup(D , negedge WCLK &&&  IS_WCLK_INVERTED && WE, 453);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+    $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
+    $setup(WE, negedge WCLK &&&  IS_WCLK_INVERTED, 654);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
+    $setup(A0, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
+    $setup(A0, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 245);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
+    $setup(A1, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
+    $setup(A1, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 208);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
+    $setup(A2, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
+    $setup(A2, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 147);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
+    $setup(A3, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
+    $setup(A3, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
+    $setup(A4, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
+    $setup(A4, posedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
+    // Captured by $__ABC9_RAM6
+    //({A0,DPRA0} => {SPO,DPO}) = 642;
+    //({A1,DPRA1} => {SPO,DPO}) = 631;
+    //({A2,DPRA2} => {SPO,DPO}) = 472;
+    //({A3,DPRA3} => {SPO,DPO}) = 407;
+    //({A4,DPRA4} => {SPO,DPO}) = 238;
+  endspecify
 endmodule
 
 module RAM32X1D_1 (
@@ -1443,23 +1442,28 @@ module RAM32X1D_1 (
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(negedge clk) if (WE) mem[a] <= D;
   specify
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-    if (WE) (negedge WCLK => (SPO : D)) = 1153;
-    if (WE) (negedge WCLK => (DPO : D)) = 1153;
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-    $setup(D , negedge WCLK, 453);
+    $setup(D , negedge WCLK &&& WE, 453);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
     $setup(WE, negedge WCLK, 654);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
-    $setup(A0, negedge WCLK, 245);
+    $setup(A0, negedge WCLK &&& WE, 245);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
-    $setup(A1, negedge WCLK, 208);
+    $setup(A1, negedge WCLK &&& WE, 208);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
-    $setup(A2, negedge WCLK, 147);
+    $setup(A2, negedge WCLK &&& WE, 147);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
-    $setup(A3, negedge WCLK, 68);
+    $setup(A3, negedge WCLK &&& WE, 68);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
-    $setup(A4, negedge WCLK, 66);
+    $setup(A4, negedge WCLK &&& WE, 66);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+    if (WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
+    // Captured by $__ABC9_RAM6
+    //({A0,DPRA0} => {SPO,DPO}) = 642;
+    //({A1,DPRA1} => {SPO,DPO}) = 631;
+    //({A2,DPRA2} => {SPO,DPO}) = 472;
+    //({A3,DPRA3} => {SPO,DPO}) = 407;
+    //({A4,DPRA4} => {SPO,DPO}) = 238;
   endspecify
 endmodule
 
@@ -1482,52 +1486,42 @@ module RAM64X1D (
   assign DPO = mem[dpra];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[a] <= D;
-  generate
-    if (!IS_WCLK_INVERTED)
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-        if (WE) (posedge WCLK => (SPO : D)) = 1153;
-        if (WE) (posedge WCLK => (DPO : D)) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(D , posedge WCLK, 453);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, posedge WCLK, 654);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
-        $setup(A0, posedge WCLK, 362);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
-        $setup(A1, posedge WCLK, 245);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
-        $setup(A2, posedge WCLK, 208);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
-        $setup(A3, posedge WCLK, 147);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
-        $setup(A4, posedge WCLK, 68);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
-        $setup(A5, posedge WCLK, 66);
-      endspecify
-    else
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-        if (WE) (negedge WCLK => (SPO : D)) = 1153;
-        if (WE) (negedge WCLK => (DPO : D)) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(D , negedge WCLK, 453);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, negedge WCLK, 654);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
-        $setup(A0, negedge WCLK, 362);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
-        $setup(A1, negedge WCLK, 245);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
-        $setup(A2, negedge WCLK, 208);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
-        $setup(A3, negedge WCLK, 147);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
-        $setup(A4, negedge WCLK, 68);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
-        $setup(A5, negedge WCLK, 66);
-      endspecify
-  endgenerate
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+    $setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
+    $setup(D , negedge WCLK &&&  IS_WCLK_INVERTED && WE, 453);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+    $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
+    $setup(WE, negedge WCLK &&&  IS_WCLK_INVERTED, 654);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
+    $setup(A0, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362);
+    $setup(A0, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 362);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
+    $setup(A1, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
+    $setup(A1, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 245);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
+    $setup(A2, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
+    $setup(A2, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 208);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
+    $setup(A3, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
+    $setup(A3, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 147);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
+    $setup(A4, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
+    $setup(A4, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
+    $setup(A5, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
+    $setup(A5, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
+    // Captured by $__ABC9_RAM6
+    //({A0,DPRA0} => {SPO,DPO}) = 642;
+    //({A1,DPRA1} => {SPO,DPO}) = 631;
+    //({A2,DPRA2} => {SPO,DPO}) = 472;
+    //({A3,DPRA3} => {SPO,DPO}) = 407;
+    //({A4,DPRA4} => {SPO,DPO}) = 238;
+    //({A5,DPRA5} => {SPO,DPO}) = 127;
+  endspecify
 endmodule
 
 module RAM64X1D_1 (
@@ -1550,25 +1544,24 @@ module RAM64X1D_1 (
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(negedge clk) if (WE) mem[a] <= D;
   specify
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-    if (WE) (negedge WCLK => (SPO : D)) = 1153;
-    if (WE) (negedge WCLK => (DPO : D)) = 1153;
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-    $setup(D , negedge WCLK, 453);
+    $setup(D , negedge WCLK &&& WE, 453);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
     $setup(WE, negedge WCLK, 654);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
-    $setup(A0, negedge WCLK, 362);
+    $setup(A0, negedge WCLK &&& WE, 362);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
-    $setup(A1, negedge WCLK, 245);
+    $setup(A1, negedge WCLK &&& WE, 245);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
-    $setup(A2, negedge WCLK, 208);
+    $setup(A2, negedge WCLK &&& WE, 208);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
-    $setup(A3, negedge WCLK, 147);
+    $setup(A3, negedge WCLK &&& WE, 147);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
-    $setup(A4, negedge WCLK, 68);
+    $setup(A4, negedge WCLK &&& WE, 68);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
-    $setup(A5, negedge WCLK, 66);
+    $setup(A5, negedge WCLK &&& WE, 66);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+    if (WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
   endspecify
 endmodule
 
@@ -1579,8 +1572,6 @@ module RAM128X1D (
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input        WCLK,
   input        WE,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
-  (* abc9_required="616 362 245 208 147 68 66" *)
   input  [6:0] A,
   input  [6:0] DPRA
 );
@@ -1591,46 +1582,47 @@ module RAM128X1D (
   assign DPO = mem[DPRA];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[A] <= D;
-  generate
-    if (!IS_WCLK_INVERTED)
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-        //   plus 208ps to cross MUXF7
-        if (WE) (posedge WCLK => (SPO : D)) = 1359;
-        if (WE) (posedge WCLK => (DPO : D)) = 1359;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(D , posedge WCLK, 453);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, posedge WCLK, 654);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
-        $setup(A[0], posedge WCLK, 616);
-        $setup(A[1], posedge WCLK, 362);
-        $setup(A[2], posedge WCLK, 245);
-        $setup(A[3], posedge WCLK, 208);
-        $setup(A[4], posedge WCLK, 147);
-        $setup(A[5], posedge WCLK, 68);
-        $setup(A[6], posedge WCLK, 66);
-      endspecify
-    else
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-        //   plus 208ps to cross MUXF7
-        if (WE) (negedge WCLK => (SPO : D)) = 1359;
-        if (WE) (negedge WCLK => (DPO : D)) = 1359;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(D , negedge WCLK, 453);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, negedge WCLK, 654);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
-        $setup(A[0], negedge WCLK, 616);
-        $setup(A[1], negedge WCLK, 362);
-        $setup(A[2], negedge WCLK, 245);
-        $setup(A[3], negedge WCLK, 208);
-        $setup(A[4], negedge WCLK, 147);
-        $setup(A[5], negedge WCLK, 68);
-        $setup(A[6], negedge WCLK, 66);
-      endspecify
-  endgenerate
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+    $setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
+    $setup(D , negedge WCLK &&&  IS_WCLK_INVERTED && WE, 453);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+    $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
+    $setup(WE, negedge WCLK &&&  IS_WCLK_INVERTED, 654);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
+    $setup(A[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 616);
+    $setup(A[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 616);
+    $setup(A[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362);
+    $setup(A[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 362);
+    $setup(A[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
+    $setup(A[2], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 245);
+    $setup(A[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
+    $setup(A[3], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 208);
+    $setup(A[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
+    $setup(A[4], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 147);
+    $setup(A[5], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
+    $setup(A[5], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
+    $setup(A[6], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
+    $setup(A[6], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D))    = 1153 + 217 /* to cross F7AMUX */ + 175 /* AMUX */;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+    // Captured by $__ABC9_RAM7
+    //(A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    //(A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    //(A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    //(A[3] => SPO) = 407 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    //(A[4] => SPO) = 238 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    //(A[5] => SPO) = 127 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    //(A[6] => SPO) = 0 + 276 /* to select F7AMUX */ + 175 /* AMUX */;
+    //(DPRA[0] => DPO) = 642 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    //(DPRA[1] => DPO) = 631 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    //(DPRA[2] => DPO) = 472 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    //(DPRA[3] => DPO) = 407 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    //(DPRA[4] => DPO) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    //(DPRA[5] => DPO) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    //(DPRA[6] => DPO) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */;
+  endspecify
 endmodule
 
 module RAM256X1D (
@@ -1690,87 +1682,72 @@ module RAM32M (
       mem_c[2*ADDRD+:2] <= DIC;
       mem_d[2*ADDRD+:2] <= DID;
     end
-  generate
-    if (!IS_WCLK_INVERTED)
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
-        if (WE) (posedge WCLK => (DOA[0] : DIA[0])) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
-        if (WE) (posedge WCLK => (DOA[1] : DIA[1])) = 1188;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-        if (WE) (posedge WCLK => (DOB[0] : DIB[0])) = 1161;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
-        if (WE) (posedge WCLK => (DOB[1] : DIB[1])) = 1187;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
-        if (WE) (posedge WCLK => (DOC[0] : DIC[0])) = 1158;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
-        if (WE) (posedge WCLK => (DOC[1] : DIC[1])) = 1180;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
-        if (WE) (posedge WCLK => (DOD[0] : DID[0])) = 1163;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
-        if (WE) (posedge WCLK => (DOD[1] : DID[1])) = 1190;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(ADDRD[0], posedge WCLK, 245);
-        $setup(ADDRD[1], posedge WCLK, 208);
-        $setup(ADDRD[2], posedge WCLK, 147);
-        $setup(ADDRD[3], posedge WCLK, 68);
-        $setup(ADDRD[4], posedge WCLK, 66);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
-        $setup(DIA[0], posedge WCLK, 453);
-        $setup(DIA[1], posedge WCLK, 384);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
-        $setup(DIB[0], posedge WCLK, 461);
-        $setup(DIB[1], posedge WCLK, 354);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
-        $setup(DIC[0], posedge WCLK, 457);
-        $setup(DIC[1], posedge WCLK, 375);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
-        $setup(DID[0], posedge WCLK, 310);
-        $setup(DID[1], posedge WCLK, 334);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, posedge WCLK, 654);
-      endspecify
-    else
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
-        if (WE) (negedge WCLK => (DOA[0] : DIA[0])) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
-        if (WE) (negedge WCLK => (DOA[1] : DIA[1])) = 1188;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-        if (WE) (negedge WCLK => (DOB[0] : DIB[0])) = 1161;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
-        if (WE) (negedge WCLK => (DOB[1] : DIB[1])) = 1187;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
-        if (WE) (negedge WCLK => (DOC[0] : DIC[0])) = 1158;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
-        if (WE) (negedge WCLK => (DOC[1] : DIC[1])) = 1180;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
-        if (WE) (negedge WCLK => (DOD[0] : DID[0])) = 1163;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
-        if (WE) (negedge WCLK => (DOD[1] : DID[1])) = 1190;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(ADDRD[0], negedge WCLK, 245);
-        $setup(ADDRD[1], negedge WCLK, 208);
-        $setup(ADDRD[2], negedge WCLK, 147);
-        $setup(ADDRD[3], negedge WCLK, 68);
-        $setup(ADDRD[4], negedge WCLK, 66);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
-        $setup(DIA[0], negedge WCLK, 453);
-        $setup(DIA[1], negedge WCLK, 384);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
-        $setup(DIB[0], negedge WCLK, 461);
-        $setup(DIB[1], negedge WCLK, 354);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
-        $setup(DIC[0], negedge WCLK, 457);
-        $setup(DIC[1], negedge WCLK, 375);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
-        $setup(DID[0], negedge WCLK, 310);
-        $setup(DID[1], negedge WCLK, 334);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, posedge WCLK, 654);
-      endspecify
-  endgenerate
-
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+    $setup(ADDRD[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
+    $setup(ADDRD[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 245);
+    $setup(ADDRD[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
+    $setup(ADDRD[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 208);
+    $setup(ADDRD[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
+    $setup(ADDRD[2], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 147);
+    $setup(ADDRD[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
+    $setup(ADDRD[3], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
+    $setup(ADDRD[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
+    $setup(ADDRD[4], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
+    $setup(DIA[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
+    $setup(DIA[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 453);
+    $setup(DIA[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 384);
+    $setup(DIA[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 384);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
+    $setup(DIB[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 461);
+    $setup(DIB[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 461);
+    $setup(DIB[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 354);
+    $setup(DIB[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 354);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
+    $setup(DIC[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 457);
+    $setup(DIC[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 457);
+    $setup(DIC[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 375);
+    $setup(DIC[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 375);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
+    $setup(DID[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 310);
+    $setup(DID[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 310);
+    $setup(DID[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 334);
+    $setup(DID[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 334);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+    $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
+    $setup(WE, negedge WCLK &&&  IS_WCLK_INVERTED, 654);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA[0] : DIA[0])) = 1153;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA[0] : DIA[0])) = 1153;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA[1] : DIA[1])) = 1188;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA[1] : DIA[1])) = 1188;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB[0] : DIB[0])) = 1161;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB[0] : DIB[0])) = 1161;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB[1] : DIB[1])) = 1187;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB[1] : DIB[1])) = 1187;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC[0] : DIC[0])) = 1158;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC[0] : DIC[0])) = 1158;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC[1] : DIC[1])) = 1180;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC[1] : DIC[1])) = 1180;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[0] : DID[0])) = 1163;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[0] : DID[0])) = 1163;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[1] : DID[1])) = 1190;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[1] : DID[1])) = 1190;
+    // Captured by $__ABC9_RAM6
+    //({{2{ADDRA[0]}},{2{ADDRB[0]}},{2{ADDRC[0]}},{2{ADDRD[0]}}} => {DOA,DOB,DOC,DOD}) = 642;
+    //({{2{ADDRA[1]}},{2{ADDRB[1]}},{2{ADDRC[1]}},{2{ADDRD[1]}}} => {DOA,DOB,DOC,DOD}) = 631;
+    //({{2{ADDRA[2]}},{2{ADDRB[2]}},{2{ADDRC[2]}},{2{ADDRD[2]}}} => {DOA,DOB,DOC,DOD}) = 472;
+    //({{2{ADDRA[3]}},{2{ADDRB[3]}},{2{ADDRC[3]}},{2{ADDRD[3]}}} => {DOA,DOB,DOC,DOD}) = 407;
+    //({{2{ADDRA[4]}},{2{ADDRB[4]}},{2{ADDRC[4]}},{2{ADDRD[4]}}} => {DOA,DOB,DOC,DOD}) = 238;
+  endspecify
 endmodule
 
 module RAM32M16 (
@@ -1879,64 +1856,54 @@ module RAM64M (
       mem_c[ADDRD] <= DIC;
       mem_d[ADDRD] <= DID;
     end
-  generate
-    if (!IS_WCLK_INVERTED)
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
-        if (WE) (posedge WCLK => (DOA : DIA)) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-        if (WE) (posedge WCLK => (DOB : DIB)) = 1161;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
-        if (WE) (posedge WCLK => (DOC : DIC)) = 1158;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
-        if (WE) (posedge WCLK => (DOD : DID)) = 1163;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
-        $setup(ADDRD[0], posedge WCLK, 362);
-        $setup(ADDRD[1], posedge WCLK, 245);
-        $setup(ADDRD[2], posedge WCLK, 208);
-        $setup(ADDRD[3], posedge WCLK, 147);
-        $setup(ADDRD[4], posedge WCLK, 68);
-        $setup(ADDRD[5], posedge WCLK, 66);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
-        $setup(DIA, posedge WCLK, 384);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
-        $setup(DIB, posedge WCLK, 354);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
-        $setup(DIC, posedge WCLK, 375);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
-        $setup(DID, posedge WCLK, 310);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, posedge WCLK, 654);
-      endspecify
-    else
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
-        if (WE) (negedge WCLK => (DOA : DIA)) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-        if (WE) (negedge WCLK => (DOB : DIB)) = 1161;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
-        if (WE) (negedge WCLK => (DOC : DIC)) = 1158;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
-        if (WE) (negedge WCLK => (DOD : DID)) = 1163;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
-        $setup(ADDRD[0], negedge WCLK, 362);
-        $setup(ADDRD[1], negedge WCLK, 245);
-        $setup(ADDRD[2], negedge WCLK, 208);
-        $setup(ADDRD[3], negedge WCLK, 147);
-        $setup(ADDRD[4], negedge WCLK, 68);
-        $setup(ADDRD[5], negedge WCLK, 66);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
-        $setup(DIA, negedge WCLK, 384);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
-        $setup(DIB, negedge WCLK, 354);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
-        $setup(DIC, negedge WCLK, 375);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
-        $setup(DID, negedge WCLK, 310);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, negedge WCLK, 654);
-      endspecify
-  endgenerate
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
+    $setup(ADDRD[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362);
+    $setup(ADDRD[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 362);
+    $setup(ADDRD[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
+    $setup(ADDRD[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 245);
+    $setup(ADDRD[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
+    $setup(ADDRD[2], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 208);
+    $setup(ADDRD[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
+    $setup(ADDRD[3], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 147);
+    $setup(ADDRD[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
+    $setup(ADDRD[4], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
+    $setup(ADDRD[5], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
+    $setup(ADDRD[5], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
+    $setup(DIA, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 384);
+    $setup(DIA, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 384);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
+    $setup(DIB, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 354);
+    $setup(DIB, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 354);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
+    $setup(DIC, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 375);
+    $setup(DIC, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 375);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
+    $setup(DID, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 310);
+    $setup(DID, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 310);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+    $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 654);
+    $setup(WE, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 654);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA : DIA)) = 1153;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA : DIA)) = 1153;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB : DIB)) = 1161;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB : DIB)) = 1161;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC : DIC)) = 1158;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC : DIC)) = 1158;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD : DID)) = 1163;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD : DID)) = 1163;
+    // Captured by $__ABC9_RAM6
+    //({ADDRA[0],ADDRB[0],ADDRC[0],ADDRD[0]} => {DOA,DOB,DOC,DOD}) = 642;
+    //({ADDRA[1],ADDRB[1],ADDRC[1],ADDRD[1]} => {DOA,DOB,DOC,DOD}) = 631;
+    //({ADDRA[2],ADDRB[2],ADDRC[2],ADDRD[2]} => {DOA,DOB,DOC,DOD}) = 472;
+    //({ADDRA[3],ADDRB[3],ADDRC[3],ADDRD[3]} => {DOA,DOB,DOC,DOD}) = 407;
+    //({ADDRA[4],ADDRB[4],ADDRC[4],ADDRD[4]} => {DOA,DOB,DOC,DOD}) = 238;
+  endspecify
 endmodule
 
 module RAM64M8 (
@@ -2064,11 +2031,21 @@ module SRL16 (
   reg [15:0] r = INIT;
   assign Q = r[{A3,A2,A1,A0}];
   always @(posedge CLK) r <= { r[14:0], D };
+
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
+    (posedge CLK => (Q : 1'bx)) = 1472;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
+    $setup(D , posedge CLK, 173);
+    // Captured by $__ABC9_RAM6
+    //(A0 => Q) = 631;
+    //(A1 => Q) = 472;
+    //(A2 => Q) = 407;
+    //(A3 => Q) = 238;
+  endspecify
 endmodule
 
 module SRL16E (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
-  (* abc9_arrival=1472 *)
   output Q,
   input A0, A1, A2, A3, CE,
   (* clkbuf_sink *)
@@ -2088,6 +2065,19 @@ module SRL16E (
     else
       always @(posedge CLK) if (CE) r <= { r[14:0], D };
   endgenerate
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
+    $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
+    $setup(D , negedge CLK &&&  IS_CLK_INVERTED, 173);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
+    if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472;
+    if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472;
+    // Captured by $__ABC9_RAM6
+    //(A0 => Q) = 631;
+    //(A1 => Q) = 472;
+    //(A2 => Q) = 407;
+    //(A3 => Q) = 238;
+  endspecify
 endmodule
 
 module SRLC16 (
@@ -2104,6 +2094,18 @@ module SRLC16 (
   assign Q15 = r[15];
   assign Q = r[{A3,A2,A1,A0}];
   always @(posedge CLK) r <= { r[14:0], D };
+
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
+    (posedge CLK => (Q : 1'bx)) = 1472;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
+    $setup(D , posedge CLK, 173);
+    // Captured by $__ABC9_RAM6
+    //(A0 => Q) = 631;
+    //(A1 => Q) = 472;
+    //(A2 => Q) = 407;
+    //(A3 => Q) = 238;
+  endspecify
 endmodule
 
 module SRLC16E (
@@ -2128,14 +2130,24 @@ module SRLC16E (
     else
       always @(posedge CLK) if (CE) r <= { r[14:0], D };
   endgenerate
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
+    $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
+    $setup(D , negedge CLK &&&  IS_CLK_INVERTED, 173);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
+    if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472;
+    if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472;
+    // Captured by $__ABC9_RAM6
+    //(A0 => Q) = 642;
+    //(A1 => Q) = 631;
+    //(A2 => Q) = 472;
+    //(A3 => Q) = 407;
+    //(A4 => Q) = 238;
+  endspecify
 endmodule
 
 module SRLC32E (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
-  (* abc9_arrival=1472 *)
   output Q,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
-  (* abc9_arrival=1114 *)
   output Q31,
   input [4:0] A,
   input CE,
@@ -2157,6 +2169,23 @@ module SRLC32E (
     else
       always @(posedge CLK) if (CE) r <= { r[30:0], D };
   endgenerate
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
+    $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
+    $setup(D , negedge CLK &&&  IS_CLK_INVERTED, 173);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
+    if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472;
+    if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
+    if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1114;
+    if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1114;
+    // Captured by $__ABC9_RAM6
+    //(A0 => Q) = 642;
+    //(A1 => Q) = 631;
+    //(A2 => Q) = 472;
+    //(A3 => Q) = 407;
+    //(A4 => Q) = 238;
+  endspecify
 endmodule
 
 module CFGLUT5 (
@@ -2928,31 +2957,16 @@ module DSP48E1 (
     output reg [3:0] CARRYOUT,
     output reg MULTSIGNOUT,
     output OVERFLOW,
-`ifdef YOSYS
-    (* abc9_arrival = \P.abc9_arrival () *)
-`endif
     output reg signed [47:0] P,
     output reg PATTERNBDETECT,
     output reg PATTERNDETECT,
-`ifdef YOSYS
-    (* abc9_arrival = \PCOUT.abc9_arrival () *)
-`endif
     output [47:0] PCOUT,
     output UNDERFLOW,
-`ifdef YOSYS
-    (* abc9_required = \A.abc9_required () *)
-`endif
     input signed [29:0] A,
     input [29:0] ACIN,
     input [3:0] ALUMODE,
-`ifdef YOSYS
-    (* abc9_required = \B.abc9_required () *)
-`endif
     input signed [17:0] B,
     input [17:0] BCIN,
-`ifdef YOSYS
-    (* abc9_required = \C.abc9_required () *)
-`endif
     input [47:0] C,
     input CARRYCASCIN,
     input CARRYIN,
@@ -2971,16 +2985,10 @@ module DSP48E1 (
     input CEM,
     input CEP,
     (* clkbuf_sink *) input CLK,
-`ifdef YOSYS
-    (* abc9_required = \D.abc9_required () *)
-`endif
     input [24:0] D,
     input [4:0] INMODE,
     input MULTSIGNIN,
     input [6:0] OPMODE,
-`ifdef YOSYS
-    (* abc9_required = \PCIN.abc9_required () *)
-`endif
     input [47:0] PCIN,
     input RSTA,
     input RSTALLCARRYIN,
@@ -3157,6 +3165,23 @@ module DSP48E1 (
         //    $error("Invalid DSP48E1 configuration");
     end
     endfunction
+
+    specify
+        $setup(A   , posedge CLK &&& !IS_CLK_INVERTED, \A.abc9_required () );
+        $setup(A   , negedge CLK &&&  IS_CLK_INVERTED, \A.abc9_required () );
+        $setup(B   , posedge CLK &&& !IS_CLK_INVERTED, \B.abc9_required () );
+        $setup(B   , negedge CLK &&&  IS_CLK_INVERTED, \B.abc9_required () );
+        $setup(C   , posedge CLK &&& !IS_CLK_INVERTED, \C.abc9_required () );
+        $setup(C   , negedge CLK &&&  IS_CLK_INVERTED, \C.abc9_required () );
+        $setup(D   , posedge CLK &&& !IS_CLK_INVERTED, \D.abc9_required () );
+        $setup(D   , negedge CLK &&&  IS_CLK_INVERTED, \D.abc9_required () );
+        $setup(PCIN, posedge CLK &&& !IS_CLK_INVERTED, \PCIN.abc9_required () );
+        $setup(PCIN, negedge CLK &&&  IS_CLK_INVERTED, \PCIN.abc9_required () );
+        if (!IS_CLK_INVERTED && CEP) (posedge CLK => (P : 48'bx)) = \P.abc9_arrival () ;
+        if ( IS_CLK_INVERTED && CEP) (negedge CLK => (P : 48'bx)) = \P.abc9_arrival () ;
+        if (!IS_CLK_INVERTED && CEP) (posedge CLK => (PCOUT : 48'bx)) = \PCOUT.abc9_arrival () ;
+        if ( IS_CLK_INVERTED && CEP) (negedge CLK => (PCOUT : 48'bx)) = \PCOUT.abc9_arrival () ;
+    endspecify
 `endif
 
     initial begin

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 4011e09b0b0fa83bd287d44704537d91a71617bc..bb3ced8da56c9857260d995b273d765a7e595eaa 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -619,8 +619,8 @@ struct SynthXilinxPass : public ScriptPass
                                if (dff_mode)
                                        techmap_args += " -D DFF_MODE";
                                run("techmap " + techmap_args);
-                               run("read_verilog -icells -specify -lib +/xilinx/abc9_model.v");
-                               std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
+                               run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
+                               std::string abc9_opts;
                                auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
                                if (active_design->scratchpad.count(k))
                                        abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());