This patch introduces ETMv4 (Embedded Trace Macrocell) system registers for the AArch...

gas           * testsuite/gas/aarch64/etm-ro-invalid.d: New test.
              * testsuite/gas/aarch64/etm-ro-invalid.l: New test.
              * testsuite/gas/aarch64/etm-ro-invalid.s: New test.
              * testsuite/gas/aarch64/etm-ro.s: New test.
              * testsuite/gas/aarch64/etm-wo-invalid.d: New test.
              * testsuite/gas/aarch64/etm-wo-invalid.l: New test.
              * testsuite/gas/aarch64/etm-wo-invalid.s: New test.
              * testsuite/gas/aarch64/etm-wo.s: New test.
              * testsuite/gas/aarch64/etm.s: New test.
              * testsuite/gas/aarch64/sysreg.d: system register s2_1_c0_c3_0 disassembled
              now to trcstatr.

opcodes       * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
              TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
              TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
              TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
              TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
              TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
              TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
              TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
              WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
              TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
              TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
              TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR,  TRCTSCTLR, TRCVDARCCTLR,
              TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
              TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 6fdabb6602d535c4693bb436fdf5bb39e9b63849..fbd69ca6efae19e258a0d199a054f159cfc89f81 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,17 @@
+2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * testsuite/gas/aarch64/etm-ro-invalid.d: New test.
+       * testsuite/gas/aarch64/etm-ro-invalid.l: New test.
+       * testsuite/gas/aarch64/etm-ro-invalid.s: New test.
+       * testsuite/gas/aarch64/etm-ro.s: New test.
+       * testsuite/gas/aarch64/etm-wo-invalid.d: New test.
+       * testsuite/gas/aarch64/etm-wo-invalid.l: New test.
+       * testsuite/gas/aarch64/etm-wo-invalid.s: New test.
+       * testsuite/gas/aarch64/etm-wo.s: New test.
+       * testsuite/gas/aarch64/etm.s: New test.
+       * testsuite/gas/aarch64/sysreg.d: system register s2_1_c0_c3_0
+       disassembled now to trcstatr.
+
 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 
        * config/tc-aarch64.c: (aarch64_cpus): Add Cortex-X1.
@@ -5,16 +19,16 @@
 
 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 
-        * testsuite/gas/aarch64/ete.d: New test.
-        * testsuite/gas/aarch64/ete.s: New test.
+       * testsuite/gas/aarch64/ete.d: New test.
+       * testsuite/gas/aarch64/ete.s: New test.
 
 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 
-        * testsuite/gas/aarch64/trbe-invalid.d: New test.
-        * testsuite/gas/aarch64/trbe-invalid.l: New test.
-        * testsuite/gas/aarch64/trbe-invalid.s: New test.
-        * testsuite/gas/aarch64/trbe.d: New test.
-        * testsuite/gas/aarch64/trbe.s: New test.
+       * testsuite/gas/aarch64/trbe-invalid.d: New test.
+       * testsuite/gas/aarch64/trbe-invalid.l: New test.
+       * testsuite/gas/aarch64/trbe-invalid.s: New test.
+       * testsuite/gas/aarch64/trbe.d: New test.
+       * testsuite/gas/aarch64/trbe.s: New test.
 
 2020-09-28  Alex Coplan  <alex.coplan@arm.com>
 

diff --git a/gas/testsuite/gas/aarch64/etm-ro-invalid.d b/gas/testsuite/gas/aarch64/etm-ro-invalid.d
new file mode 100644 (file)
index 0000000..c5dd75a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/etm-ro-invalid.d
@@ -0,0 +1,3 @@
+#name: Invalid ETM read-only system registers usage
+#source: etm-ro-invalid.s
+#warning_output: etm-ro-invalid.l

diff --git a/gas/testsuite/gas/aarch64/etm-ro-invalid.l b/gas/testsuite/gas/aarch64/etm-ro-invalid.l
new file mode 100644 (file)
index 0000000..19bc324
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/etm-ro-invalid.l
@@ -0,0 +1,37 @@
+.*: Assembler messages:
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcauthstatus,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trccidr0,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trccidr1,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trccidr2,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trccidr3,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcdevaff0,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcdevaff1,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcdevarch,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcdevid,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcdevtype,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcidr0,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcidr1,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcidr2,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcidr3,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcidr4,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcidr5,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcidr6,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcidr7,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcidr8,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcidr9,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcidr10,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcidr11,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcidr12,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcidr13,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trclsr,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcoslsr,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcpdsr,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcpidr0,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcpidr1,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcpidr2,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcpidr3,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcpidr4,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcpidr5,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcpidr6,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcpidr7,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr trcstatr,x0'

diff --git a/gas/testsuite/gas/aarch64/etm-ro-invalid.s b/gas/testsuite/gas/aarch64/etm-ro-invalid.s
new file mode 100644 (file)
index 0000000..ae7769f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/etm-ro-invalid.s
@@ -0,0 +1,39 @@
+/* ETMv4 system registers  */
+
+/* Write from read-only system register.  */
+msr trcauthstatus, x0
+msr trccidr0, x0
+msr trccidr1, x0
+msr trccidr2, x0
+msr trccidr3, x0
+msr trcdevaff0, x0
+msr trcdevaff1, x0
+msr trcdevarch, x0
+msr trcdevid, x0
+msr trcdevtype, x0
+msr trcidr0 , x0
+msr trcidr1, x0
+msr trcidr2, x0
+msr trcidr3, x0
+msr trcidr4, x0
+msr trcidr5, x0
+msr trcidr6, x0
+msr trcidr7, x0
+msr trcidr8, x0
+msr trcidr9, x0
+msr trcidr10, x0
+msr trcidr11, x0
+msr trcidr12, x0
+msr trcidr13, x0
+msr trclsr, x0
+msr trcoslsr, x0
+msr trcpdsr, x0
+msr trcpidr0, x0
+msr trcpidr1, x0
+msr trcpidr2, x0
+msr trcpidr3, x0
+msr trcpidr4, x0
+msr trcpidr5, x0
+msr trcpidr6, x0
+msr trcpidr7, x0
+msr trcstatr, x0

diff --git a/gas/testsuite/gas/aarch64/etm-ro.d b/gas/testsuite/gas/aarch64/etm-ro.d
new file mode 100644 (file)
index 0000000..9fd51b6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/etm-ro.d
@@ -0,0 +1,44 @@
+#name: ETM read-only system registers
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[^:]+: d5317ec0        mrs     x0, trcauthstatus
+[^:]+: d5317ce0        mrs     x0, trccidr0
+[^:]+: d5317de0        mrs     x0, trccidr1
+[^:]+: d5317ee0        mrs     x0, trccidr2
+[^:]+: d5317fe0        mrs     x0, trccidr3
+[^:]+: d5317ac0        mrs     x0, trcdevaff0
+[^:]+: d5317bc0        mrs     x0, trcdevaff1
+[^:]+: d5317fc0        mrs     x0, trcdevarch
+[^:]+: d53172e0        mrs     x0, trcdevid
+[^:]+: d53173e0        mrs     x0, trcdevtype
+[^:]+: d53108e0        mrs     x0, trcidr0
+[^:]+: d53109e0        mrs     x0, trcidr1
+[^:]+: d5310ae0        mrs     x0, trcidr2
+[^:]+: d5310be0        mrs     x0, trcidr3
+[^:]+: d5310ce0        mrs     x0, trcidr4
+[^:]+: d5310de0        mrs     x0, trcidr5
+[^:]+: d5310ee0        mrs     x0, trcidr6
+[^:]+: d5310fe0        mrs     x0, trcidr7
+[^:]+: d53100c0        mrs     x0, trcidr8
+[^:]+: d53101c0        mrs     x0, trcidr9
+[^:]+: d53102c0        mrs     x0, trcidr10
+[^:]+: d53103c0        mrs     x0, trcidr11
+[^:]+: d53104c0        mrs     x0, trcidr12
+[^:]+: d53105c0        mrs     x0, trcidr13
+[^:]+: d5317dc0        mrs     x0, trclsr
+[^:]+: d5311180        mrs     x0, trcoslsr
+[^:]+: d5311580        mrs     x0, trcpdsr
+[^:]+: d53178e0        mrs     x0, trcpidr0
+[^:]+: d53179e0        mrs     x0, trcpidr1
+[^:]+: d5317ae0        mrs     x0, trcpidr2
+[^:]+: d5317be0        mrs     x0, trcpidr3
+[^:]+: d53174e0        mrs     x0, trcpidr4
+[^:]+: d53175e0        mrs     x0, trcpidr5
+[^:]+: d53176e0        mrs     x0, trcpidr6
+[^:]+: d53177e0        mrs     x0, trcpidr7
+[^:]+: d5310300        mrs     x0, trcstatr

diff --git a/gas/testsuite/gas/aarch64/etm-ro.s b/gas/testsuite/gas/aarch64/etm-ro.s
new file mode 100644 (file)
index 0000000..0d4507f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/etm-ro.s
@@ -0,0 +1,39 @@
+/* ETMv4 system registers  */
+
+/* Read from read-only system register.  */
+mrs x0, trcauthstatus
+mrs x0, trccidr0
+mrs x0, trccidr1
+mrs x0, trccidr2
+mrs x0, trccidr3
+mrs x0, trcdevaff0
+mrs x0, trcdevaff1
+mrs x0, trcdevarch
+mrs x0, trcdevid
+mrs x0, trcdevtype
+mrs x0, trcidr0
+mrs x0, trcidr1
+mrs x0, trcidr2
+mrs x0, trcidr3
+mrs x0, trcidr4
+mrs x0, trcidr5
+mrs x0, trcidr6
+mrs x0, trcidr7
+mrs x0, trcidr8
+mrs x0, trcidr9
+mrs x0, trcidr10
+mrs x0, trcidr11
+mrs x0, trcidr12
+mrs x0, trcidr13
+mrs x0, trclsr
+mrs x0, trcoslsr
+mrs x0, trcpdsr
+mrs x0, trcpidr0
+mrs x0, trcpidr1
+mrs x0, trcpidr2
+mrs x0, trcpidr3
+mrs x0, trcpidr4
+mrs x0, trcpidr5
+mrs x0, trcpidr6
+mrs x0, trcpidr7
+mrs x0, trcstatr

diff --git a/gas/testsuite/gas/aarch64/etm-wo-invalid.d b/gas/testsuite/gas/aarch64/etm-wo-invalid.d
new file mode 100644 (file)
index 0000000..2a3a8fa
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/etm-wo-invalid.d
@@ -0,0 +1,3 @@
+#name: Invalid ETM write-only system registers usage
+#source: etm-wo-invalid.s
+#warning_output: etm-wo-invalid.l

diff --git a/gas/testsuite/gas/aarch64/etm-wo-invalid.l b/gas/testsuite/gas/aarch64/etm-wo-invalid.l
new file mode 100644 (file)
index 0000000..8364357
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/etm-wo-invalid.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Warning: specified register cannot be read from at operand 2 -- `mrs x0,trclar'
+.*: Warning: specified register cannot be read from at operand 2 -- `mrs x0,trcoslar'

diff --git a/gas/testsuite/gas/aarch64/etm-wo-invalid.s b/gas/testsuite/gas/aarch64/etm-wo-invalid.s
new file mode 100644 (file)
index 0000000..bbf28bc
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/etm-wo-invalid.s
@@ -0,0 +1,5 @@
+/* ETMv4 system registers  */
+
+/* Read from write-only system register.  */
+mrs x0, trclar
+mrs x0, trcoslar

diff --git a/gas/testsuite/gas/aarch64/etm-wo.d b/gas/testsuite/gas/aarch64/etm-wo.d
new file mode 100644 (file)
index 0000000..3caac1d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/etm-wo.d
@@ -0,0 +1,10 @@
+#name: ETM write-only system registers
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[^:]+: d5117cc0        msr     trclar, x0
+[^:]+: d5111080        msr     trcoslar, x0

diff --git a/gas/testsuite/gas/aarch64/etm-wo.s b/gas/testsuite/gas/aarch64/etm-wo.s
new file mode 100644 (file)
index 0000000..8a8afcd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/etm-wo.s
@@ -0,0 +1,5 @@
+/* ETMv4 system registers  */
+
+/* Write to write-only system register.  */
+msr trclar, x0
+msr trcoslar, x0

diff --git a/gas/testsuite/gas/aarch64/etm.d b/gas/testsuite/gas/aarch64/etm.d
new file mode 100644 (file)
index 0000000..4472b2f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/etm.d
@@ -0,0 +1,362 @@
+#name: ETM System registers
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[^:]+: d5312040        mrs     x0, trcacatr0
+[^:]+: d5312240        mrs     x0, trcacatr1
+[^:]+: d5312440        mrs     x0, trcacatr2
+[^:]+: d5312640        mrs     x0, trcacatr3
+[^:]+: d5312840        mrs     x0, trcacatr4
+[^:]+: d5312a40        mrs     x0, trcacatr5
+[^:]+: d5312c40        mrs     x0, trcacatr6
+[^:]+: d5312e40        mrs     x0, trcacatr7
+[^:]+: d5312060        mrs     x0, trcacatr8
+[^:]+: d5312260        mrs     x0, trcacatr9
+[^:]+: d5312460        mrs     x0, trcacatr10
+[^:]+: d5312660        mrs     x0, trcacatr11
+[^:]+: d5312860        mrs     x0, trcacatr12
+[^:]+: d5312a60        mrs     x0, trcacatr13
+[^:]+: d5312c60        mrs     x0, trcacatr14
+[^:]+: d5312e60        mrs     x0, trcacatr15
+[^:]+: d5312000        mrs     x0, trcacvr0
+[^:]+: d5312200        mrs     x0, trcacvr1
+[^:]+: d5312400        mrs     x0, trcacvr2
+[^:]+: d5312600        mrs     x0, trcacvr3
+[^:]+: d5312800        mrs     x0, trcacvr4
+[^:]+: d5312a00        mrs     x0, trcacvr5
+[^:]+: d5312c00        mrs     x0, trcacvr6
+[^:]+: d5312e00        mrs     x0, trcacvr7
+[^:]+: d5312020        mrs     x0, trcacvr8
+[^:]+: d5312220        mrs     x0, trcacvr9
+[^:]+: d5312420        mrs     x0, trcacvr10
+[^:]+: d5312620        mrs     x0, trcacvr11
+[^:]+: d5312820        mrs     x0, trcacvr12
+[^:]+: d5312a20        mrs     x0, trcacvr13
+[^:]+: d5312c20        mrs     x0, trcacvr14
+[^:]+: d5312e20        mrs     x0, trcacvr15
+[^:]+: d5310600        mrs     x0, trcauxctlr
+[^:]+: d5310f00        mrs     x0, trcbbctlr
+[^:]+: d5310e00        mrs     x0, trcccctlr
+[^:]+: d5313040        mrs     x0, trccidcctlr0
+[^:]+: d5313140        mrs     x0, trccidcctlr1
+[^:]+: d5313000        mrs     x0, trccidcvr0
+[^:]+: d5313200        mrs     x0, trccidcvr1
+[^:]+: d5313400        mrs     x0, trccidcvr2
+[^:]+: d5313600        mrs     x0, trccidcvr3
+[^:]+: d5313800        mrs     x0, trccidcvr4
+[^:]+: d5313a00        mrs     x0, trccidcvr5
+[^:]+: d5313c00        mrs     x0, trccidcvr6
+[^:]+: d5313e00        mrs     x0, trccidcvr7
+[^:]+: d53179c0        mrs     x0, trcclaimclr
+[^:]+: d53178c0        mrs     x0, trcclaimset
+[^:]+: d53104a0        mrs     x0, trccntctlr0
+[^:]+: d53105a0        mrs     x0, trccntctlr1
+[^:]+: d53106a0        mrs     x0, trccntctlr2
+[^:]+: d53107a0        mrs     x0, trccntctlr3
+[^:]+: d53100a0        mrs     x0, trccntrldvr0
+[^:]+: d53101a0        mrs     x0, trccntrldvr1
+[^:]+: d53102a0        mrs     x0, trccntrldvr2
+[^:]+: d53103a0        mrs     x0, trccntrldvr3
+[^:]+: d53108a0        mrs     x0, trccntvr0
+[^:]+: d53109a0        mrs     x0, trccntvr1
+[^:]+: d5310aa0        mrs     x0, trccntvr2
+[^:]+: d5310ba0        mrs     x0, trccntvr3
+[^:]+: d5310400        mrs     x0, trcconfigr
+[^:]+: d53120c0        mrs     x0, trcdvcmr0
+[^:]+: d53124c0        mrs     x0, trcdvcmr1
+[^:]+: d53128c0        mrs     x0, trcdvcmr2
+[^:]+: d5312cc0        mrs     x0, trcdvcmr3
+[^:]+: d53120e0        mrs     x0, trcdvcmr4
+[^:]+: d53124e0        mrs     x0, trcdvcmr5
+[^:]+: d53128e0        mrs     x0, trcdvcmr6
+[^:]+: d5312ce0        mrs     x0, trcdvcmr7
+[^:]+: d5312080        mrs     x0, trcdvcvr0
+[^:]+: d5312480        mrs     x0, trcdvcvr1
+[^:]+: d5312880        mrs     x0, trcdvcvr2
+[^:]+: d5312c80        mrs     x0, trcdvcvr3
+[^:]+: d53120a0        mrs     x0, trcdvcvr4
+[^:]+: d53124a0        mrs     x0, trcdvcvr5
+[^:]+: d53128a0        mrs     x0, trcdvcvr6
+[^:]+: d5312ca0        mrs     x0, trcdvcvr7
+[^:]+: d5310800        mrs     x0, trceventctl0r
+[^:]+: d5310900        mrs     x0, trceventctl1r
+[^:]+: d5310880        mrs     x0, trcextinselr0
+[^:]+: d5310880        mrs     x0, trcextinselr0
+[^:]+: d5310980        mrs     x0, trcextinselr1
+[^:]+: d5310a80        mrs     x0, trcextinselr2
+[^:]+: d5310b80        mrs     x0, trcextinselr3
+[^:]+: d53100e0        mrs     x0, trcimspec0
+[^:]+: d53100e0        mrs     x0, trcimspec0
+[^:]+: d53101e0        mrs     x0, trcimspec1
+[^:]+: d53102e0        mrs     x0, trcimspec2
+[^:]+: d53103e0        mrs     x0, trcimspec3
+[^:]+: d53104e0        mrs     x0, trcimspec4
+[^:]+: d53105e0        mrs     x0, trcimspec5
+[^:]+: d53106e0        mrs     x0, trcimspec6
+[^:]+: d53107e0        mrs     x0, trcimspec7
+[^:]+: d5317080        mrs     x0, trcitctrl
+[^:]+: d5311480        mrs     x0, trcpdcr
+[^:]+: d5310100        mrs     x0, trcprgctlr
+[^:]+: d5310200        mrs     x0, trcprocselr
+[^:]+: d5310120        mrs     x0, trcqctlr
+[^:]+: d5311200        mrs     x0, trcrsctlr2
+[^:]+: d5311300        mrs     x0, trcrsctlr3
+[^:]+: d5311400        mrs     x0, trcrsctlr4
+[^:]+: d5311500        mrs     x0, trcrsctlr5
+[^:]+: d5311600        mrs     x0, trcrsctlr6
+[^:]+: d5311700        mrs     x0, trcrsctlr7
+[^:]+: d5311800        mrs     x0, trcrsctlr8
+[^:]+: d5311900        mrs     x0, trcrsctlr9
+[^:]+: d5311a00        mrs     x0, trcrsctlr10
+[^:]+: d5311b00        mrs     x0, trcrsctlr11
+[^:]+: d5311c00        mrs     x0, trcrsctlr12
+[^:]+: d5311d00        mrs     x0, trcrsctlr13
+[^:]+: d5311e00        mrs     x0, trcrsctlr14
+[^:]+: d5311f00        mrs     x0, trcrsctlr15
+[^:]+: d5311020        mrs     x0, trcrsctlr16
+[^:]+: d5311120        mrs     x0, trcrsctlr17
+[^:]+: d5311220        mrs     x0, trcrsctlr18
+[^:]+: d5311320        mrs     x0, trcrsctlr19
+[^:]+: d5311420        mrs     x0, trcrsctlr20
+[^:]+: d5311520        mrs     x0, trcrsctlr21
+[^:]+: d5311620        mrs     x0, trcrsctlr22
+[^:]+: d5311720        mrs     x0, trcrsctlr23
+[^:]+: d5311820        mrs     x0, trcrsctlr24
+[^:]+: d5311920        mrs     x0, trcrsctlr25
+[^:]+: d5311a20        mrs     x0, trcrsctlr26
+[^:]+: d5311b20        mrs     x0, trcrsctlr27
+[^:]+: d5311c20        mrs     x0, trcrsctlr28
+[^:]+: d5311d20        mrs     x0, trcrsctlr29
+[^:]+: d5311e20        mrs     x0, trcrsctlr30
+[^:]+: d5311f20        mrs     x0, trcrsctlr31
+[^:]+: d5310080        mrs     x0, trcseqevr0
+[^:]+: d5310180        mrs     x0, trcseqevr1
+[^:]+: d5310280        mrs     x0, trcseqevr2
+[^:]+: d5310680        mrs     x0, trcseqrstevr
+[^:]+: d5310780        mrs     x0, trcseqstr
+[^:]+: d5311040        mrs     x0, trcssccr0
+[^:]+: d5311140        mrs     x0, trcssccr1
+[^:]+: d5311240        mrs     x0, trcssccr2
+[^:]+: d5311340        mrs     x0, trcssccr3
+[^:]+: d5311440        mrs     x0, trcssccr4
+[^:]+: d5311540        mrs     x0, trcssccr5
+[^:]+: d5311640        mrs     x0, trcssccr6
+[^:]+: d5311740        mrs     x0, trcssccr7
+[^:]+: d5311840        mrs     x0, trcsscsr0
+[^:]+: d5311940        mrs     x0, trcsscsr1
+[^:]+: d5311a40        mrs     x0, trcsscsr2
+[^:]+: d5311b40        mrs     x0, trcsscsr3
+[^:]+: d5311c40        mrs     x0, trcsscsr4
+[^:]+: d5311d40        mrs     x0, trcsscsr5
+[^:]+: d5311e40        mrs     x0, trcsscsr6
+[^:]+: d5311f40        mrs     x0, trcsscsr7
+[^:]+: d5311060        mrs     x0, trcsspcicr0
+[^:]+: d5311160        mrs     x0, trcsspcicr1
+[^:]+: d5311260        mrs     x0, trcsspcicr2
+[^:]+: d5311360        mrs     x0, trcsspcicr3
+[^:]+: d5311460        mrs     x0, trcsspcicr4
+[^:]+: d5311560        mrs     x0, trcsspcicr5
+[^:]+: d5311660        mrs     x0, trcsspcicr6
+[^:]+: d5311760        mrs     x0, trcsspcicr7
+[^:]+: d5310b00        mrs     x0, trcstallctlr
+[^:]+: d5310d00        mrs     x0, trcsyncpr
+[^:]+: d5310020        mrs     x0, trctraceidr
+[^:]+: d5310c00        mrs     x0, trctsctlr
+[^:]+: d5310a40        mrs     x0, trcvdarcctlr
+[^:]+: d5310840        mrs     x0, trcvdctlr
+[^:]+: d5310940        mrs     x0, trcvdsacctlr
+[^:]+: d5310040        mrs     x0, trcvictlr
+[^:]+: d5310140        mrs     x0, trcviiectlr
+[^:]+: d5310340        mrs     x0, trcvipcssctlr
+[^:]+: d5310240        mrs     x0, trcvissctlr
+[^:]+: d5313240        mrs     x0, trcvmidcctlr0
+[^:]+: d5313340        mrs     x0, trcvmidcctlr1
+[^:]+: d5313020        mrs     x0, trcvmidcvr0
+[^:]+: d5313220        mrs     x0, trcvmidcvr1
+[^:]+: d5313420        mrs     x0, trcvmidcvr2
+[^:]+: d5313620        mrs     x0, trcvmidcvr3
+[^:]+: d5313820        mrs     x0, trcvmidcvr4
+[^:]+: d5313a20        mrs     x0, trcvmidcvr5
+[^:]+: d5313c20        mrs     x0, trcvmidcvr6
+[^:]+: d5313e20        mrs     x0, trcvmidcvr7
+[^:]+: d5112040        msr     trcacatr0, x0
+[^:]+: d5112240        msr     trcacatr1, x0
+[^:]+: d5112440        msr     trcacatr2, x0
+[^:]+: d5112640        msr     trcacatr3, x0
+[^:]+: d5112840        msr     trcacatr4, x0
+[^:]+: d5112a40        msr     trcacatr5, x0
+[^:]+: d5112c40        msr     trcacatr6, x0
+[^:]+: d5112e40        msr     trcacatr7, x0
+[^:]+: d5112060        msr     trcacatr8, x0
+[^:]+: d5112260        msr     trcacatr9, x0
+[^:]+: d5112460        msr     trcacatr10, x0
+[^:]+: d5112660        msr     trcacatr11, x0
+[^:]+: d5112860        msr     trcacatr12, x0
+[^:]+: d5112a60        msr     trcacatr13, x0
+[^:]+: d5112c60        msr     trcacatr14, x0
+[^:]+: d5112e60        msr     trcacatr15, x0
+[^:]+: d5112000        msr     trcacvr0, x0
+[^:]+: d5112200        msr     trcacvr1, x0
+[^:]+: d5112400        msr     trcacvr2, x0
+[^:]+: d5112600        msr     trcacvr3, x0
+[^:]+: d5112800        msr     trcacvr4, x0
+[^:]+: d5112a00        msr     trcacvr5, x0
+[^:]+: d5112c00        msr     trcacvr6, x0
+[^:]+: d5112e00        msr     trcacvr7, x0
+[^:]+: d5112020        msr     trcacvr8, x0
+[^:]+: d5112220        msr     trcacvr9, x0
+[^:]+: d5112420        msr     trcacvr10, x0
+[^:]+: d5112620        msr     trcacvr11, x0
+[^:]+: d5112820        msr     trcacvr12, x0
+[^:]+: d5112a20        msr     trcacvr13, x0
+[^:]+: d5112c20        msr     trcacvr14, x0
+[^:]+: d5112e20        msr     trcacvr15, x0
+[^:]+: d5110600        msr     trcauxctlr, x0
+[^:]+: d5110f00        msr     trcbbctlr, x0
+[^:]+: d5110e00        msr     trcccctlr, x0
+[^:]+: d5113040        msr     trccidcctlr0, x0
+[^:]+: d5113140        msr     trccidcctlr1, x0
+[^:]+: d5113000        msr     trccidcvr0, x0
+[^:]+: d5113200        msr     trccidcvr1, x0
+[^:]+: d5113400        msr     trccidcvr2, x0
+[^:]+: d5113600        msr     trccidcvr3, x0
+[^:]+: d5113800        msr     trccidcvr4, x0
+[^:]+: d5113a00        msr     trccidcvr5, x0
+[^:]+: d5113c00        msr     trccidcvr6, x0
+[^:]+: d5113e00        msr     trccidcvr7, x0
+[^:]+: d51179c0        msr     trcclaimclr, x0
+[^:]+: d51178c0        msr     trcclaimset, x0
+[^:]+: d51104a0        msr     trccntctlr0, x0
+[^:]+: d51105a0        msr     trccntctlr1, x0
+[^:]+: d51106a0        msr     trccntctlr2, x0
+[^:]+: d51107a0        msr     trccntctlr3, x0
+[^:]+: d51100a0        msr     trccntrldvr0, x0
+[^:]+: d51101a0        msr     trccntrldvr1, x0
+[^:]+: d51102a0        msr     trccntrldvr2, x0
+[^:]+: d51103a0        msr     trccntrldvr3, x0
+[^:]+: d51108a0        msr     trccntvr0, x0
+[^:]+: d51109a0        msr     trccntvr1, x0
+[^:]+: d5110aa0        msr     trccntvr2, x0
+[^:]+: d5110ba0        msr     trccntvr3, x0
+[^:]+: d5110400        msr     trcconfigr, x0
+[^:]+: d51120c0        msr     trcdvcmr0, x0
+[^:]+: d51124c0        msr     trcdvcmr1, x0
+[^:]+: d51128c0        msr     trcdvcmr2, x0
+[^:]+: d5112cc0        msr     trcdvcmr3, x0
+[^:]+: d51120e0        msr     trcdvcmr4, x0
+[^:]+: d51124e0        msr     trcdvcmr5, x0
+[^:]+: d51128e0        msr     trcdvcmr6, x0
+[^:]+: d5112ce0        msr     trcdvcmr7, x0
+[^:]+: d5112080        msr     trcdvcvr0, x0
+[^:]+: d5112480        msr     trcdvcvr1, x0
+[^:]+: d5112880        msr     trcdvcvr2, x0
+[^:]+: d5112c80        msr     trcdvcvr3, x0
+[^:]+: d51120a0        msr     trcdvcvr4, x0
+[^:]+: d51124a0        msr     trcdvcvr5, x0
+[^:]+: d51128a0        msr     trcdvcvr6, x0
+[^:]+: d5112ca0        msr     trcdvcvr7, x0
+[^:]+: d5110800        msr     trceventctl0r, x0
+[^:]+: d5110900        msr     trceventctl1r, x0
+[^:]+: d5110880        msr     trcextinselr0, x0
+[^:]+: d5110880        msr     trcextinselr0, x0
+[^:]+: d5110980        msr     trcextinselr1, x0
+[^:]+: d5110a80        msr     trcextinselr2, x0
+[^:]+: d5110b80        msr     trcextinselr3, x0
+[^:]+: d51100e0        msr     trcimspec0, x0
+[^:]+: d51100e0        msr     trcimspec0, x0
+[^:]+: d51101e0        msr     trcimspec1, x0
+[^:]+: d51102e0        msr     trcimspec2, x0
+[^:]+: d51103e0        msr     trcimspec3, x0
+[^:]+: d51104e0        msr     trcimspec4, x0
+[^:]+: d51105e0        msr     trcimspec5, x0
+[^:]+: d51106e0        msr     trcimspec6, x0
+[^:]+: d51107e0        msr     trcimspec7, x0
+[^:]+: d5117080        msr     trcitctrl, x0
+[^:]+: d5111480        msr     trcpdcr, x0
+[^:]+: d5110100        msr     trcprgctlr, x0
+[^:]+: d5110200        msr     trcprocselr, x0
+[^:]+: d5110120        msr     trcqctlr, x0
+[^:]+: d5111200        msr     trcrsctlr2, x0
+[^:]+: d5111300        msr     trcrsctlr3, x0
+[^:]+: d5111400        msr     trcrsctlr4, x0
+[^:]+: d5111500        msr     trcrsctlr5, x0
+[^:]+: d5111600        msr     trcrsctlr6, x0
+[^:]+: d5111700        msr     trcrsctlr7, x0
+[^:]+: d5111800        msr     trcrsctlr8, x0
+[^:]+: d5111900        msr     trcrsctlr9, x0
+[^:]+: d5111a00        msr     trcrsctlr10, x0
+[^:]+: d5111b00        msr     trcrsctlr11, x0
+[^:]+: d5111c00        msr     trcrsctlr12, x0
+[^:]+: d5111d00        msr     trcrsctlr13, x0
+[^:]+: d5111e00        msr     trcrsctlr14, x0
+[^:]+: d5111f00        msr     trcrsctlr15, x0
+[^:]+: d5111020        msr     trcrsctlr16, x0
+[^:]+: d5111120        msr     trcrsctlr17, x0
+[^:]+: d5111220        msr     trcrsctlr18, x0
+[^:]+: d5111320        msr     trcrsctlr19, x0
+[^:]+: d5111420        msr     trcrsctlr20, x0
+[^:]+: d5111520        msr     trcrsctlr21, x0
+[^:]+: d5111620        msr     trcrsctlr22, x0
+[^:]+: d5111720        msr     trcrsctlr23, x0
+[^:]+: d5111820        msr     trcrsctlr24, x0
+[^:]+: d5111920        msr     trcrsctlr25, x0
+[^:]+: d5111a20        msr     trcrsctlr26, x0
+[^:]+: d5111b20        msr     trcrsctlr27, x0
+[^:]+: d5111c20        msr     trcrsctlr28, x0
+[^:]+: d5111d20        msr     trcrsctlr29, x0
+[^:]+: d5111e20        msr     trcrsctlr30, x0
+[^:]+: d5111f20        msr     trcrsctlr31, x0
+[^:]+: d5110080        msr     trcseqevr0, x0
+[^:]+: d5110180        msr     trcseqevr1, x0
+[^:]+: d5110280        msr     trcseqevr2, x0
+[^:]+: d5110680        msr     trcseqrstevr, x0
+[^:]+: d5110780        msr     trcseqstr, x0
+[^:]+: d5111040        msr     trcssccr0, x0
+[^:]+: d5111140        msr     trcssccr1, x0
+[^:]+: d5111240        msr     trcssccr2, x0
+[^:]+: d5111340        msr     trcssccr3, x0
+[^:]+: d5111440        msr     trcssccr4, x0
+[^:]+: d5111540        msr     trcssccr5, x0
+[^:]+: d5111640        msr     trcssccr6, x0
+[^:]+: d5111740        msr     trcssccr7, x0
+[^:]+: d5111840        msr     trcsscsr0, x0
+[^:]+: d5111940        msr     trcsscsr1, x0
+[^:]+: d5111a40        msr     trcsscsr2, x0
+[^:]+: d5111b40        msr     trcsscsr3, x0
+[^:]+: d5111c40        msr     trcsscsr4, x0
+[^:]+: d5111d40        msr     trcsscsr5, x0
+[^:]+: d5111e40        msr     trcsscsr6, x0
+[^:]+: d5111f40        msr     trcsscsr7, x0
+[^:]+: d5111060        msr     trcsspcicr0, x0
+[^:]+: d5111160        msr     trcsspcicr1, x0
+[^:]+: d5111260        msr     trcsspcicr2, x0
+[^:]+: d5111360        msr     trcsspcicr3, x0
+[^:]+: d5111460        msr     trcsspcicr4, x0
+[^:]+: d5111560        msr     trcsspcicr5, x0
+[^:]+: d5111660        msr     trcsspcicr6, x0
+[^:]+: d5111760        msr     trcsspcicr7, x0
+[^:]+: d5110b00        msr     trcstallctlr, x0
+[^:]+: d5110d00        msr     trcsyncpr, x0
+[^:]+: d5110020        msr     trctraceidr, x0
+[^:]+: d5110c00        msr     trctsctlr, x0
+[^:]+: d5110a40        msr     trcvdarcctlr, x0
+[^:]+: d5110840        msr     trcvdctlr, x0
+[^:]+: d5110940        msr     trcvdsacctlr, x0
+[^:]+: d5110040        msr     trcvictlr, x0
+[^:]+: d5110140        msr     trcviiectlr, x0
+[^:]+: d5110340        msr     trcvipcssctlr, x0
+[^:]+: d5110240        msr     trcvissctlr, x0
+[^:]+: d5113240        msr     trcvmidcctlr0, x0
+[^:]+: d5113340        msr     trcvmidcctlr1, x0
+[^:]+: d5113020        msr     trcvmidcvr0, x0
+[^:]+: d5113220        msr     trcvmidcvr1, x0
+[^:]+: d5113420        msr     trcvmidcvr2, x0
+[^:]+: d5113620        msr     trcvmidcvr3, x0
+[^:]+: d5113820        msr     trcvmidcvr4, x0
+[^:]+: d5113a20        msr     trcvmidcvr5, x0
+[^:]+: d5113c20        msr     trcvmidcvr6, x0
+[^:]+: d5113e20        msr     trcvmidcvr7, x0

diff --git a/gas/testsuite/gas/aarch64/etm.s b/gas/testsuite/gas/aarch64/etm.s
new file mode 100644 (file)
index 0000000..8f1947d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/etm.s
@@ -0,0 +1,360 @@
+/* ETMv4 system registers.  */
+
+/* Read from system register.  */
+
+mrs x0, trcacatr0
+mrs x0, trcacatr1
+mrs x0, trcacatr2
+mrs x0, trcacatr3
+mrs x0, trcacatr4
+mrs x0, trcacatr5
+mrs x0, trcacatr6
+mrs x0, trcacatr7
+mrs x0, trcacatr8
+mrs x0, trcacatr9
+mrs x0, trcacatr10
+mrs x0, trcacatr11
+mrs x0, trcacatr12
+mrs x0, trcacatr13
+mrs x0, trcacatr14
+mrs x0, trcacatr15
+mrs x0, trcacvr0
+mrs x0, trcacvr1
+mrs x0, trcacvr2
+mrs x0, trcacvr3
+mrs x0, trcacvr4
+mrs x0, trcacvr5
+mrs x0, trcacvr6
+mrs x0, trcacvr7
+mrs x0, trcacvr8
+mrs x0, trcacvr9
+mrs x0, trcacvr10
+mrs x0, trcacvr11
+mrs x0, trcacvr12
+mrs x0, trcacvr13
+mrs x0, trcacvr14
+mrs x0, trcacvr15
+mrs x0, trcauxctlr
+mrs x0, trcbbctlr
+mrs x0, trcccctlr
+mrs x0, trccidcctlr0
+mrs x0, trccidcctlr1
+mrs x0, trccidcvr0
+mrs x0, trccidcvr1
+mrs x0, trccidcvr2
+mrs x0, trccidcvr3
+mrs x0, trccidcvr4
+mrs x0, trccidcvr5
+mrs x0, trccidcvr6
+mrs x0, trccidcvr7
+mrs x0, trcclaimclr
+mrs x0, trcclaimset
+mrs x0, trccntctlr0
+mrs x0, trccntctlr1
+mrs x0, trccntctlr2
+mrs x0, trccntctlr3
+mrs x0, trccntrldvr0
+mrs x0, trccntrldvr1
+mrs x0, trccntrldvr2
+mrs x0, trccntrldvr3
+mrs x0, trccntvr0
+mrs x0, trccntvr1
+mrs x0, trccntvr2
+mrs x0, trccntvr3
+mrs x0, trcconfigr
+mrs x0, trcdvcmr0
+mrs x0, trcdvcmr1
+mrs x0, trcdvcmr2
+mrs x0, trcdvcmr3
+mrs x0, trcdvcmr4
+mrs x0, trcdvcmr5
+mrs x0, trcdvcmr6
+mrs x0, trcdvcmr7
+mrs x0, trcdvcvr0
+mrs x0, trcdvcvr1
+mrs x0, trcdvcvr2
+mrs x0, trcdvcvr3
+mrs x0, trcdvcvr4
+mrs x0, trcdvcvr5
+mrs x0, trcdvcvr6
+mrs x0, trcdvcvr7
+mrs x0, trceventctl0r
+mrs x0, trceventctl1r
+mrs x0, trcextinselr0
+mrs x0, trcextinselr
+mrs x0, trcextinselr1
+mrs x0, trcextinselr2
+mrs x0, trcextinselr3
+mrs x0, trcimspec0
+mrs x0, trcimspec0
+mrs x0, trcimspec1
+mrs x0, trcimspec2
+mrs x0, trcimspec3
+mrs x0, trcimspec4
+mrs x0, trcimspec5
+mrs x0, trcimspec6
+mrs x0, trcimspec7
+mrs x0, trcitctrl
+mrs x0, trcpdcr
+mrs x0, trcprgctlr
+mrs x0, trcprocselr
+mrs x0, trcqctlr
+mrs x0, trcrsctlr2
+mrs x0, trcrsctlr3
+mrs x0, trcrsctlr4
+mrs x0, trcrsctlr5
+mrs x0, trcrsctlr6
+mrs x0, trcrsctlr7
+mrs x0, trcrsctlr8
+mrs x0, trcrsctlr9
+mrs x0, trcrsctlr10
+mrs x0, trcrsctlr11
+mrs x0, trcrsctlr12
+mrs x0, trcrsctlr13
+mrs x0, trcrsctlr14
+mrs x0, trcrsctlr15
+mrs x0, trcrsctlr16
+mrs x0, trcrsctlr17
+mrs x0, trcrsctlr18
+mrs x0, trcrsctlr19
+mrs x0, trcrsctlr20
+mrs x0, trcrsctlr21
+mrs x0, trcrsctlr22
+mrs x0, trcrsctlr23
+mrs x0, trcrsctlr24
+mrs x0, trcrsctlr25
+mrs x0, trcrsctlr26
+mrs x0, trcrsctlr27
+mrs x0, trcrsctlr28
+mrs x0, trcrsctlr29
+mrs x0, trcrsctlr30
+mrs x0, trcrsctlr31
+mrs x0, trcseqevr0
+mrs x0, trcseqevr1
+mrs x0, trcseqevr2
+mrs x0, trcseqrstevr
+mrs x0, trcseqstr
+mrs x0, trcssccr0
+mrs x0, trcssccr1
+mrs x0, trcssccr2
+mrs x0, trcssccr3
+mrs x0, trcssccr4
+mrs x0, trcssccr5
+mrs x0, trcssccr6
+mrs x0, trcssccr7
+mrs x0, trcsscsr0
+mrs x0, trcsscsr1
+mrs x0, trcsscsr2
+mrs x0, trcsscsr3
+mrs x0, trcsscsr4
+mrs x0, trcsscsr5
+mrs x0, trcsscsr6
+mrs x0, trcsscsr7
+mrs x0, trcsspcicr0
+mrs x0, trcsspcicr1
+mrs x0, trcsspcicr2
+mrs x0, trcsspcicr3
+mrs x0, trcsspcicr4
+mrs x0, trcsspcicr5
+mrs x0, trcsspcicr6
+mrs x0, trcsspcicr7
+mrs x0, trcstallctlr
+mrs x0, trcsyncpr
+mrs x0, trctraceidr
+mrs x0, trctsctlr
+mrs x0, trcvdarcctlr
+mrs x0, trcvdctlr
+mrs x0, trcvdsacctlr
+mrs x0, trcvictlr
+mrs x0, trcviiectlr
+mrs x0, trcvipcssctlr
+mrs x0, trcvissctlr
+mrs x0, trcvmidcctlr0
+mrs x0, trcvmidcctlr1
+mrs x0, trcvmidcvr0
+mrs x0, trcvmidcvr1
+mrs x0, trcvmidcvr2
+mrs x0, trcvmidcvr3
+mrs x0, trcvmidcvr4
+mrs x0, trcvmidcvr5
+mrs x0, trcvmidcvr6
+mrs x0, trcvmidcvr7
+
+/* Write to system register.  */
+msr trcacatr0, x0
+msr trcacatr1, x0
+msr trcacatr2, x0
+msr trcacatr3, x0
+msr trcacatr4, x0
+msr trcacatr5, x0
+msr trcacatr6, x0
+msr trcacatr7, x0
+msr trcacatr8, x0
+msr trcacatr9, x0
+msr trcacatr10, x0
+msr trcacatr11, x0
+msr trcacatr12, x0
+msr trcacatr13, x0
+msr trcacatr14, x0
+msr trcacatr15, x0
+msr trcacvr0, x0
+msr trcacvr1, x0
+msr trcacvr2, x0
+msr trcacvr3, x0
+msr trcacvr4, x0
+msr trcacvr5, x0
+msr trcacvr6, x0
+msr trcacvr7, x0
+msr trcacvr8, x0
+msr trcacvr9, x0
+msr trcacvr10, x0
+msr trcacvr11, x0
+msr trcacvr12, x0
+msr trcacvr13, x0
+msr trcacvr14, x0
+msr trcacvr15, x0
+msr trcauxctlr, x0
+msr trcbbctlr, x0
+msr trcccctlr, x0
+msr trccidcctlr0, x0
+msr trccidcctlr1, x0
+msr trccidcvr0, x0
+msr trccidcvr1, x0
+msr trccidcvr2, x0
+msr trccidcvr3, x0
+msr trccidcvr4, x0
+msr trccidcvr5, x0
+msr trccidcvr6, x0
+msr trccidcvr7, x0
+msr trcclaimclr, x0
+msr trcclaimset, x0
+msr trccntctlr0, x0
+msr trccntctlr1, x0
+msr trccntctlr2, x0
+msr trccntctlr3, x0
+msr trccntrldvr0, x0
+msr trccntrldvr1, x0
+msr trccntrldvr2, x0
+msr trccntrldvr3, x0
+msr trccntvr0, x0
+msr trccntvr1, x0
+msr trccntvr2, x0
+msr trccntvr3, x0
+msr trcconfigr, x0
+msr trcdvcmr0, x0
+msr trcdvcmr1, x0
+msr trcdvcmr2, x0
+msr trcdvcmr3, x0
+msr trcdvcmr4, x0
+msr trcdvcmr5, x0
+msr trcdvcmr6, x0
+msr trcdvcmr7, x0
+msr trcdvcvr0, x0
+msr trcdvcvr1, x0
+msr trcdvcvr2, x0
+msr trcdvcvr3, x0
+msr trcdvcvr4, x0
+msr trcdvcvr5, x0
+msr trcdvcvr6, x0
+msr trcdvcvr7, x0
+msr trceventctl0r, x0
+msr trceventctl1r, x0
+msr trcextinselr0, x0
+msr trcextinselr, x0
+msr trcextinselr1, x0
+msr trcextinselr2, x0
+msr trcextinselr3, x0
+msr trcimspec0, x0
+msr trcimspec0, x0
+msr trcimspec1, x0
+msr trcimspec2, x0
+msr trcimspec3, x0
+msr trcimspec4, x0
+msr trcimspec5, x0
+msr trcimspec6, x0
+msr trcimspec7, x0
+msr trcitctrl, x0
+msr trcpdcr, x0
+msr trcprgctlr, x0
+msr trcprocselr, x0
+msr trcqctlr, x0
+msr trcrsctlr2, x0
+msr trcrsctlr3, x0
+msr trcrsctlr4, x0
+msr trcrsctlr5, x0
+msr trcrsctlr6, x0
+msr trcrsctlr7, x0
+msr trcrsctlr8, x0
+msr trcrsctlr9, x0
+msr trcrsctlr10, x0
+msr trcrsctlr11, x0
+msr trcrsctlr12, x0
+msr trcrsctlr13, x0
+msr trcrsctlr14, x0
+msr trcrsctlr15, x0
+msr trcrsctlr16, x0
+msr trcrsctlr17, x0
+msr trcrsctlr18, x0
+msr trcrsctlr19, x0
+msr trcrsctlr20, x0
+msr trcrsctlr21, x0
+msr trcrsctlr22, x0
+msr trcrsctlr23, x0
+msr trcrsctlr24, x0
+msr trcrsctlr25, x0
+msr trcrsctlr26, x0
+msr trcrsctlr27, x0
+msr trcrsctlr28, x0
+msr trcrsctlr29, x0
+msr trcrsctlr30, x0
+msr trcrsctlr31, x0
+msr trcseqevr0, x0
+msr trcseqevr1, x0
+msr trcseqevr2, x0
+msr trcseqrstevr, x0
+msr trcseqstr, x0
+msr trcssccr0, x0
+msr trcssccr1, x0
+msr trcssccr2, x0
+msr trcssccr3, x0
+msr trcssccr4, x0
+msr trcssccr5, x0
+msr trcssccr6, x0
+msr trcssccr7, x0
+msr trcsscsr0, x0
+msr trcsscsr1, x0
+msr trcsscsr2, x0
+msr trcsscsr3, x0
+msr trcsscsr4, x0
+msr trcsscsr5, x0
+msr trcsscsr6, x0
+msr trcsscsr7, x0
+msr trcsspcicr0, x0
+msr trcsspcicr1, x0
+msr trcsspcicr2, x0
+msr trcsspcicr3, x0
+msr trcsspcicr4, x0
+msr trcsspcicr5, x0
+msr trcsspcicr6, x0
+msr trcsspcicr7, x0
+msr trcstallctlr, x0
+msr trcsyncpr, x0
+msr trctraceidr, x0
+msr trctsctlr, x0
+msr trcvdarcctlr, x0
+msr trcvdctlr, x0
+msr trcvdsacctlr, x0
+msr trcvictlr, x0
+msr trcviiectlr, x0
+msr trcvipcssctlr, x0
+msr trcvissctlr, x0
+msr trcvmidcctlr0, x0
+msr trcvmidcctlr1, x0
+msr trcvmidcvr0, x0
+msr trcvmidcvr1, x0
+msr trcvmidcvr2, x0
+msr trcvmidcvr3, x0
+msr trcvmidcvr4, x0
+msr trcvmidcvr5, x0
+msr trcvmidcvr6, x0
+msr trcvmidcvr7, x0

diff --git a/gas/testsuite/gas/aarch64/sysreg.d b/gas/testsuite/gas/aarch64/sysreg.d
index d4f5402050d19d3c112afe72e46fa053fc87f98f..35b829e0dd3a047985164e8172b6bae5622f7305 100644 (file)
--- a/gas/testsuite/gas/aarch64/sysreg.d
+++ b/gas/testsuite/gas/aarch64/sysreg.d
@@ -27,5 +27,5 @@ Disassembly of section \.text:
   4c:  d538cc00        mrs     x0, s3_0_c12_c12_0
   50:  d5384600        mrs     x0, s3_0_c4_c6_0
   54:  d5184600        msr     s3_0_c4_c6_0, x0
-  58:  d5310300        mrs     x0, s2_1_c0_c3_0
-  5c:  d5110300        msr     s2_1_c0_c3_0, x0
+  58:  d5310300        mrs     x0, trcstatr
+  5c:  d5110300        msr     trcstatr, x0

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e9dfb78faad4022721fec2e8522943e5a7ee05fb..c57c0b1e209f0105b4de62e25c644cef821b888a 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,11 +1,28 @@
 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 
-        * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
+       * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
+       TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
+       TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
+       TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
+       TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
+       TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
+       TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
+       TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
+       WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
+       TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
+       TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
+       TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR,  TRCTSCTLR, TRCVDARCCTLR,
+       TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
+       TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
 
 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 
-        * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
-        TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
+       * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
+
+2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
+       TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
 
 2020-09-26  Alan Modra  <amodra@gmail.com>
 

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 83afb1f9778ab7cff8f2105c95999e83847f89d7..5c8d8ec6443fe9bfec81ea25a84735c4ba3a5d3a 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4325,6 +4325,222 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   SR_CORE ("trcextinselr3",    CPENC (2,1,C0,C11,4),   0),
   SR_CORE ("trcrsr",           CPENC (2,1,C0,C10,0),   0),
 
+  SR_CORE ("trcauthstatus", CPENC (2,1,C7,C14,6), F_REG_READ),
+  SR_CORE ("trccidr0",      CPENC (2,1,C7,C12,7), F_REG_READ),
+  SR_CORE ("trccidr1",      CPENC (2,1,C7,C13,7), F_REG_READ),
+  SR_CORE ("trccidr2",      CPENC (2,1,C7,C14,7), F_REG_READ),
+  SR_CORE ("trccidr3",      CPENC (2,1,C7,C15,7), F_REG_READ),
+  SR_CORE ("trcdevaff0",    CPENC (2,1,C7,C10,6), F_REG_READ),
+  SR_CORE ("trcdevaff1",    CPENC (2,1,C7,C11,6), F_REG_READ),
+  SR_CORE ("trcdevarch",    CPENC (2,1,C7,C15,6), F_REG_READ),
+  SR_CORE ("trcdevid",      CPENC (2,1,C7,C2,7),  F_REG_READ),
+  SR_CORE ("trcdevtype",    CPENC (2,1,C7,C3,7),  F_REG_READ),
+  SR_CORE ("trcidr0",       CPENC (2,1,C0,C8,7),  F_REG_READ),
+  SR_CORE ("trcidr1",       CPENC (2,1,C0,C9,7),  F_REG_READ),
+  SR_CORE ("trcidr2",       CPENC (2,1,C0,C10,7), F_REG_READ),
+  SR_CORE ("trcidr3",       CPENC (2,1,C0,C11,7), F_REG_READ),
+  SR_CORE ("trcidr4",       CPENC (2,1,C0,C12,7), F_REG_READ),
+  SR_CORE ("trcidr5",       CPENC (2,1,C0,C13,7), F_REG_READ),
+  SR_CORE ("trcidr6",       CPENC (2,1,C0,C14,7), F_REG_READ),
+  SR_CORE ("trcidr7",       CPENC (2,1,C0,C15,7), F_REG_READ),
+  SR_CORE ("trcidr8",       CPENC (2,1,C0,C0,6),  F_REG_READ),
+  SR_CORE ("trcidr9",       CPENC (2,1,C0,C1,6),  F_REG_READ),
+  SR_CORE ("trcidr10",      CPENC (2,1,C0,C2,6),  F_REG_READ),
+  SR_CORE ("trcidr11",      CPENC (2,1,C0,C3,6),  F_REG_READ),
+  SR_CORE ("trcidr12",      CPENC (2,1,C0,C4,6),  F_REG_READ),
+  SR_CORE ("trcidr13",      CPENC (2,1,C0,C5,6),  F_REG_READ),
+  SR_CORE ("trclsr",        CPENC (2,1,C7,C13,6), F_REG_READ),
+  SR_CORE ("trcoslsr",      CPENC (2,1,C1,C1,4),  F_REG_READ),
+  SR_CORE ("trcpdsr",       CPENC (2,1,C1,C5,4),  F_REG_READ),
+  SR_CORE ("trcpidr0",      CPENC (2,1,C7,C8,7),  F_REG_READ),
+  SR_CORE ("trcpidr1",      CPENC (2,1,C7,C9,7),  F_REG_READ),
+  SR_CORE ("trcpidr2",      CPENC (2,1,C7,C10,7), F_REG_READ),
+  SR_CORE ("trcpidr3",      CPENC (2,1,C7,C11,7), F_REG_READ),
+  SR_CORE ("trcpidr4",      CPENC (2,1,C7,C4,7),  F_REG_READ),
+  SR_CORE ("trcpidr5",      CPENC (2,1,C7,C5,7),  F_REG_READ),
+  SR_CORE ("trcpidr6",      CPENC (2,1,C7,C6,7),  F_REG_READ),
+  SR_CORE ("trcpidr7",      CPENC (2,1,C7,C7,7),  F_REG_READ),
+  SR_CORE ("trcstatr",      CPENC (2,1,C0,C3,0),  F_REG_READ),
+  SR_CORE ("trcacatr0",     CPENC (2,1,C2,C0,2),  0),
+  SR_CORE ("trcacatr1",     CPENC (2,1,C2,C2,2),  0),
+  SR_CORE ("trcacatr2",     CPENC (2,1,C2,C4,2),  0),
+  SR_CORE ("trcacatr3",     CPENC (2,1,C2,C6,2),  0),
+  SR_CORE ("trcacatr4",     CPENC (2,1,C2,C8,2),  0),
+  SR_CORE ("trcacatr5",     CPENC (2,1,C2,C10,2), 0),
+  SR_CORE ("trcacatr6",     CPENC (2,1,C2,C12,2), 0),
+  SR_CORE ("trcacatr7",     CPENC (2,1,C2,C14,2), 0),
+  SR_CORE ("trcacatr8",     CPENC (2,1,C2,C0,3),  0),
+  SR_CORE ("trcacatr9",     CPENC (2,1,C2,C2,3),  0),
+  SR_CORE ("trcacatr10",    CPENC (2,1,C2,C4,3),  0),
+  SR_CORE ("trcacatr11",    CPENC (2,1,C2,C6,3),  0),
+  SR_CORE ("trcacatr12",    CPENC (2,1,C2,C8,3),  0),
+  SR_CORE ("trcacatr13",    CPENC (2,1,C2,C10,3), 0),
+  SR_CORE ("trcacatr14",    CPENC (2,1,C2,C12,3), 0),
+  SR_CORE ("trcacatr15",    CPENC (2,1,C2,C14,3), 0),
+  SR_CORE ("trcacvr0",      CPENC (2,1,C2,C0,0),  0),
+  SR_CORE ("trcacvr1",      CPENC (2,1,C2,C2,0),  0),
+  SR_CORE ("trcacvr2",      CPENC (2,1,C2,C4,0),  0),
+  SR_CORE ("trcacvr3",      CPENC (2,1,C2,C6,0),  0),
+  SR_CORE ("trcacvr4",      CPENC (2,1,C2,C8,0),  0),
+  SR_CORE ("trcacvr5",      CPENC (2,1,C2,C10,0), 0),
+  SR_CORE ("trcacvr6",      CPENC (2,1,C2,C12,0), 0),
+  SR_CORE ("trcacvr7",      CPENC (2,1,C2,C14,0), 0),
+  SR_CORE ("trcacvr8",      CPENC (2,1,C2,C0,1),  0),
+  SR_CORE ("trcacvr9",      CPENC (2,1,C2,C2,1),  0),
+  SR_CORE ("trcacvr10",     CPENC (2,1,C2,C4,1),  0),
+  SR_CORE ("trcacvr11",     CPENC (2,1,C2,C6,1),  0),
+  SR_CORE ("trcacvr12",     CPENC (2,1,C2,C8,1),  0),
+  SR_CORE ("trcacvr13",     CPENC (2,1,C2,C10,1), 0),
+  SR_CORE ("trcacvr14",     CPENC (2,1,C2,C12,1), 0),
+  SR_CORE ("trcacvr15",     CPENC (2,1,C2,C14,1), 0),
+  SR_CORE ("trcauxctlr",    CPENC (2,1,C0,C6,0),  0),
+  SR_CORE ("trcbbctlr",     CPENC (2,1,C0,C15,0), 0),
+  SR_CORE ("trcccctlr",     CPENC (2,1,C0,C14,0), 0),
+  SR_CORE ("trccidcctlr0",  CPENC (2,1,C3,C0,2),  0),
+  SR_CORE ("trccidcctlr1",  CPENC (2,1,C3,C1,2),  0),
+  SR_CORE ("trccidcvr0",    CPENC (2,1,C3,C0,0),  0),
+  SR_CORE ("trccidcvr1",    CPENC (2,1,C3,C2,0),  0),
+  SR_CORE ("trccidcvr2",    CPENC (2,1,C3,C4,0),  0),
+  SR_CORE ("trccidcvr3",    CPENC (2,1,C3,C6,0),  0),
+  SR_CORE ("trccidcvr4",    CPENC (2,1,C3,C8,0),  0),
+  SR_CORE ("trccidcvr5",    CPENC (2,1,C3,C10,0), 0),
+  SR_CORE ("trccidcvr6",    CPENC (2,1,C3,C12,0), 0),
+  SR_CORE ("trccidcvr7",    CPENC (2,1,C3,C14,0), 0),
+  SR_CORE ("trcclaimclr",   CPENC (2,1,C7,C9,6),  0),
+  SR_CORE ("trcclaimset",   CPENC (2,1,C7,C8,6),  0),
+  SR_CORE ("trccntctlr0",   CPENC (2,1,C0,C4,5),  0),
+  SR_CORE ("trccntctlr1",   CPENC (2,1,C0,C5,5),  0),
+  SR_CORE ("trccntctlr2",   CPENC (2,1,C0,C6,5),  0),
+  SR_CORE ("trccntctlr3",   CPENC (2,1,C0,C7,5),  0),
+  SR_CORE ("trccntrldvr0",  CPENC (2,1,C0,C0,5),  0),
+  SR_CORE ("trccntrldvr1",  CPENC (2,1,C0,C1,5),  0),
+  SR_CORE ("trccntrldvr2",  CPENC (2,1,C0,C2,5),  0),
+  SR_CORE ("trccntrldvr3",  CPENC (2,1,C0,C3,5),  0),
+  SR_CORE ("trccntvr0",     CPENC (2,1,C0,C8,5),  0),
+  SR_CORE ("trccntvr1",     CPENC (2,1,C0,C9,5),  0),
+  SR_CORE ("trccntvr2",     CPENC (2,1,C0,C10,5), 0),
+  SR_CORE ("trccntvr3",     CPENC (2,1,C0,C11,5), 0),
+  SR_CORE ("trcconfigr",    CPENC (2,1,C0,C4,0),  0),
+  SR_CORE ("trcdvcmr0",     CPENC (2,1,C2,C0,6),  0),
+  SR_CORE ("trcdvcmr1",     CPENC (2,1,C2,C4,6),  0),
+  SR_CORE ("trcdvcmr2",     CPENC (2,1,C2,C8,6),  0),
+  SR_CORE ("trcdvcmr3",     CPENC (2,1,C2,C12,6), 0),
+  SR_CORE ("trcdvcmr4",     CPENC (2,1,C2,C0,7),  0),
+  SR_CORE ("trcdvcmr5",     CPENC (2,1,C2,C4,7),  0),
+  SR_CORE ("trcdvcmr6",     CPENC (2,1,C2,C8,7),  0),
+  SR_CORE ("trcdvcmr7",     CPENC (2,1,C2,C12,7), 0),
+  SR_CORE ("trcdvcvr0",     CPENC (2,1,C2,C0,4),  0),
+  SR_CORE ("trcdvcvr1",     CPENC (2,1,C2,C4,4),  0),
+  SR_CORE ("trcdvcvr2",     CPENC (2,1,C2,C8,4),  0),
+  SR_CORE ("trcdvcvr3",     CPENC (2,1,C2,C12,4), 0),
+  SR_CORE ("trcdvcvr4",     CPENC (2,1,C2,C0,5),  0),
+  SR_CORE ("trcdvcvr5",     CPENC (2,1,C2,C4,5),  0),
+  SR_CORE ("trcdvcvr6",     CPENC (2,1,C2,C8,5),  0),
+  SR_CORE ("trcdvcvr7",     CPENC (2,1,C2,C12,5), 0),
+  SR_CORE ("trceventctl0r", CPENC (2,1,C0,C8,0),  0),
+  SR_CORE ("trceventctl1r", CPENC (2,1,C0,C9,0),  0),
+  SR_CORE ("trcextinselr0", CPENC (2,1,C0,C8,4),  0),
+  SR_CORE ("trcextinselr",  CPENC (2,1,C0,C8,4),  0),
+  SR_CORE ("trcextinselr1", CPENC (2,1,C0,C9,4),  0),
+  SR_CORE ("trcextinselr2", CPENC (2,1,C0,C10,4), 0),
+  SR_CORE ("trcextinselr3", CPENC (2,1,C0,C11,4), 0),
+  SR_CORE ("trcimspec0",    CPENC (2,1,C0,C0,7),  0),
+  SR_CORE ("trcimspec0",    CPENC (2,1,C0,C0,7),  0),
+  SR_CORE ("trcimspec1",    CPENC (2,1,C0,C1,7),  0),
+  SR_CORE ("trcimspec2",    CPENC (2,1,C0,C2,7),  0),
+  SR_CORE ("trcimspec3",    CPENC (2,1,C0,C3,7),  0),
+  SR_CORE ("trcimspec4",    CPENC (2,1,C0,C4,7),  0),
+  SR_CORE ("trcimspec5",    CPENC (2,1,C0,C5,7),  0),
+  SR_CORE ("trcimspec6",    CPENC (2,1,C0,C6,7),  0),
+  SR_CORE ("trcimspec7",    CPENC (2,1,C0,C7,7),  0),
+  SR_CORE ("trcitctrl",     CPENC (2,1,C7,C0,4),  0),
+  SR_CORE ("trcpdcr",       CPENC (2,1,C1,C4,4),  0),
+  SR_CORE ("trcprgctlr",    CPENC (2,1,C0,C1,0),  0),
+  SR_CORE ("trcprocselr",   CPENC (2,1,C0,C2,0),  0),
+  SR_CORE ("trcqctlr",      CPENC (2,1,C0,C1,1),  0),
+  SR_CORE ("trcrsctlr2",    CPENC (2,1,C1,C2,0),  0),
+  SR_CORE ("trcrsctlr3",    CPENC (2,1,C1,C3,0),  0),
+  SR_CORE ("trcrsctlr4",    CPENC (2,1,C1,C4,0),  0),
+  SR_CORE ("trcrsctlr5",    CPENC (2,1,C1,C5,0),  0),
+  SR_CORE ("trcrsctlr6",    CPENC (2,1,C1,C6,0),  0),
+  SR_CORE ("trcrsctlr7",    CPENC (2,1,C1,C7,0),  0),
+  SR_CORE ("trcrsctlr8",    CPENC (2,1,C1,C8,0),  0),
+  SR_CORE ("trcrsctlr9",    CPENC (2,1,C1,C9,0),  0),
+  SR_CORE ("trcrsctlr10",   CPENC (2,1,C1,C10,0), 0),
+  SR_CORE ("trcrsctlr11",   CPENC (2,1,C1,C11,0), 0),
+  SR_CORE ("trcrsctlr12",   CPENC (2,1,C1,C12,0), 0),
+  SR_CORE ("trcrsctlr13",   CPENC (2,1,C1,C13,0), 0),
+  SR_CORE ("trcrsctlr14",   CPENC (2,1,C1,C14,0), 0),
+  SR_CORE ("trcrsctlr15",   CPENC (2,1,C1,C15,0), 0),
+  SR_CORE ("trcrsctlr16",   CPENC (2,1,C1,C0,1),  0),
+  SR_CORE ("trcrsctlr17",   CPENC (2,1,C1,C1,1),  0),
+  SR_CORE ("trcrsctlr18",   CPENC (2,1,C1,C2,1),  0),
+  SR_CORE ("trcrsctlr19",   CPENC (2,1,C1,C3,1),  0),
+  SR_CORE ("trcrsctlr20",   CPENC (2,1,C1,C4,1),  0),
+  SR_CORE ("trcrsctlr21",   CPENC (2,1,C1,C5,1),  0),
+  SR_CORE ("trcrsctlr22",   CPENC (2,1,C1,C6,1),  0),
+  SR_CORE ("trcrsctlr23",   CPENC (2,1,C1,C7,1),  0),
+  SR_CORE ("trcrsctlr24",   CPENC (2,1,C1,C8,1),  0),
+  SR_CORE ("trcrsctlr25",   CPENC (2,1,C1,C9,1),  0),
+  SR_CORE ("trcrsctlr26",   CPENC (2,1,C1,C10,1), 0),
+  SR_CORE ("trcrsctlr27",   CPENC (2,1,C1,C11,1), 0),
+  SR_CORE ("trcrsctlr28",   CPENC (2,1,C1,C12,1), 0),
+  SR_CORE ("trcrsctlr29",   CPENC (2,1,C1,C13,1), 0),
+  SR_CORE ("trcrsctlr30",   CPENC (2,1,C1,C14,1), 0),
+  SR_CORE ("trcrsctlr31",   CPENC (2,1,C1,C15,1), 0),
+  SR_CORE ("trcseqevr0",    CPENC (2,1,C0,C0,4),  0),
+  SR_CORE ("trcseqevr1",    CPENC (2,1,C0,C1,4),  0),
+  SR_CORE ("trcseqevr2",    CPENC (2,1,C0,C2,4),  0),
+  SR_CORE ("trcseqrstevr",  CPENC (2,1,C0,C6,4),  0),
+  SR_CORE ("trcseqstr",     CPENC (2,1,C0,C7,4),  0),
+  SR_CORE ("trcssccr0",     CPENC (2,1,C1,C0,2),  0),
+  SR_CORE ("trcssccr1",     CPENC (2,1,C1,C1,2),  0),
+  SR_CORE ("trcssccr2",     CPENC (2,1,C1,C2,2),  0),
+  SR_CORE ("trcssccr3",     CPENC (2,1,C1,C3,2),  0),
+  SR_CORE ("trcssccr4",     CPENC (2,1,C1,C4,2),  0),
+  SR_CORE ("trcssccr5",     CPENC (2,1,C1,C5,2),  0),
+  SR_CORE ("trcssccr6",     CPENC (2,1,C1,C6,2),  0),
+  SR_CORE ("trcssccr7",     CPENC (2,1,C1,C7,2),  0),
+  SR_CORE ("trcsscsr0",     CPENC (2,1,C1,C8,2),  0),
+  SR_CORE ("trcsscsr1",     CPENC (2,1,C1,C9,2),  0),
+  SR_CORE ("trcsscsr2",     CPENC (2,1,C1,C10,2), 0),
+  SR_CORE ("trcsscsr3",     CPENC (2,1,C1,C11,2), 0),
+  SR_CORE ("trcsscsr4",     CPENC (2,1,C1,C12,2), 0),
+  SR_CORE ("trcsscsr5",     CPENC (2,1,C1,C13,2), 0),
+  SR_CORE ("trcsscsr6",     CPENC (2,1,C1,C14,2), 0),
+  SR_CORE ("trcsscsr7",     CPENC (2,1,C1,C15,2), 0),
+  SR_CORE ("trcsspcicr0",   CPENC (2,1,C1,C0,3),  0),
+  SR_CORE ("trcsspcicr1",   CPENC (2,1,C1,C1,3),  0),
+  SR_CORE ("trcsspcicr2",   CPENC (2,1,C1,C2,3),  0),
+  SR_CORE ("trcsspcicr3",   CPENC (2,1,C1,C3,3),  0),
+  SR_CORE ("trcsspcicr4",   CPENC (2,1,C1,C4,3),  0),
+  SR_CORE ("trcsspcicr5",   CPENC (2,1,C1,C5,3),  0),
+  SR_CORE ("trcsspcicr6",   CPENC (2,1,C1,C6,3),  0),
+  SR_CORE ("trcsspcicr7",   CPENC (2,1,C1,C7,3),  0),
+  SR_CORE ("trcstallctlr",  CPENC (2,1,C0,C11,0), 0),
+  SR_CORE ("trcsyncpr",     CPENC (2,1,C0,C13,0), 0),
+  SR_CORE ("trctraceidr",   CPENC (2,1,C0,C0,1),  0),
+  SR_CORE ("trctsctlr",     CPENC (2,1,C0,C12,0), 0),
+  SR_CORE ("trcvdarcctlr",  CPENC (2,1,C0,C10,2), 0),
+  SR_CORE ("trcvdctlr",     CPENC (2,1,C0,C8,2),  0),
+  SR_CORE ("trcvdsacctlr",  CPENC (2,1,C0,C9,2),  0),
+  SR_CORE ("trcvictlr",     CPENC (2,1,C0,C0,2),  0),
+  SR_CORE ("trcviiectlr",   CPENC (2,1,C0,C1,2),  0),
+  SR_CORE ("trcvipcssctlr", CPENC (2,1,C0,C3,2),  0),
+  SR_CORE ("trcvissctlr",   CPENC (2,1,C0,C2,2),  0),
+  SR_CORE ("trcvmidcctlr0", CPENC (2,1,C3,C2,2),  0),
+  SR_CORE ("trcvmidcctlr1", CPENC (2,1,C3,C3,2),  0),
+  SR_CORE ("trcvmidcvr0",   CPENC (2,1,C3,C0,1),  0),
+  SR_CORE ("trcvmidcvr1",   CPENC (2,1,C3,C2,1),  0),
+  SR_CORE ("trcvmidcvr2",   CPENC (2,1,C3,C4,1),  0),
+  SR_CORE ("trcvmidcvr3",   CPENC (2,1,C3,C6,1),  0),
+  SR_CORE ("trcvmidcvr4",   CPENC (2,1,C3,C8,1),  0),
+  SR_CORE ("trcvmidcvr5",   CPENC (2,1,C3,C10,1), 0),
+  SR_CORE ("trcvmidcvr6",   CPENC (2,1,C3,C12,1), 0),
+  SR_CORE ("trcvmidcvr7",   CPENC (2,1,C3,C14,1), 0),
+  SR_CORE ("trclar",        CPENC (2,1,C7,C12,6), F_REG_WRITE),
+  SR_CORE ("trcoslar",      CPENC (2,1,C1,C0,4),  F_REG_WRITE),
+
   { 0, CPENC (0,0,0,0,0), 0, 0 }
 };