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liteeth: Update yaml config
authorAnton Blanchard <anton@linux.ibm.com>
Mon, 9 Aug 2021 03:49:25 +0000 (13:49 +1000)
committerAnton Blanchard <anton@ozlabs.org>
Mon, 9 Aug 2021 11:21:08 +0000 (21:21 +1000)
csr_data_width is no longer required. Add ntxslots and nrxslots
parameters but set them to the default value.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
liteeth/gen-src/arty.yml patch | blob | history
liteeth/gen-src/nexys-video.yml patch | blob | history

diff --git a/liteeth/gen-src/arty.yml b/liteeth/gen-src/arty.yml
index 7200a70dc5b6c3b87e85d9ae9ae0a8b8e65c8e0c..d092c0abb73558f6712cc722caf54f427a3f73aa 100644 (file)
--- a/liteeth/gen-src/arty.yml
+++ b/liteeth/gen-src/arty.yml
@@ -8,8 +8,9 @@ vendor:     xilinx
 clk_freq:   100e6
 core:       wishbone
 endianness: little
+ntxslots:   2
+nrxslots:   2
 
 soc:
     mem_map:
         ethmac: 0x00010000
-    csr_data_width: 32
diff --git a/liteeth/gen-src/nexys-video.yml b/liteeth/gen-src/nexys-video.yml
index 38a207c893f89b96fb3d38cbb203f69f7575ee3a..d7253ea13da995d76c472fba5c27120c3a149289 100644 (file)
--- a/liteeth/gen-src/nexys-video.yml
+++ b/liteeth/gen-src/nexys-video.yml
@@ -8,8 +8,9 @@ vendor:     xilinx
 clk_freq:   125e6
 core:       wishbone
 endianness: little
+ntxslots:   2
+nrxslots:   2
 
 soc:
     mem_map:
         ethmac: 0x00010000
-    csr_data_width: 32