add explanation of areas

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index c0240d57cd14305b563d44a5a1e6bc2bca1fbdbf..ed5c6725ab9ea9802e51700adc40050806557412 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -302,8 +302,6 @@ Scheme.
 | PO  | 0 | 1 | nnnn  | new-suffix, vector (SVP64)       |
 | PO  | 1 | 1 | nnnn  | old-suffix, vector (SVP64)       |
 
-The above table requires some explanation, with some definitions.
-
 * **PO** - Primary Opcode. Likely candidates: EXT022, EXT005, EXT009
 * **bit 6** - specifies whether the suffix is old (EXT000-EXT063)
   or new (EXTn00-EXTn63, n greater than 1)
@@ -340,6 +338,41 @@ The opportunity to create two new 32-bit encoding spaces each with
 |new bit6=0| `RESERVED1`:{EXT200-063}  | SVP64-Single:{EXT200-263} | SVP64:{EXT200-263} |
 |old bit6=1| `RESERVED2`:{EXT300-363}  | SVP64-Single:{EXT000-063}   | SVP64:{EXT000-063}   |
 
+* **`RESERVED2`:{EXT300-363}** is not and **cannot** ever be Vectorised or
+  Augmented by Simple-V or any future Simple-V Scheme.
+  it is a pure **Scalar-only** new set of 64 Major Opcodes
+* **`RESERVED1`:{EXT200-263}** is also a Scalar-only new set of 64 Major
+  Opcodes.
+  These opcodes do not *need* to be Simple-V-Augmented
+  *but the option to do so exists* should an Implementor choose to do so.
+  This is unlike `EXT300-363` which may **never** be Simple-V-Augmented
+  under any cirmstances.
+* **`SVP64-Single:{EXT200-263}`** - Major opcodes 200-263 with
+  Single-Augmentation, providing a one-bit predicate mask, element-width
+  overrides on source and destination, and the option to extend the Scalar
+  Register numbering (r0-32 extends to r0-127).  **Placing of alternative
+  instruction encodings other than those exactly defined in EXT200-263
+  is prohibited**.
+* **`SVP64-Single:{EXT000-063}`** - Major opcodes 000-063 with
+  Single-Augmentation, just like SVP64-Single on EXT200-263, these are
+  in effect Single-Augmented-Prefixed variants of the v3.0 32-bit Power ISA.
+  Alternative instruction encodings other than the exact same 32-bit word
+  from EXT000-EXT063 are likewise prohibited.
+* **`SVP64:{EXT000-063}`** and **`SVP64:{EXT200-263}`** - Full Vectorisation
+  of EXT000-063 and EXT200-263 respectively, these Prefixed instructions
+  are likewise prohibited from being a different encoding from their
+  32-bit scalar versions.
+
+Limitations of this scheme is that 32-bit Scalar operations have to have
+a 32-bit "escape-sequence" in front of them. If commonly-used this could
+increase binary size. Thus the Encodings EXT300-363 and EXT200-263 should
+only be allocated for less-popular operations.  However the scheme does
+have the strong advantage of *tripling* the available number of Major
+Opcodes in the Power ISA, caveat being that care on allocation is needed
+because EXT200-EXT263 may be SVP64-Augmented whilst EXT300-EXT363 may **not**.
+The issues of allocation for bitmanip etc. from Libre-SOC is therefore
+overwhelmingly made moot.
+
 \newpage{}
 # Use cases