trySendTimingReq();
}
-RequestPtr
+void
DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay,
Request::Flags flag)
// i.e. cache line size
DmaReqState *reqState = new DmaReqState(event, size, delay);
- // (functionality added for Table Walker statistics)
- // We're only interested in this when there will only be one request.
- // For simplicity, we return the last request, which would also be
- // the only request in that case.
RequestPtr req = nullptr;
DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
// just created, for atomic this involves actually completing all
// the requests
sendDma();
-
- return req;
}
-RequestPtr
+void
DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
uint8_t *data, Tick delay, Request::Flags flag)
{
- return dmaAction(cmd, addr, size, event, data,
- defaultSid, defaultSSid, delay, flag);
+ dmaAction(cmd, addr, size, event, data,
+ defaultSid, defaultSSid, delay, flag);
}
void
DmaPort(ClockedObject *dev, System *s, uint32_t sid=0, uint32_t ssid=0);
- RequestPtr
+ void
dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
uint8_t *data, Tick delay, Request::Flags flag=0);
- RequestPtr
+ void
dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay,
Request::Flags flag=0);