dvisampler: add resolution detection

diff --git a/milkymist/dvisampler/__init__.py b/milkymist/dvisampler/__init__.py
index c752b1c28eea293129706a21cb67bbcb2a3e0dd1..c508b9650d033a386e486222ac5c78139092fa08 100644 (file)
--- a/milkymist/dvisampler/__init__.py
+++ b/milkymist/dvisampler/__init__.py
@@ -8,6 +8,7 @@ from milkymist.dvisampler.datacapture import DataCapture
 from milkymist.dvisampler.charsync import CharSync
 from milkymist.dvisampler.decoding import Decoding
 from milkymist.dvisampler.chansync import ChanSync
+from milkymist.dvisampler.resdetection import ResolutionDetection
 
 class DVISampler(Module, AutoReg):
        def __init__(self, inversions=""):
@@ -59,3 +60,10 @@ class DVISampler(Module, AutoReg):
                b = self.chansync.data_out0.d
                hsync = self.chansync.data_out0.c[0]
                vsync = self.chansync.data_out0.c[1]
+
+               self.submodules.resdetection = ResolutionDetection()
+               self.comb += [
+                       self.resdetection.de.eq(de),
+                       self.resdetection.hsync.eq(hsync),
+                       self.resdetection.vsync.eq(vsync)
+               ]

diff --git a/milkymist/dvisampler/resdetection.py b/milkymist/dvisampler/resdetection.py
new file mode 100644 (file)
index 0000000..20f7453
--- /dev/null
+++ b/milkymist/dvisampler/resdetection.py
@@ -0,0 +1,71 @@
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
+from migen.genlib.cdc import MultiReg
+from migen.bank.description import *
+
+class ResolutionDetection(Module, AutoReg):
+       def __init__(self, nbits=10):
+               self.hsync = Signal()
+               self.vsync = Signal()
+               self.de = Signal()
+
+               self._hres = RegisterField(nbits, READ_ONLY, WRITE_ONLY)
+               self._vres = RegisterField(nbits, READ_ONLY, WRITE_ONLY)
+               self._de_cycles = RegisterField(2*nbits, READ_ONLY, WRITE_ONLY)
+
+               ###
+
+               # HRES/VRES
+               hsync_r = Signal()
+               vsync_r = Signal()
+               p_hsync = Signal()
+               p_vsync = Signal()
+               self.sync.pix += [
+                       hsync_r.eq(self.hsync),
+                       vsync_r.eq(self.vsync),
+               ]
+               self.comb += [
+                       p_hsync.eq(self.hsync & ~hsync_r),
+                       p_vsync.eq(self.vsync & ~vsync_r)
+               ]
+
+               hcounter = Signal(nbits)
+               vcounter = Signal(nbits)
+               self.sync.pix += [
+                       If(p_hsync,
+                               hcounter.eq(0)
+                       ).Elif(self.de,
+                               hcounter.eq(hcounter + 1)
+                       ),
+                       If(p_vsync,
+                               vcounter.eq(0)
+                       ).Elif(p_hsync,
+                               vcounter.eq(vcounter + 1)
+                       )
+               ]
+
+               hcounter_st = Signal(nbits)
+               vcounter_st = Signal(nbits)
+               self.sync.pix += [
+                       If(p_hsync & (hcounter != 0), hcounter_st.eq(hcounter)),
+                       If(p_vsync & (vcounter != 0), vcounter_st.eq(vcounter))
+               ]
+               self.specials += MultiReg(hcounter_st, self._hres.field.w)
+               self.specials += MultiReg(vcounter_st, self._vres.field.w)
+
+               # DE
+               de_r = Signal()
+               pn_de = Signal()
+               self.sync.pix += de_r.eq(self.de)
+               self.comb += pn_de.eq(~self.de & de_r)
+
+               decounter = Signal(2*nbits)
+               self.sync.pix += If(self.de,
+                               decounter.eq(decounter + 1)
+                       ).Else(
+                               decounter.eq(0)
+                       )
+
+               decounter_st = Signal(2*nbits)
+               self.sync.pix += If(pn_de, decounter_st.eq(decounter))
+               self.specials += MultiReg(decounter_st, self._de_cycles.field.w)