Fixed parsing of verilog macros at end of line

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 5cfa0f24b2e22912aec83ec077a44b37677249a9..db53e8c68eea130d63ee6b56f6f83249651208ba 100644 (file)
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -386,7 +386,7 @@ std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::m
                        std::string name = tok.substr(1);
                        // printf("expand: >>%s<< -> >>%s<<\n", name.c_str(), defines_map[name].c_str());
                        std::string skipped_spaces = skip_spaces();
-                       tok = next_token(true);
+                       tok = next_token(false);
                        if (tok == "(" && defines_with_args.count(name) > 0) {
                                int level = 1;
                                std::vector<std::string> args;