mem-ruby: add cache hit/miss statistics for TCP and TCC

Change-Id: Ifa6fdbb9dd062a3684b9620eac6683c57e651a72
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30174
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>

diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
index 5f05a605bcf66e5976749c08e634092889065669..c4c4c3e06eee062a9320822b73d72d94d84b127f 100644 (file)
--- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
@@ -438,6 +438,14 @@ machine(MachineType:TCC, "TCC Cache")
     }
   }
 
+  action(p_profileMiss, "pm", desc="Profile cache miss") {
+      ++L2cache.demand_misses;
+  }
+
+  action(p_profileHit, "ph", desc="Profile cache hit") {
+      ++L2cache.demand_hits;
+  }
+
   action(t_allocateTBE, "t", desc="allocate TBE Entry") {
     if (is_invalid(tbe)) {
       check_allocate(TBEs);
@@ -596,28 +604,42 @@ machine(MachineType:TCC, "TCC Cache")
       z_stall;
   }
   transition({M, V}, RdBlk) {TagArrayRead, DataArrayRead} {
+    p_profileHit;
     sd_sendData;
     ut_updateTag;
     p_popRequestQueue;
   }
   transition(W, RdBlk, WI) {TagArrayRead, DataArrayRead} {
+    p_profileHit;
     t_allocateTBE;
     wb_writeBack;
   }
 
   transition(I, RdBlk, IV) {TagArrayRead} {
+    p_profileMiss;
     t_allocateTBE;
     rd_requestData;
     p_popRequestQueue;
   }
 
   transition(IV, RdBlk) {
+    p_profileMiss;
     t_allocateTBE;
     rd_requestData;
     p_popRequestQueue;
   }
 
-  transition({V, I},Atomic, A) {TagArrayRead} {
+  transition(V, Atomic, A) {TagArrayRead} {
+    p_profileHit;
+    i_invL2;
+    t_allocateTBE;
+    at_atomicThrough;
+    ina_incrementNumAtomics;
+    p_popRequestQueue;
+  }
+
+transition(I, Atomic, A) {TagArrayRead} {
+    p_profileMiss;
     i_invL2;
     t_allocateTBE;
     at_atomicThrough;
@@ -626,22 +648,26 @@ machine(MachineType:TCC, "TCC Cache")
   }
 
   transition(A, Atomic) {
+    p_profileMiss;
     at_atomicThrough;
     ina_incrementNumAtomics;
     p_popRequestQueue;
   }
 
   transition({M, W}, Atomic, WI) {TagArrayRead} {
+    p_profileHit;
     t_allocateTBE;
     wb_writeBack;
   }
 
   transition(I, WrVicBlk) {TagArrayRead} {
+    p_profileMiss;
     wt_writeThrough;
     p_popRequestQueue;
   }
 
   transition(V, WrVicBlk) {TagArrayRead, DataArrayWrite} {
+    p_profileHit;
     ut_updateTag;
     wdb_writeDirtyBytes;
     wt_writeThrough;
@@ -649,6 +675,7 @@ machine(MachineType:TCC, "TCC Cache")
   }
 
   transition({V, M}, WrVicBlkBack, M) {TagArrayRead, TagArrayWrite, DataArrayWrite} {
+    p_profileHit;
     ut_updateTag;
     swb_sendWBAck;
     wdb_writeDirtyBytes;
@@ -656,6 +683,7 @@ machine(MachineType:TCC, "TCC Cache")
   }
 
   transition(W, WrVicBlkBack) {TagArrayRead, TagArrayWrite, DataArrayWrite} {
+    p_profileHit;
     ut_updateTag;
     swb_sendWBAck;
     wdb_writeDirtyBytes;
@@ -663,6 +691,7 @@ machine(MachineType:TCC, "TCC Cache")
   }
 
   transition(I, WrVicBlkBack, W) {TagArrayRead, TagArrayWrite, DataArrayWrite} {
+    p_profileMiss;
     a_allocateBlock;
     ut_updateTag;
     swb_sendWBAck;

diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
index 3f617915907cdbe682b82fd1c78185ffc19cc54a..aafe5a4118d62e4c217695246d35ce8d8d81cf2a 100644 (file)
--- a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
@@ -527,6 +527,16 @@ machine(MachineType:TCP, "GPU TCP (L1 Data Cache)")
       // built-int action
   }
 
+  // added for profiling
+  action(uu_profileDataMiss, "\udm", desc="Profile the demand miss"){
+      ++L1cache.demand_misses;
+  }
+
+  action(uu_profileDataHit, "\udh", desc="Profile the demand hit"){
+      ++L1cache.demand_hits;
+  }
+
+
   // Transitions
   // ArrayRead/Write assumptions:
   // All requests read Tag Array
@@ -544,12 +554,14 @@ machine(MachineType:TCP, "GPU TCP (L1 Data Cache)")
 
   transition(I, Load) {TagArrayRead} {
     n_issueRdBlk;
+    uu_profileDataMiss;
     p_popMandatoryQueue;
   }
 
   transition(V, Load) {TagArrayRead, DataArrayRead} {
     l_loadDone;
     mru_updateMRU;
+    uu_profileDataHit;
     p_popMandatoryQueue;
   }
 
@@ -564,6 +576,7 @@ machine(MachineType:TCP, "GPU TCP (L1 Data Cache)")
     a_allocate;
     dw_dirtyWrite;
     s_storeDone;
+    uu_profileDataMiss;
     wt_writeThrough;
     ic_invCache;
     p_popMandatoryQueue;
@@ -572,6 +585,7 @@ machine(MachineType:TCP, "GPU TCP (L1 Data Cache)")
   transition(V, StoreThrough, I) {TagArrayRead, TagArrayWrite, DataArrayWrite} {
     dw_dirtyWrite;
     s_storeDone;
+    uu_profileDataHit;
     wt_writeThrough;
     ic_invCache;
     p_popMandatoryQueue;