ARM: Decode the swp and swpb instructions.

diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
index f1fb57fc17401c66a766e2865af73de080bee364..d739395a1b768819fb019d15dbed5639faf0a918 100644 (file)
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -58,12 +58,7 @@ format DataOp {
         1: decode MISC_OPCODE {
             0x9: decode PREPOST {
                 0: ArmMultAndMultAcc::armMultAndMultAcc();
-                1: decode PUBWL {
-                    0x10: WarnUnimpl::swp();
-                    0x14: WarnUnimpl::swpb();
-                    0x18: WarnUnimpl::strex();
-                    0x19: WarnUnimpl::ldrex();
-                }
+                1: ArmSyncMem::armSyncMem();
             }
             0xb, 0xd, 0xf: AddrMode3::addrMode3();
         }

diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index 13309ec9bdeddcd34a2cb40e7590042022c3cd24..2ea45733bdddc4031e173f5d544264599504ede7 100644 (file)
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -213,6 +213,28 @@ def format AddrMode3() {{
     decode_block = decode % subs
 }};
 
+def format ArmSyncMem() {{
+    decode_block = '''
+    {
+        const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
+        const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+        const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+        switch (PUBWL) {
+          case 0x10:
+            return new Swp(machInst, rt, rt2, rn);
+          case 0x14:
+            return new Swpb(machInst, rt, rt2, rn);
+          case 0x18:
+            return new WarnUnimplemented("strex", machInst);
+          case 0x19:
+            return new WarnUnimplemented("ldrex", machInst);
+          default:
+            return new Unknown(machInst);
+        }
+    }
+    '''
+}};
+
 def format Thumb32LoadWord() {{
     decode = '''
     {