parser.add_option("--output", default="", help="Redirect stdout to a file.")
parser.add_option("--errout", default="", help="Redirect stderr to a file.")
+# cache parameters
+parser.add_option("--l1d_size", type="string", default="32kB")
+parser.add_option("--l1i_size", type="string", default="32kB")
+parser.add_option("--l2_size", type="string", default="1MB")
+parser.add_option("--l1d_assoc", type="int", default=2)
+parser.add_option("--l1i_assoc", type="int", default=2)
+parser.add_option("--l2_assoc", type="int", default=16)
+
# ruby host memory experimentation
-parser.add_option("--cache_size", type="int")
-parser.add_option("--cache_assoc", type="int")
parser.add_option("--map_levels", type="int")
execfile(os.path.join(config_root, "common", "Options.py"))
# Note: the L1 Cache latency is only used by the sequencer on fast path hits
#
class L1Cache(RubyCache):
- assoc = 2
latency = 3
- size = 32768
#
# Note: the L2 Cache latency is not currently used
#
class L2Cache(RubyCache):
- assoc = 16
latency = 15
- size = 1048576
def create_system(options, phys_mem, piobus, dma_devices):
#
# First create the Ruby objects associated with this cpu
#
- l1i_cache = L1Cache()
- l1d_cache = L1Cache()
- l2_cache = L2Cache()
+ l1i_cache = L1Cache(size = options.l1i_size,
+ assoc = options.l1i_assoc)
+ l1d_cache = L1Cache(size = options.l1d_size,
+ assoc = options.l1d_assoc)
+ l2_cache = L2Cache(size = options.l2_size,
+ assoc = options.l2_assoc)
cpu_seq = RubySequencer(icache = l1i_cache,
dcache = l1d_cache,
#
network = SimpleNetwork(topology = makeCrossbar(all_cntrls))
- mem_size_mb = sum([int(dir_cntrl.directory.size_mb) \
- for dir_cntrl in dir_cntrls])
+ #
+ # determine the total memory size of the ruby system
+ #
+ total_mem_size = MemorySize('0B')
+ for dir_cntrl in dir_cntrls:
+ total_mem_size.value += dir_cntrl.directory.size.value
ruby_profiler = RubyProfiler(num_of_sequencers = len(cpu_sequencers))
debug = RubyDebug(filter_string = 'none',
verbosity_string = 'none',
protocol_trace = False),
- mem_size_mb = mem_size_mb)
+ mem_size = total_mem_size)
ruby.cpu_ruby_ports = cpu_sequencers
class RubyCache(SimObject):
type = 'RubyCache'
cxx_class = 'CacheMemory'
- size = Param.Int("");
+ size = Param.MemorySize("capacity in bytes");
latency = Param.Int("");
assoc = Param.Int("");
replacement_policy = Param.String("PSEUDO_LRU", "");
: SimObject(p)
{
m_version = p->version;
- m_size_bytes = p->size_mb * static_cast<uint64>(1<<20);
+ m_size_bytes = p->size;
m_size_bits = log_int(m_size_bytes);
}
type = 'RubyDirectoryMemory'
cxx_class = 'DirectoryMemory'
version = Param.Int(0, "")
- size_mb = Param.Int(1024, "")
+ size = Param.MemorySize("1GB", "capacity in bytes")
clock = Param.Clock('1GHz', "")
block_size_bytes = Param.Int(64,
"default cache block size; must be a power of two");
- mem_size_mb = Param.Int("");
+ mem_size = Param.MemorySize("total memory size of the system");
network = Param.RubyNetwork("")
debug = Param.RubyDebug("the default debug object")
profiler = Param.RubyProfiler("");
assert(is_power_of_2(m_block_size_bytes));
m_block_size_bits = log_int(m_block_size_bytes);
- m_memory_size_bytes = (uint64_t)p->mem_size_mb * 1024 * 1024;
+ m_memory_size_bytes = p->mem_size;
m_memory_size_bits = log_int(m_memory_size_bytes);
m_network_ptr = p->network;