Merge zizzer.eecs.umich.edu:/bk/newmem

into  ewok.(none):/home/gblack/m5/newmemo3

src/sim/byteswap.hh:
    Hand Merge

--HG--
extra : convert_revision : 640d33ad0c416934e8a5107768e7f1dce6709ca8

diff --cc src/arch/sparc/faults.cc
Simple merge

diff --cc src/arch/sparc/intregfile.cc
Simple merge

diff --cc src/arch/sparc/isa/decoder.isa
index 8abaf10077a62aea093621133e31c14f25a34d4e,175866eba50099e826d734fc2be122c0aa45b05c..e59ce9d1148701fd41d50632315166e23bac8e01
--- 1/src/arch/sparc/isa/decoder.isa
--- 2/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@@ -891,16 -893,15 +891,16 @@@ decode OP default Unknown::unknown(
                      if(Canrestore == 0)
                      {
                          if(Otherwin)
-                             fault = new FillNOther(Wstate<5:3>);
+                             fault = new FillNOther(4*Wstate<5:3>);
                          else
-                             fault = new FillNNormal(Wstate<2:0>);
+                             fault = new FillNNormal(4*Wstate<2:0>);
                      }
 +                    //Check for alignment faults
 +                    else if(target & 0x3)
 +                        fault = new MemAddressNotAligned;
                      else
                      {
 -                        //CWP should be set directly so that it always happens
 -                        //Also, this will allow writing to the new window and
 -                        //reading from the old one
 +                        NNPC = target;
                          Cwp = (Cwp - 1 + NWindows) % NWindows;
                          Cansave = Cansave + 1;
                          Canrestore = Canrestore - 1;
@@@ -941,9 -946,13 +941,9 @@@
                  if(Cansave == 0)
                  {
                      if(Otherwin)
-                         fault = new SpillNOther(Wstate<5:3>);
+                         fault = new SpillNOther(4*Wstate<5:3>);
                      else
-                         fault = new SpillNNormal(Wstate<2:0>);
+                         fault = new SpillNNormal(4*Wstate<2:0>);
 -                    //Cwp = (Cwp + 2) % NWindows;
                  }
                  else if(Cleanwin - Canrestore == 0)
                  {

diff --cc src/arch/sparc/isa/formats/mem/blockmem.isa
index 62ac4b43adcc46b7f173b736bde78d9e2156e2cb,32421a75f29b2366299205d66355b6bbb0a4c8cc..352e963b3387ff8a06ef9278c0fff6198bfca630
--- 1/src/arch/sparc/isa/formats/mem/blockmem.isa
--- 2/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@@ -492,16 -494,16 +494,16 @@@ let {
                  flag_code = "flags[IsLastMicroOp] = true;"
                  pcedCode = matcher.sub("RdHigh", code)
              else:
-                 flag_code = "flags[IsDelayedCommit] = true;"
+                 flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;"
                  pcedCode = matcher.sub("RdLow", code)
 -            iop = InstObjParams(name, Name, 'TwinMem', pcedCode,
 -                    opt_flags, {"ea_code": addrCalcReg,
 +            iop = InstObjParams(name, Name, 'TwinMem',
 +                    {"code": pcedCode, "ea_code": addrCalcReg,
                      "fault_check": faultCode, "micro_pc": microPc,
 -                    "set_flags": flag_code})
 -            iop_imm = InstObjParams(name, Name + 'Imm', 'TwinMemImm', pcedCode,
 -                    opt_flags, {"ea_code": addrCalcImm,
 +                    "set_flags": flag_code}, opt_flags)
 +            iop_imm = InstObjParams(name, Name + 'Imm', 'TwinMemImm',
 +                    {"code": pcedCode, "ea_code": addrCalcImm,
                      "fault_check": faultCode, "micro_pc": microPc,
 -                    "set_flags": flag_code})
 +                    "set_flags": flag_code}, opt_flags)
              decoder_output += BlockMemMicroConstructor.subst(iop)
              decoder_output += BlockMemMicroConstructor.subst(iop_imm)
              exec_output += doDualSplitExecute(

diff --cc src/arch/sparc/isa_traits.hh
Simple merge

diff --cc src/arch/sparc/miscregfile.cc
Simple merge

diff --cc src/arch/sparc/miscregfile.hh
Simple merge

diff --cc src/arch/sparc/regfile.cc
Simple merge

diff --cc src/cpu/exetrace.cc
Simple merge

diff --cc src/sim/byteswap.hh
index 7b63cf6e0c09b4f5dff21e391b65b0f1b08f58ec,4ac1ee711c48e393379921642ae5dc1a0cbd6eb2..9e7390977e533ffc3efaea4ca7a064e01b6762fb
--- 1/src/sim/byteswap.hh
--- 2/src/sim/byteswap.hh
+++ b/src/sim/byteswap.hh
@@@ -132,8 -130,7 +132,8 @@@ template <typename T> static inline T l
  
  //For conversions not involving the guest system, we can define the functions
  //conditionally based on the BYTE_ORDER macro and outside of the namespaces
- #if defined(_BIG_ENDIAN) || BYTE_ORDER == BIG_ENDIAN
+ #if defined(_BIG_ENDIAN) || !defined(_LITTLE_ENDIAN) && BYTE_ORDER == BIG_ENDIAN
 +const ByteOrder HostByteOrder = BigEndianByteOrder;
  template <typename T> static inline T htole(T value) {return swap_byte(value);}
  template <typename T> static inline T letoh(T value) {return swap_byte(value);}
  template <typename T> static inline T htobe(T value) {return value;}

diff --cc src/sim/process.cc
Simple merge