bank: support raw registers

diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py
index e6d0f43b172f25dd236cce90173d02d3bb21bca8..acd0d7dc9c518c246158f01fe23058a6498e89b1 100644 (file)
--- a/migen/bank/csrgen.py
+++ b/migen/bank/csrgen.py
@@ -22,14 +22,20 @@ class Bank:
                bwcases = []
                for i in range(nregs):
                        reg = self.description[i]
-                       nfields = len(reg.fields)
-                       bwra = [Constant(i, BV(nbits))]
-                       for j in range(nfields):
-                               field = reg.fields[j]
-                               if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
-                                       bwra.append(field.storage.eq(self.interface.d_i[j]))
-                       if len(bwra) > 1:
-                               bwcases.append(bwra)
+                       if reg.raw is None:
+                               bwra = [Constant(i, BV(nbits))]
+                               nfields = len(reg.fields)
+                               for j in range(nfields):
+                                       field = reg.fields[j]
+                                       if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
+                                               bwra.append(field.storage.eq(self.interface.d_i[j]))
+                               if len(bwra) > 1:
+                                       bwcases.append(bwra)
+                       else:
+                               comb.append(reg.dev_r.eq(self.interface.d_i[:reg.raw.width]))
+                               comb.append(reg.dev_re.eq(self._sel & \
+                                       self.interface.we_i & \
+                                       (self.interface.a_i[:nbits] == Constant(i, BV(nbits)))))
                if bwcases:
                        sync.append(If(self._sel & self.interface.we_i, Case(self.interface.a_i[:nbits], *bwcases)))
                
@@ -37,21 +43,24 @@ class Bank:
                brcases = []
                for i in range(nregs):
                        reg = self.description[i]
-                       nfields = len(reg.fields)
-                       brs = []
-                       reg_readable = False
-                       for j in range(nfields):
-                               field = reg.fields[j]
-                               if field.access_bus == READ_ONLY or field.access_bus == READ_WRITE:
-                                       brs.append(field.storage)
-                                       reg_readable = True
-                               else:
-                                       brs.append(Constant(0, BV(field.size)))
-                       if reg_readable:
-                               if len(brs) > 1:
-                                       brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(f.Cat(*brs))])
-                               else:
-                                       brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(brs[0])])
+                       if reg.raw is None:
+                               nfields = len(reg.fields)
+                               brs = []
+                               reg_readable = False
+                               for j in range(nfields):
+                                       field = reg.fields[j]
+                                       if field.access_bus == READ_ONLY or field.access_bus == READ_WRITE:
+                                               brs.append(field.storage)
+                                               reg_readable = True
+                                       else:
+                                               brs.append(Constant(0, BV(field.size)))
+                               if reg_readable:
+                                       if len(brs) > 1:
+                                               brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(f.Cat(*brs))])
+                                       else:
+                                               brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(brs[0])])
+                       else:
+                               brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(reg.dev_w)])
                if brcases:
                        sync.append(self.interface.d_o.eq(Constant(0, BV(8))))
                        sync.append(If(self._sel, Case(self.interface.a_i[:nbits], *brcases)))
@@ -60,10 +69,11 @@ class Bank:
                
                # Device access
                for reg in self.description:
-                       for field in reg.fields:
-                               if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE:
-                                       comb.append(field.dev_r.eq(field.storage))
-                               if field.access_dev == WRITE_ONLY or field.access_dev == READ_WRITE:
-                                       sync.append(If(field.dev_we, field.storage.eq(field.dev_w)))
+                       if reg.raw is None:
+                               for field in reg.fields:
+                                       if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE:
+                                               comb.append(field.dev_r.eq(field.storage))
+                                       if field.access_dev == WRITE_ONLY or field.access_dev == READ_WRITE:
+                                               sync.append(If(field.dev_we, field.storage.eq(field.dev_w)))
                
                return Fragment(comb, sync)

diff --git a/migen/bank/description.py b/migen/bank/description.py
index d0115f7fbac5ba51fb0ce809589b12f0ec5c73d7..102deff01801ced218bac9844f134ac75ec64d6d 100644 (file)
--- a/migen/bank/description.py
+++ b/migen/bank/description.py
@@ -1,9 +1,15 @@
 from migen.fhdl.structure import *
 
 class Register:
-       def __init__(self, name):
+       def __init__(self, name, raw=None):
                self.name = name
-               self.fields = []
+               self.raw = raw
+               if raw is not None:
+                       self.dev_re = Signal(name=name + "_re")
+                       self.dev_r = Signal(raw, name + "_r")
+                       self.dev_w = Signal(raw, name + "_w")
+               else:
+                       self.fields = []
        
        def add_field(self, f):
                self.fields.append(f)