fhdl/verilog: fix representation of negative integers

Give the explicit two's complement representation for the given bit width.

This results in less readable code compared to using unary minus,
but fixes a bug when trying to represent the most negative integer.

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index fc56f78493b9054910b4b67e30a71553cbf98a83..684812a52b2711d69ffa18b5cdb7bb0ce3c02577 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -27,7 +27,8 @@ def _printintbool(node):
                if node >= 0:
                        return str(bits_for(node)) + "'d" + str(node), False
                else:
-                       return "-" + str(bits_for(node)) + "'sd" + str(-node), True
+                       nbits = bits_for(node)
+                       return str(nbits) + "'sd" + str(2**nbits + node), True
        else:
                raise TypeError