radeonsi: rename and rearrange RW buffer slots

- use an enum
- use a unique slot number regardless of the shader stage
  (the per-stage slots will go away for RW buffers)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 2306a8b23ec53415eccbc900166a639f6a42bdb2..425c6a0860b01955eaece1627f0e00d6cc6ee026 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1053,7 +1053,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
 
        /* Set the shader resources.*/
        for (i = 0; i < num_targets; i++) {
-               bufidx = SI_SO_BUF_OFFSET + i;
+               bufidx = SI_VS_STREAMOUT_BUF0 + i;
 
                if (targets[i]) {
                        struct pipe_resource *buffer = targets[i]->buffer;
@@ -1093,7 +1093,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
                buffers->desc.dirty_mask |= 1llu << bufidx;
        }
        for (; i < old_num_targets; i++) {
-               bufidx = SI_SO_BUF_OFFSET + i;
+               bufidx = SI_VS_STREAMOUT_BUF0 + i;
                /* Clear the descriptor and unset the resource. */
                memset(buffers->desc.list + bufidx*4, 0, sizeof(uint32_t) * 4);
                pipe_resource_reference(&buffers->buffers[bufidx], NULL);
@@ -1220,7 +1220,7 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
                                                      rbuffer, buffers->shader_usage,
                                                      buffers->priority);
 
-                               if (i >= SI_SO_BUF_OFFSET && shader == PIPE_SHADER_VERTEX) {
+                               if (i >= SI_VS_STREAMOUT_BUF0 && shader == PIPE_SHADER_VERTEX) {
                                        /* Update the streamout state. */
                                        if (sctx->b.streamout.begin_emitted) {
                                                r600_emit_streamout_end(&sctx->b);

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index c48ae3b5636930356f05e086ff41f76de3336592..e8393869f9f0c251d0a7e6423140601fd8ba71ab 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2186,7 +2186,7 @@ static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
        rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
                                  SI_PARAM_RW_BUFFERS);
        buffer = build_indexed_load_const(ctx, rw_buffers,
-                       lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
+                       lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
 
        /* Get the offset. */
        tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
@@ -5240,7 +5240,7 @@ static void preload_streamout_buffers(struct si_shader_context *ctx)
        for (i = 0; i < 4; ++i) {
                if (ctx->shader->selector->so.stride[i]) {
                        LLVMValueRef offset = lp_build_const_int32(gallivm,
-                                                                  SI_SO_BUF_OFFSET + i);
+                                                                  SI_VS_STREAMOUT_BUF0 + i);
 
                        ctx->so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
                }
@@ -5264,14 +5264,17 @@ static void preload_ring_buffers(struct si_shader_context *ctx)
            (ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
             ctx->shader->key.tes.as_es) ||
            ctx->type == TGSI_PROCESSOR_GEOMETRY) {
-               LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
+               unsigned ring =
+                       ctx->type == TGSI_PROCESSOR_GEOMETRY ? SI_GS_RING_ESGS
+                                                            : SI_ES_RING_ESGS;
+               LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
 
                ctx->esgs_ring =
                        build_indexed_load_const(ctx, buf_ptr, offset);
        }
 
        if (ctx->is_gs_copy_shader) {
-               LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
+               LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
 
                ctx->gsvs_ring[0] =
                        build_indexed_load_const(ctx, buf_ptr, offset);
@@ -5279,7 +5282,7 @@ static void preload_ring_buffers(struct si_shader_context *ctx)
        if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
                int i;
                for (i = 0; i < 4; i++) {
-                       LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
+                       LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
 
                        ctx->gsvs_ring[i] =
                                build_indexed_load_const(ctx, buf_ptr, offset);

diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index cbe91dd43d7214ad50713df047abfaa4e5b70191..1571bad98453cec2118a88936265d8d7524c2da8 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -164,20 +164,26 @@ struct si_shader_data {
 
 #define SI_NUM_SHADER_BUFFERS          16
 
-/* Read-write buffer slots.
- *
- * Ring buffers:        0..1
- * Streamout buffers:   2..5
- */
-#define SI_RING_TESS_FACTOR    0 /* for HS (TCS)  */
-#define SI_RING_ESGS           0 /* for ES, GS */
-#define SI_RING_GSVS           1 /* for GS, VS */
-#define SI_RING_GSVS_1         2 /* 1, 2, 3 for GS */
-#define SI_RING_GSVS_2         3
-#define SI_RING_GSVS_3         4
-#define SI_NUM_RING_BUFFERS    5
-#define SI_SO_BUF_OFFSET       SI_NUM_RING_BUFFERS
-#define SI_NUM_RW_BUFFERS      (SI_SO_BUF_OFFSET + 4)
+/* Private read-write buffer slots. */
+enum {
+       SI_HS_RING_TESS_FACTOR,
+
+       SI_ES_RING_ESGS,
+       SI_GS_RING_ESGS,
+
+       SI_GS_RING_GSVS0,
+       SI_GS_RING_GSVS1,
+       SI_GS_RING_GSVS2,
+       SI_GS_RING_GSVS3,
+       SI_VS_RING_GSVS,
+
+       SI_VS_STREAMOUT_BUF0,
+       SI_VS_STREAMOUT_BUF1,
+       SI_VS_STREAMOUT_BUF2,
+       SI_VS_STREAMOUT_BUF3,
+
+       SI_NUM_RW_BUFFERS,
+};
 
 #define SI_NUM_VERTEX_BUFFERS  SI_MAX_ATTRIBS
 

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 49e688adb179f603c3dd60fff0004898372f6ddf..5c923cb80c1e573294e99db4bd0cd7c992a7979c 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1565,15 +1565,15 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
 
        /* Set ring bindings. */
        if (sctx->esgs_ring) {
-               si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
+               si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_ES_RING_ESGS,
                                   sctx->esgs_ring, 0, sctx->esgs_ring->width0,
                                   true, true, 4, 64, 0);
-               si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
+               si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_ESGS,
                                   sctx->esgs_ring, 0, sctx->esgs_ring->width0,
                                   false, false, 0, 0, 0);
        }
        if (sctx->gsvs_ring)
-               si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
+               si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_VS_RING_GSVS,
                                   sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
                                   false, false, 0, 0, 0);
        return true;
@@ -1589,22 +1589,22 @@ static void si_update_gsvs_ring_bindings(struct si_context *sctx)
 
        sctx->last_gsvs_itemsize = gsvs_itemsize;
 
-       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
+       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS0,
                           sctx->gsvs_ring, gsvs_itemsize,
                           64, true, true, 4, 16, 0);
 
        offset = gsvs_itemsize * 64;
-       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
+       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS1,
                           sctx->gsvs_ring, gsvs_itemsize,
                           64, true, true, 4, 16, offset);
 
        offset = (gsvs_itemsize * 2) * 64;
-       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
+       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS2,
                           sctx->gsvs_ring, gsvs_itemsize,
                           64, true, true, 4, 16, offset);
 
        offset = (gsvs_itemsize * 3) * 64;
-       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
+       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS3,
                           sctx->gsvs_ring, gsvs_itemsize,
                           64, true, true, 4, 16, offset);
 }
@@ -1793,7 +1793,7 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
        si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
 
        si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
-                          SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
+                          SI_HS_RING_TESS_FACTOR, sctx->tf_ring, 0,
                           sctx->tf_ring->width0, false, false, 0, 0, 0);
 }