from m5.params import *
from m5.proxy import *
-from Gic import Pl390
+from Gic import GicV2
-class MuxingKvmGic(Pl390):
+class MuxingKvmGic(GicV2):
type = 'MuxingKvmGic'
cxx_header = "arch/arm/kvm/gic.hh"
MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams *p)
- : Pl390(p),
+ : GicV2(p),
system(*p->system),
kernelGic(nullptr),
usingKvm(false)
void
MuxingKvmGic::startup()
{
- Pl390::startup();
+ GicV2::startup();
usingKvm = (kernelGic != nullptr) && system.validKvmEnvironment();
if (usingKvm)
- fromPl390ToKvm();
+ fromGicV2ToKvm();
}
DrainState
MuxingKvmGic::drain()
{
if (usingKvm)
- fromKvmToPl390();
- return Pl390::drain();
+ fromKvmToGicV2();
+ return GicV2::drain();
}
void
MuxingKvmGic::drainResume()
{
- Pl390::drainResume();
+ GicV2::drainResume();
bool use_kvm = (kernelGic != nullptr) && system.validKvmEnvironment();
if (use_kvm != usingKvm) {
// Should only occur due to CPU switches
if (use_kvm) // from simulation to KVM emulation
- fromPl390ToKvm();
- // otherwise, drain() already sync'd the state back to the Pl390
+ fromGicV2ToKvm();
+ // otherwise, drain() already sync'd the state back to the GicV2
usingKvm = use_kvm;
}
MuxingKvmGic::read(PacketPtr pkt)
{
if (!usingKvm)
- return Pl390::read(pkt);
+ return GicV2::read(pkt);
panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
}
MuxingKvmGic::write(PacketPtr pkt)
{
if (!usingKvm)
- return Pl390::write(pkt);
+ return GicV2::write(pkt);
panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
}
MuxingKvmGic::sendInt(uint32_t num)
{
if (!usingKvm)
- return Pl390::sendInt(num);
+ return GicV2::sendInt(num);
DPRINTF(Interrupt, "Set SPI %d\n", num);
kernelGic->setSPI(num);
MuxingKvmGic::clearInt(uint32_t num)
{
if (!usingKvm)
- return Pl390::clearInt(num);
+ return GicV2::clearInt(num);
DPRINTF(Interrupt, "Clear SPI %d\n", num);
kernelGic->clearSPI(num);
MuxingKvmGic::sendPPInt(uint32_t num, uint32_t cpu)
{
if (!usingKvm)
- return Pl390::sendPPInt(num, cpu);
+ return GicV2::sendPPInt(num, cpu);
DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
kernelGic->setPPI(cpu, num);
}
MuxingKvmGic::clearPPInt(uint32_t num, uint32_t cpu)
{
if (!usingKvm)
- return Pl390::clearPPInt(num, cpu);
+ return GicV2::clearPPInt(num, cpu);
DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
kernelGic->clearPPI(cpu, num);
void
MuxingKvmGic::updateIntState(int hint)
{
- // During Kvm->Pl390 state transfer, writes to the Pl390 will call
+ // During Kvm->GicV2 state transfer, writes to the GicV2 will call
// updateIntState() which can post an interrupt. Since we're only
- // using the Pl390 model for holding state in this circumstance, we
- // short-circuit this behavior, as the Pl390 is not actually active.
+ // using the GicV2 model for holding state in this circumstance, we
+ // short-circuit this behavior, as the GicV2 is not actually active.
if (!usingKvm)
- return Pl390::updateIntState(hint);
+ return GicV2::updateIntState(hint);
}
void
copyDistRegister(from, to, 0, GICD_CTLR);
// Copy interrupt-enabled statuses (I[CS]ENABLERn; R0 is per-CPU banked)
- set = Pl390::GICD_ISENABLER.start();
- clear = Pl390::GICD_ICENABLER.start();
- size = Pl390::itLines / 8;
+ set = GicV2::GICD_ISENABLER.start();
+ clear = GicV2::GICD_ICENABLER.start();
+ size = GicV2::itLines / 8;
clearBankedDistRange(to, clear, 4);
copyBankedDistRange(from, to, set, 4);
copyDistRange(from, to, set, size);
// Copy pending interrupts (I[CS]PENDRn; R0 is per-CPU banked)
- set = Pl390::GICD_ISPENDR.start();
- clear = Pl390::GICD_ICPENDR.start();
- size = Pl390::itLines / 8;
+ set = GicV2::GICD_ISPENDR.start();
+ clear = GicV2::GICD_ICPENDR.start();
+ size = GicV2::itLines / 8;
clearBankedDistRange(to, clear, 4);
copyBankedDistRange(from, to, set, 4);
copyDistRange(from, to, set, size);
// Copy active interrupts (I[CS]ACTIVERn; R0 is per-CPU banked)
- set = Pl390::GICD_ISACTIVER.start();
- clear = Pl390::GICD_ICACTIVER.start();
- size = Pl390::itLines / 8;
+ set = GicV2::GICD_ISACTIVER.start();
+ clear = GicV2::GICD_ICACTIVER.start();
+ size = GicV2::itLines / 8;
clearBankedDistRange(to, clear, 4);
copyBankedDistRange(from, to, set, 4);
copyDistRange(from, to, set, size);
// Copy interrupt priorities (IPRIORITYRn; R0-7 are per-CPU banked)
- set = Pl390::GICD_IPRIORITYR.start();
+ set = GicV2::GICD_IPRIORITYR.start();
copyBankedDistRange(from, to, set, 32);
set += 32;
- size = Pl390::itLines - 32;
+ size = GicV2::itLines - 32;
copyDistRange(from, to, set, size);
// Copy interrupt processor target regs (ITARGETRn; R0-7 are read-only)
- set = Pl390::GICD_ITARGETSR.start() + 32;
- size = Pl390::itLines - 32;
+ set = GicV2::GICD_ITARGETSR.start() + 32;
+ size = GicV2::itLines - 32;
copyDistRange(from, to, set, size);
// Copy interrupt configuration registers (ICFGRn)
- set = Pl390::GICD_ICFGR.start();
- size = Pl390::itLines / 4;
+ set = GicV2::GICD_ICFGR.start();
+ size = GicV2::itLines / 4;
copyDistRange(from, to, set, size);
}
void
-MuxingKvmGic::fromPl390ToKvm()
+MuxingKvmGic::fromGicV2ToKvm()
{
- copyGicState(static_cast<Pl390*>(this), kernelGic);
+ copyGicState(static_cast<GicV2*>(this), kernelGic);
}
void
-MuxingKvmGic::fromKvmToPl390()
+MuxingKvmGic::fromKvmToGicV2()
{
- copyGicState(kernelGic, static_cast<Pl390*>(this));
+ copyGicState(kernelGic, static_cast<GicV2*>(this));
// the values read for the Interrupt Priority Mask Register (PMR)
// have been shifted by three bits due to its having been emulated by
#include "arch/arm/system.hh"
#include "cpu/kvm/device.hh"
#include "cpu/kvm/vm.hh"
-#include "dev/arm/gic_pl390.hh"
+#include "dev/arm/gic_v2.hh"
#include "dev/platform.hh"
/**
struct MuxingKvmGicParams;
-class MuxingKvmGic : public Pl390
+class MuxingKvmGic : public GicV2
{
public: // SimObject / Serializable / Drainable
MuxingKvmGic(const MuxingKvmGicParams *p);
Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;
- public: // Pl390
+ public: // GicV2
void sendInt(uint32_t num) override;
void clearInt(uint32_t num) override;
void sendPPInt(uint32_t num, uint32_t cpu) override;
void clearPPInt(uint32_t num, uint32_t cpu) override;
- protected: // Pl390
+ protected: // GicV2
void updateIntState(int hint) override;
protected:
bool usingKvm;
/** Multiplexing implementation */
- void fromPl390ToKvm();
- void fromKvmToPl390();
+ void fromGicV2ToKvm();
+ void fromKvmToGicV2();
void copyGicState(BaseGicRegisters* from, BaseGicRegisters* to);
cxx_header = "dev/arm/base_gic.hh"
cxx_class = "ArmPPIGen"
-class Pl390(BaseGic):
- type = 'Pl390'
- cxx_header = "dev/arm/gic_pl390.hh"
+class GicV2(BaseGic):
+ type = 'GicV2'
+ cxx_header = "dev/arm/gic_v2.hh"
dist_addr = Param.Addr("Address for distributor")
cpu_addr = Param.Addr("Address for cpu")
except ImportError:
# KVM support wasn't compiled into gem5. Fallback to a
# software-only GIC.
- kvm_gicv2_class = Pl390
+ kvm_gicv2_class = GicV2
pass
class AmbaPioDevice(BasicPioDevice):
realview_io = RealViewCtrl(pio_addr=0x10000000)
mcc = VExpressMCC()
dcc = CoreTile2A15DCC()
- gic = Pl390(cpu_addr=0x1f000100, dist_addr=0x1f001000, cpu_size=0x100)
+ gic = GicV2(cpu_addr=0x1f000100, dist_addr=0x1f001000, cpu_size=0x100)
pci_host = GenericPciHost(
conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
pci_pio_base=0)
dcc = CoreTile2A15DCC()
### On-chip devices ###
- gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
+ gic = GicV2(dist_addr=0x2C001000, cpu_addr=0x2C002000)
vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
InterruptLine=2, InterruptPin=2)
def enableMSIX(self):
- self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
+ self.gic = GicV2(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
self.gicv2m = Gicv2m()
self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
Source('base_gic.cc')
Source('flash_device.cc')
Source('generic_timer.cc')
- Source('gic_pl390.cc')
+ Source('gic_v2.cc')
Source('gic_v2m.cc')
Source('pl011.cc')
Source('pl111.cc')
+++ /dev/null
-/*
- * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- * Prakash Ramrakhyani
- */
-
-#include "dev/arm/gic_pl390.hh"
-
-#include "base/trace.hh"
-#include "debug/Checkpoint.hh"
-#include "debug/GIC.hh"
-#include "debug/IPI.hh"
-#include "debug/Interrupt.hh"
-#include "mem/packet.hh"
-#include "mem/packet_access.hh"
-
-const AddrRange Pl390::GICD_IGROUPR (0x080, 0x0ff);
-const AddrRange Pl390::GICD_ISENABLER (0x100, 0x17f);
-const AddrRange Pl390::GICD_ICENABLER (0x180, 0x1ff);
-const AddrRange Pl390::GICD_ISPENDR (0x200, 0x27f);
-const AddrRange Pl390::GICD_ICPENDR (0x280, 0x2ff);
-const AddrRange Pl390::GICD_ISACTIVER (0x300, 0x37f);
-const AddrRange Pl390::GICD_ICACTIVER (0x380, 0x3ff);
-const AddrRange Pl390::GICD_IPRIORITYR(0x400, 0x7ff);
-const AddrRange Pl390::GICD_ITARGETSR (0x800, 0xbff);
-const AddrRange Pl390::GICD_ICFGR (0xc00, 0xcff);
-
-Pl390::Pl390(const Params *p)
- : BaseGic(p),
- distRange(RangeSize(p->dist_addr, DIST_SIZE)),
- cpuRange(RangeSize(p->cpu_addr, p->cpu_size)),
- addrRanges{distRange, cpuRange},
- distPioDelay(p->dist_pio_delay),
- cpuPioDelay(p->cpu_pio_delay), intLatency(p->int_latency),
- enabled(false), haveGem5Extensions(p->gem5_extensions),
- itLines(p->it_lines),
- intEnabled {}, pendingInt {}, activeInt {},
- intPriority {}, cpuTarget {}, intConfig {},
- cpuSgiPending {}, cpuSgiActive {},
- cpuSgiPendingExt {}, cpuSgiActiveExt {},
- cpuPpiPending {}, cpuPpiActive {},
- pendingDelayedInterrupts(0)
-{
- for (int x = 0; x < CPU_MAX; x++) {
- iccrpr[x] = 0xff;
- cpuEnabled[x] = false;
- cpuPriority[x] = 0xff;
- cpuBpr[x] = GICC_BPR_MINIMUM;
- // Initialize cpu highest int
- cpuHighestInt[x] = SPURIOUS_INT;
- postIntEvent[x] =
- new EventFunctionWrapper([this, x]{ postDelayedInt(x); },
- "Post Interrupt to CPU");
- }
- DPRINTF(Interrupt, "cpuEnabled[0]=%d cpuEnabled[1]=%d\n", cpuEnabled[0],
- cpuEnabled[1]);
-
- gem5ExtensionsEnabled = false;
-}
-
-Pl390::~Pl390()
-{
- for (int x = 0; x < CPU_MAX; x++)
- delete postIntEvent[x];
-}
-
-Tick
-Pl390::read(PacketPtr pkt)
-{
- const Addr addr = pkt->getAddr();
-
- if (distRange.contains(addr))
- return readDistributor(pkt);
- else if (cpuRange.contains(addr))
- return readCpu(pkt);
- else
- panic("Read to unknown address %#x\n", pkt->getAddr());
-}
-
-
-Tick
-Pl390::write(PacketPtr pkt)
-{
- const Addr addr = pkt->getAddr();
-
- if (distRange.contains(addr))
- return writeDistributor(pkt);
- else if (cpuRange.contains(addr))
- return writeCpu(pkt);
- else
- panic("Write to unknown address %#x\n", pkt->getAddr());
-}
-
-Tick
-Pl390::readDistributor(PacketPtr pkt)
-{
- const Addr daddr = pkt->getAddr() - distRange.start();
- const ContextID ctx = pkt->req->contextId();
-
- DPRINTF(GIC, "gic distributor read register %#x\n", daddr);
-
- const uint32_t resp = readDistributor(ctx, daddr, pkt->getSize());
-
- switch (pkt->getSize()) {
- case 1:
- pkt->set<uint8_t>(resp);
- break;
- case 2:
- pkt->set<uint16_t>(resp);
- break;
- case 4:
- pkt->set<uint32_t>(resp);
- break;
- default:
- panic("Invalid size while reading Distributor regs in GIC: %d\n",
- pkt->getSize());
- }
-
- pkt->makeAtomicResponse();
- return distPioDelay;
-}
-
-uint32_t
-Pl390::readDistributor(ContextID ctx, Addr daddr, size_t resp_sz)
-{
- if (GICD_IGROUPR.contains(daddr)) {
- return 0; // unimplemented; RAZ (read as zero)
- }
-
- if (GICD_ISENABLER.contains(daddr)) {
- uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
- assert(ix < 32);
- return getIntEnabled(ctx, ix);
- }
-
- if (GICD_ICENABLER.contains(daddr)) {
- uint32_t ix = (daddr - GICD_ICENABLER.start()) >> 2;
- assert(ix < 32);
- return getIntEnabled(ctx, ix);
- }
-
- if (GICD_ISPENDR.contains(daddr)) {
- uint32_t ix = (daddr - GICD_ISPENDR.start()) >> 2;
- assert(ix < 32);
- return getPendingInt(ctx, ix);
- }
-
- if (GICD_ICPENDR.contains(daddr)) {
- uint32_t ix = (daddr - GICD_ICPENDR.start()) >> 2;
- assert(ix < 32);
- return getPendingInt(ctx, ix);
- }
-
- if (GICD_ISACTIVER.contains(daddr)) {
- uint32_t ix = (daddr - GICD_ISACTIVER.start()) >> 2;
- assert(ix < 32);
- return getActiveInt(ctx, ix);
- }
-
- if (GICD_ICACTIVER.contains(daddr)) {
- uint32_t ix = (daddr - GICD_ICACTIVER.start()) >> 2;
- assert(ix < 32);
- return getActiveInt(ctx, ix);
- }
-
- if (GICD_IPRIORITYR.contains(daddr)) {
- Addr int_num = daddr - GICD_IPRIORITYR.start();
- assert(int_num < INT_LINES_MAX);
- DPRINTF(Interrupt, "Reading interrupt priority at int# %#x \n",int_num);
-
- switch (resp_sz) {
- default: // will panic() after return to caller anyway
- case 1:
- return getIntPriority(ctx, int_num);
- case 2:
- assert((int_num + 1) < INT_LINES_MAX);
- return (getIntPriority(ctx, int_num) |
- getIntPriority(ctx, int_num+1) << 8);
- case 4:
- assert((int_num + 3) < INT_LINES_MAX);
- return (getIntPriority(ctx, int_num) |
- getIntPriority(ctx, int_num+1) << 8 |
- getIntPriority(ctx, int_num+2) << 16 |
- getIntPriority(ctx, int_num+3) << 24);
- }
- }
-
- if (GICD_ITARGETSR.contains(daddr)) {
- Addr int_num = daddr - GICD_ITARGETSR.start();
- DPRINTF(GIC, "Reading processor target register for int# %#x \n",
- int_num);
- assert(int_num < INT_LINES_MAX);
-
- if (resp_sz == 1) {
- return getCpuTarget(ctx, int_num);
- } else {
- assert(resp_sz == 4);
- int_num = mbits(int_num, 31, 2);
- return (getCpuTarget(ctx, int_num) |
- getCpuTarget(ctx, int_num+1) << 8 |
- getCpuTarget(ctx, int_num+2) << 16 |
- getCpuTarget(ctx, int_num+3) << 24) ;
- }
- }
-
- if (GICD_ICFGR.contains(daddr)) {
- uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2;
- assert(ix < 64);
- /** @todo software generated interrupts and PPIs
- * can't be configured in some ways */
- return intConfig[ix];
- }
-
- switch(daddr) {
- case GICD_CTLR:
- return enabled;
- case GICD_TYPER:
- /* The 0x100 is a made-up flag to show that gem5 extensions
- * are available,
- * write 0x200 to this register to enable it. */
- return (((sys->numRunningContexts() - 1) << 5) |
- (itLines/INT_BITS_MAX -1) |
- (haveGem5Extensions ? 0x100 : 0x0));
- case GICD_PIDR0:
- //ARM defined DevID
- return (GICD_400_PIDR_VALUE & 0xFF);
- case GICD_PIDR1:
- return ((GICD_400_PIDR_VALUE >> 8) & 0xFF);
- case GICD_PIDR2:
- return ((GICD_400_PIDR_VALUE >> 16) & 0xFF);
- case GICD_PIDR3:
- return ((GICD_400_PIDR_VALUE >> 24) & 0xFF);
- case GICD_IIDR:
- /* revision id is resorted to 1 and variant to 0*/
- return GICD_400_IIDR_VALUE;
- default:
- panic("Tried to read Gic distributor at offset %#x\n", daddr);
- break;
- }
-}
-
-Tick
-Pl390::readCpu(PacketPtr pkt)
-{
- const Addr daddr = pkt->getAddr() - cpuRange.start();
-
- assert(pkt->req->hasContextId());
- const ContextID ctx = pkt->req->contextId();
- assert(ctx < sys->numRunningContexts());
-
- DPRINTF(GIC, "gic cpu read register %#x cpu context: %d\n", daddr,
- ctx);
-
- pkt->set<uint32_t>(readCpu(ctx, daddr));
-
- pkt->makeAtomicResponse();
- return cpuPioDelay;
-}
-
-uint32_t
-Pl390::readCpu(ContextID ctx, Addr daddr)
-{
- switch(daddr) {
- case GICC_IIDR:
- return GICC_400_IIDR_VALUE;
- case GICC_CTLR:
- return cpuEnabled[ctx];
- case GICC_PMR:
- return cpuPriority[ctx];
- case GICC_BPR:
- return cpuBpr[ctx];
- case GICC_IAR:
- if (enabled && cpuEnabled[ctx]) {
- int active_int = cpuHighestInt[ctx];
- IAR iar = 0;
- iar.ack_id = active_int;
- iar.cpu_id = 0;
- if (active_int < SGI_MAX) {
- // this is a software interrupt from another CPU
- if (!gem5ExtensionsEnabled) {
- panic_if(!cpuSgiPending[active_int],
- "Interrupt %d active but no CPU generated it?\n",
- active_int);
- for (int x = 0; x < sys->numRunningContexts(); x++) {
- // See which CPU generated the interrupt
- uint8_t cpugen =
- bits(cpuSgiPending[active_int], 7 + 8 * x, 8 * x);
- if (cpugen & (1 << ctx)) {
- iar.cpu_id = x;
- break;
- }
- }
- uint64_t sgi_num = ULL(1) << (ctx + 8 * iar.cpu_id);
- cpuSgiActive[iar.ack_id] |= sgi_num;
- cpuSgiPending[iar.ack_id] &= ~sgi_num;
- } else {
- uint64_t sgi_num = ULL(1) << iar.ack_id;
- cpuSgiActiveExt[ctx] |= sgi_num;
- cpuSgiPendingExt[ctx] &= ~sgi_num;
- }
- } else if (active_int < (SGI_MAX + PPI_MAX) ) {
- uint32_t int_num = 1 << (cpuHighestInt[ctx] - SGI_MAX);
- cpuPpiActive[ctx] |= int_num;
- updateRunPri();
- cpuPpiPending[ctx] &= ~int_num;
-
- } else {
- uint32_t int_num = 1 << intNumToBit(cpuHighestInt[ctx]);
- getActiveInt(ctx, intNumToWord(cpuHighestInt[ctx])) |= int_num;
- updateRunPri();
- getPendingInt(ctx, intNumToWord(cpuHighestInt[ctx]))
- &= ~int_num;
- }
-
- DPRINTF(Interrupt,"CPU %d reading IAR.id=%d IAR.cpu=%d, iar=0x%x\n",
- ctx, iar.ack_id, iar.cpu_id, iar);
- cpuHighestInt[ctx] = SPURIOUS_INT;
- updateIntState(-1);
- platform->intrctrl->clear(ctx, ArmISA::INT_IRQ, 0);
- return iar;
- } else {
- return SPURIOUS_INT;
- }
-
- break;
- case GICC_RPR:
- return iccrpr[0];
- case GICC_HPPIR:
- panic("Need to implement HPIR");
- break;
- default:
- panic("Tried to read Gic cpu at offset %#x\n", daddr);
- break;
- }
-}
-
-Tick
-Pl390::writeDistributor(PacketPtr pkt)
-{
- const Addr daddr = pkt->getAddr() - distRange.start();
-
- assert(pkt->req->hasContextId());
- const ContextID ctx = pkt->req->contextId();
- const size_t data_sz = pkt->getSize();
-
- uint32_t pkt_data M5_VAR_USED;
- switch (data_sz)
- {
- case 1:
- pkt_data = pkt->get<uint8_t>();
- break;
- case 2:
- pkt_data = pkt->get<uint16_t>();
- break;
- case 4:
- pkt_data = pkt->get<uint32_t>();
- break;
- default:
- panic("Invalid size when writing to priority regs in Gic: %d\n",
- data_sz);
- }
-
- DPRINTF(GIC, "gic distributor write register %#x size %#x value %#x \n",
- daddr, data_sz, pkt_data);
-
- writeDistributor(ctx, daddr, pkt_data, data_sz);
-
- pkt->makeAtomicResponse();
- return distPioDelay;
-}
-
-void
-Pl390::writeDistributor(ContextID ctx, Addr daddr, uint32_t data,
- size_t data_sz)
-{
- if (GICD_IGROUPR.contains(daddr)) {
- return; // unimplemented; WI (writes ignored)
- }
-
- if (GICD_ISENABLER.contains(daddr)) {
- uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
- assert(ix < 32);
- getIntEnabled(ctx, ix) |= data;
- return;
- }
-
- if (GICD_ICENABLER.contains(daddr)) {
- uint32_t ix = (daddr - GICD_ICENABLER.start()) >> 2;
- assert(ix < 32);
- getIntEnabled(ctx, ix) &= ~data;
- return;
- }
-
- if (GICD_ISPENDR.contains(daddr)) {
- uint32_t ix = (daddr - GICD_ISPENDR.start()) >> 2;
- auto mask = data;
- if (ix == 0) mask &= SGI_MASK; // Don't allow SGIs to be changed
- getPendingInt(ctx, ix) |= mask;
- updateIntState(ix);
- return;
- }
-
- if (GICD_ICPENDR.contains(daddr)) {
- uint32_t ix = (daddr - GICD_ICPENDR.start()) >> 2;
- auto mask = data;
- if (ix == 0) mask &= SGI_MASK; // Don't allow SGIs to be changed
- getPendingInt(ctx, ix) &= ~mask;
- updateIntState(ix);
- return;
- }
-
- if (GICD_ISACTIVER.contains(daddr)) {
- uint32_t ix = (daddr - GICD_ISACTIVER.start()) >> 2;
- getActiveInt(ctx, ix) |= data;
- return;
- }
-
- if (GICD_ICACTIVER.contains(daddr)) {
- uint32_t ix = (daddr - GICD_ICACTIVER.start()) >> 2;
- getActiveInt(ctx, ix) &= ~data;
- return;
- }
-
- if (GICD_IPRIORITYR.contains(daddr)) {
- Addr int_num = daddr - GICD_IPRIORITYR.start();
- switch(data_sz) {
- case 1:
- getIntPriority(ctx, int_num) = data;
- break;
- case 2: {
- getIntPriority(ctx, int_num) = bits(data, 7, 0);
- getIntPriority(ctx, int_num + 1) = bits(data, 15, 8);
- break;
- }
- case 4: {
- getIntPriority(ctx, int_num) = bits(data, 7, 0);
- getIntPriority(ctx, int_num + 1) = bits(data, 15, 8);
- getIntPriority(ctx, int_num + 2) = bits(data, 23, 16);
- getIntPriority(ctx, int_num + 3) = bits(data, 31, 24);
- break;
- }
- default:
- panic("Invalid size when writing to priority regs in Gic: %d\n",
- data_sz);
- }
-
- updateIntState(-1);
- updateRunPri();
- return;
- }
-
- if (GICD_ITARGETSR.contains(daddr)) {
- Addr int_num = daddr - GICD_ITARGETSR.start();
- // Interrupts 0-31 are read only
- unsigned offset = SGI_MAX + PPI_MAX;
- if (int_num >= offset) {
- unsigned ix = int_num - offset; // index into cpuTarget array
- if (data_sz == 1) {
- cpuTarget[ix] = data & 0xff;
- } else {
- assert (data_sz == 4);
- cpuTarget[ix] = bits(data, 7, 0);
- cpuTarget[ix+1] = bits(data, 15, 8);
- cpuTarget[ix+2] = bits(data, 23, 16);
- cpuTarget[ix+3] = bits(data, 31, 24);
- }
- updateIntState(int_num >> 2);
- }
- return;
- }
-
- if (GICD_ICFGR.contains(daddr)) {
- uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2;
- assert(ix < INT_BITS_MAX*2);
- intConfig[ix] = data;
- if (data & NN_CONFIG_MASK)
- warn("GIC N:N mode selected and not supported at this time\n");
- return;
- }
-
- switch(daddr) {
- case GICD_CTLR:
- enabled = data;
- DPRINTF(Interrupt, "Distributor enable flag set to = %d\n", enabled);
- break;
- case GICD_TYPER:
- /* 0x200 is a made-up flag to enable gem5 extension functionality.
- * This reg is not normally written.
- */
- gem5ExtensionsEnabled = (data & 0x200) && haveGem5Extensions;
- DPRINTF(GIC, "gem5 extensions %s\n",
- gem5ExtensionsEnabled ? "enabled" : "disabled");
- break;
- case GICD_SGIR:
- softInt(ctx, data);
- break;
- default:
- panic("Tried to write Gic distributor at offset %#x\n", daddr);
- break;
- }
-}
-
-Tick
-Pl390::writeCpu(PacketPtr pkt)
-{
- const Addr daddr = pkt->getAddr() - cpuRange.start();
-
- assert(pkt->req->hasContextId());
- const ContextID ctx = pkt->req->contextId();
- const uint32_t data = pkt->get<uint32_t>();
-
- DPRINTF(GIC, "gic cpu write register cpu:%d %#x val: %#x\n",
- ctx, daddr, data);
-
- writeCpu(ctx, daddr, data);
-
- pkt->makeAtomicResponse();
- return cpuPioDelay;
-}
-
-void
-Pl390::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
-{
- switch(daddr) {
- case GICC_CTLR:
- cpuEnabled[ctx] = data;
- break;
- case GICC_PMR:
- cpuPriority[ctx] = data;
- break;
- case GICC_BPR: {
- auto bpr = data & 0x7;
- if (bpr < GICC_BPR_MINIMUM)
- bpr = GICC_BPR_MINIMUM;
- cpuBpr[ctx] = bpr;
- break;
- }
- case GICC_EOIR: {
- const IAR iar = data;
- if (iar.ack_id < SGI_MAX) {
- // Clear out the bit that corresponds to the cleared int
- uint64_t clr_int = ULL(1) << (ctx + 8 * iar.cpu_id);
- if (!(cpuSgiActive[iar.ack_id] & clr_int) &&
- !(cpuSgiActiveExt[ctx] & (1 << iar.ack_id)))
- panic("Done handling a SGI that isn't active?\n");
- if (gem5ExtensionsEnabled)
- cpuSgiActiveExt[ctx] &= ~(1 << iar.ack_id);
- else
- cpuSgiActive[iar.ack_id] &= ~clr_int;
- } else if (iar.ack_id < (SGI_MAX + PPI_MAX) ) {
- uint32_t int_num = 1 << (iar.ack_id - SGI_MAX);
- if (!(cpuPpiActive[ctx] & int_num))
- panic("CPU %d Done handling a PPI interrupt "
- "that isn't active?\n", ctx);
- cpuPpiActive[ctx] &= ~int_num;
- } else {
- uint32_t int_num = 1 << intNumToBit(iar.ack_id);
- if (!(getActiveInt(ctx, intNumToWord(iar.ack_id)) & int_num))
- warn("Done handling interrupt that isn't active: %d\n",
- intNumToBit(iar.ack_id));
- getActiveInt(ctx, intNumToWord(iar.ack_id)) &= ~int_num;
- }
- updateRunPri();
- DPRINTF(Interrupt, "CPU %d done handling intr IAR = %d from cpu %d\n",
- ctx, iar.ack_id, iar.cpu_id);
- break;
- }
- case GICC_APR0:
- case GICC_APR1:
- case GICC_APR2:
- case GICC_APR3:
- warn("GIC APRn write ignored because not implemented: %#x\n", daddr);
- break;
- default:
- panic("Tried to write Gic cpu at offset %#x\n", daddr);
- break;
- }
- if (cpuEnabled[ctx]) updateIntState(-1);
-}
-
-Pl390::BankedRegs&
-Pl390::getBankedRegs(ContextID ctx) {
- if (bankedRegs.size() <= ctx)
- bankedRegs.resize(ctx + 1);
-
- if (!bankedRegs[ctx])
- bankedRegs[ctx] = new BankedRegs;
- return *bankedRegs[ctx];
-}
-
-void
-Pl390::softInt(ContextID ctx, SWI swi)
-{
- if (gem5ExtensionsEnabled) {
- switch (swi.list_type) {
- case 0: {
- // interrupt cpus specified
- int dest = swi.cpu_list;
- DPRINTF(IPI, "Generating softIRQ from CPU %d for CPU %d\n",
- ctx, dest);
- if (cpuEnabled[dest]) {
- cpuSgiPendingExt[dest] |= (1 << swi.sgi_id);
- DPRINTF(IPI, "SGI[%d]=%#x\n", dest,
- cpuSgiPendingExt[dest]);
- }
- } break;
- case 1: {
- // interrupt all
- for (int i = 0; i < sys->numContexts(); i++) {
- DPRINTF(IPI, "Processing CPU %d\n", i);
- if (!cpuEnabled[i])
- continue;
- cpuSgiPendingExt[i] |= 1 << swi.sgi_id;
- DPRINTF(IPI, "SGI[%d]=%#x\n", swi.sgi_id,
- cpuSgiPendingExt[i]);
- }
- } break;
- case 2: {
- // Interrupt requesting cpu only
- DPRINTF(IPI, "Generating softIRQ from CPU %d for CPU %d\n",
- ctx, ctx);
- if (cpuEnabled[ctx]) {
- cpuSgiPendingExt[ctx] |= (1 << swi.sgi_id);
- DPRINTF(IPI, "SGI[%d]=%#x\n", ctx,
- cpuSgiPendingExt[ctx]);
- }
- } break;
- }
- } else {
- switch (swi.list_type) {
- case 1:
- // interrupt all
- uint8_t cpu_list;
- cpu_list = 0;
- for (int x = 0; x < sys->numContexts(); x++)
- cpu_list |= cpuEnabled[x] ? 1 << x : 0;
- swi.cpu_list = cpu_list;
- break;
- case 2:
- // interrupt requesting cpu only
- swi.cpu_list = 1 << ctx;
- break;
- // else interrupt cpus specified
- }
-
- DPRINTF(IPI, "Generating softIRQ from CPU %d for %#x\n", ctx,
- swi.cpu_list);
- for (int i = 0; i < sys->numContexts(); i++) {
- DPRINTF(IPI, "Processing CPU %d\n", i);
- if (!cpuEnabled[i])
- continue;
- if (swi.cpu_list & (1 << i))
- cpuSgiPending[swi.sgi_id] |= (1 << i) << (8 * ctx);
- DPRINTF(IPI, "SGI[%d]=%#x\n", swi.sgi_id,
- cpuSgiPending[swi.sgi_id]);
- }
- }
- updateIntState(-1);
-}
-
-uint64_t
-Pl390::genSwiMask(int cpu)
-{
- if (cpu > sys->numContexts())
- panic("Invalid CPU ID\n");
- return ULL(0x0101010101010101) << cpu;
-}
-
-uint8_t
-Pl390::getCpuPriority(unsigned cpu)
-{
- // see Table 3-2 in IHI0048B.b (GICv2)
- // mask some low-order priority bits per BPR value
- // NB: the GIC prioritization scheme is upside down:
- // lower values are higher priority; masking off bits
- // actually creates a higher priority, not lower.
- return cpuPriority[cpu] & (0xff00 >> (7 - cpuBpr[cpu]));
-}
-
-void
-Pl390::updateIntState(int hint)
-{
- for (int cpu = 0; cpu < sys->numContexts(); cpu++) {
- if (!cpuEnabled[cpu])
- continue;
-
- /*@todo use hint to do less work. */
- int highest_int = SPURIOUS_INT;
- // Priorities below that set in GICC_PMR can be ignored
- uint8_t highest_pri = getCpuPriority(cpu);
-
- // Check SGIs
- for (int swi = 0; swi < SGI_MAX; swi++) {
- if (!cpuSgiPending[swi] && !cpuSgiPendingExt[cpu])
- continue;
- if ((cpuSgiPending[swi] & genSwiMask(cpu)) ||
- (cpuSgiPendingExt[cpu] & (1 << swi)))
- if (highest_pri > getIntPriority(cpu, swi)) {
- highest_pri = getIntPriority(cpu, swi);
- highest_int = swi;
- }
- }
-
- // Check PPIs
- if (cpuPpiPending[cpu]) {
- for (int ppi = 0; ppi < PPI_MAX; ppi++) {
- if (cpuPpiPending[cpu] & (1 << ppi))
- if (highest_pri > getIntPriority(cpu, SGI_MAX + ppi)) {
- highest_pri = getIntPriority(cpu, SGI_MAX + ppi);
- highest_int = SGI_MAX + ppi;
- }
- }
- }
-
- bool mp_sys = sys->numRunningContexts() > 1;
- // Check other ints
- for (int x = 0; x < (itLines/INT_BITS_MAX); x++) {
- if (getIntEnabled(cpu, x) & getPendingInt(cpu, x)) {
- for (int y = 0; y < INT_BITS_MAX; y++) {
- uint32_t int_nm = x * INT_BITS_MAX + y;
- DPRINTF(GIC, "Checking for interrupt# %d \n",int_nm);
- /* Set current pending int as highest int for current cpu
- if the interrupt's priority higher than current priority
- and if current cpu is the target (for mp configs only)
- */
- if ((bits(getIntEnabled(cpu, x), y)
- &bits(getPendingInt(cpu, x), y)) &&
- (getIntPriority(cpu, int_nm) < highest_pri))
- if ((!mp_sys) ||
- (gem5ExtensionsEnabled
- ? (getCpuTarget(cpu, int_nm) == cpu)
- : (getCpuTarget(cpu, int_nm) & (1 << cpu)))) {
- highest_pri = getIntPriority(cpu, int_nm);
- highest_int = int_nm;
- }
- }
- }
- }
-
- cpuHighestInt[cpu] = highest_int;
-
- if (highest_int == SPURIOUS_INT)
- continue;
-
- /* @todo make this work for more than one cpu, need to handle 1:N, N:N
- * models */
- if (enabled && cpuEnabled[cpu] &&
- (highest_pri < getCpuPriority(cpu)) &&
- !(getActiveInt(cpu, intNumToWord(highest_int))
- & (1 << intNumToBit(highest_int)))) {
-
- DPRINTF(Interrupt, "Posting interrupt %d to cpu%d\n", highest_int,
- cpu);
- postInt(cpu, curTick() + intLatency);
- }
- }
-}
-
-void
-Pl390::updateRunPri()
-{
- for (int cpu = 0; cpu < sys->numContexts(); cpu++) {
- if (!cpuEnabled[cpu])
- continue;
- uint8_t maxPriority = 0xff;
- for (int i = 0; i < itLines; i++) {
- if (i < SGI_MAX) {
- if (((cpuSgiActive[i] & genSwiMask(cpu)) ||
- (cpuSgiActiveExt[cpu] & (1 << i))) &&
- (getIntPriority(cpu, i) < maxPriority))
- maxPriority = getIntPriority(cpu, i);
- } else if (i < (SGI_MAX + PPI_MAX)) {
- if ((cpuPpiActive[cpu] & ( 1 << (i - SGI_MAX))) &&
- (getIntPriority(cpu, i) < maxPriority))
- maxPriority = getIntPriority(cpu, i);
-
- } else {
- if (getActiveInt(cpu, intNumToWord(i))
- & (1 << intNumToBit(i)))
- if (getIntPriority(cpu, i) < maxPriority)
- maxPriority = getIntPriority(cpu, i);
- }
- }
- iccrpr[cpu] = maxPriority;
- }
-}
-
-void
-Pl390::sendInt(uint32_t num)
-{
- uint8_t target = getCpuTarget(0, num);
- DPRINTF(Interrupt, "Received Interrupt number %d, cpuTarget %#x: \n",
- num, target);
- if ((target & (target - 1)) && !gem5ExtensionsEnabled)
- panic("Multiple targets for peripheral interrupts is not supported\n");
- panic_if(num < SGI_MAX + PPI_MAX,
- "sentInt() must only be used for interrupts 32 and higher");
- getPendingInt(target, intNumToWord(num)) |= 1 << intNumToBit(num);
- updateIntState(intNumToWord(num));
-}
-
-void
-Pl390::sendPPInt(uint32_t num, uint32_t cpu)
-{
- DPRINTF(Interrupt, "Received PPI %d, cpuTarget %#x: \n",
- num, cpu);
- cpuPpiPending[cpu] |= 1 << (num - SGI_MAX);
- updateIntState(intNumToWord(num));
-}
-
-void
-Pl390::clearInt(uint32_t number)
-{
- /* @todo assume edge triggered only at the moment. Nothing to do. */
-}
-
-void
-Pl390::clearPPInt(uint32_t num, uint32_t cpu)
-{
- DPRINTF(Interrupt, "Clearing PPI %d, cpuTarget %#x: \n",
- num, cpu);
- cpuPpiPending[cpu] &= ~(1 << (num - SGI_MAX));
- updateIntState(intNumToWord(num));
-}
-
-void
-Pl390::postInt(uint32_t cpu, Tick when)
-{
- if (!(postIntEvent[cpu]->scheduled())) {
- ++pendingDelayedInterrupts;
- eventq->schedule(postIntEvent[cpu], when);
- }
-}
-
-void
-Pl390::postDelayedInt(uint32_t cpu)
-{
- platform->intrctrl->post(cpu, ArmISA::INT_IRQ, 0);
- --pendingDelayedInterrupts;
- assert(pendingDelayedInterrupts >= 0);
- if (pendingDelayedInterrupts == 0)
- signalDrainDone();
-}
-
-DrainState
-Pl390::drain()
-{
- if (pendingDelayedInterrupts == 0) {
- return DrainState::Drained;
- } else {
- return DrainState::Draining;
- }
-}
-
-
-void
-Pl390::drainResume()
-{
- // There may be pending interrupts if checkpointed from Kvm; post them.
- updateIntState(-1);
-}
-
-void
-Pl390::serialize(CheckpointOut &cp) const
-{
- DPRINTF(Checkpoint, "Serializing Arm GIC\n");
-
- SERIALIZE_SCALAR(enabled);
- SERIALIZE_SCALAR(itLines);
- SERIALIZE_ARRAY(intEnabled, INT_BITS_MAX-1);
- SERIALIZE_ARRAY(pendingInt, INT_BITS_MAX-1);
- SERIALIZE_ARRAY(activeInt, INT_BITS_MAX-1);
- SERIALIZE_ARRAY(iccrpr, CPU_MAX);
- SERIALIZE_ARRAY(intPriority, GLOBAL_INT_LINES);
- SERIALIZE_ARRAY(cpuTarget, GLOBAL_INT_LINES);
- SERIALIZE_ARRAY(intConfig, INT_BITS_MAX * 2);
- SERIALIZE_ARRAY(cpuEnabled, CPU_MAX);
- SERIALIZE_ARRAY(cpuPriority, CPU_MAX);
- SERIALIZE_ARRAY(cpuBpr, CPU_MAX);
- SERIALIZE_ARRAY(cpuHighestInt, CPU_MAX);
- SERIALIZE_ARRAY(cpuSgiActive, SGI_MAX);
- SERIALIZE_ARRAY(cpuSgiPending, SGI_MAX);
- SERIALIZE_ARRAY(cpuSgiActiveExt, CPU_MAX);
- SERIALIZE_ARRAY(cpuSgiPendingExt, CPU_MAX);
- SERIALIZE_ARRAY(cpuPpiActive, CPU_MAX);
- SERIALIZE_ARRAY(cpuPpiPending, CPU_MAX);
- SERIALIZE_SCALAR(gem5ExtensionsEnabled);
-
- for (uint32_t i=0; i < bankedRegs.size(); ++i) {
- if (!bankedRegs[i])
- continue;
- bankedRegs[i]->serializeSection(cp, csprintf("bankedRegs%i", i));
- }
-}
-
-void
-Pl390::BankedRegs::serialize(CheckpointOut &cp) const
-{
- SERIALIZE_SCALAR(intEnabled);
- SERIALIZE_SCALAR(pendingInt);
- SERIALIZE_SCALAR(activeInt);
- SERIALIZE_ARRAY(intPriority, SGI_MAX + PPI_MAX);
-}
-
-void
-Pl390::unserialize(CheckpointIn &cp)
-{
- DPRINTF(Checkpoint, "Unserializing Arm GIC\n");
-
- UNSERIALIZE_SCALAR(enabled);
- UNSERIALIZE_SCALAR(itLines);
- UNSERIALIZE_ARRAY(intEnabled, INT_BITS_MAX-1);
- UNSERIALIZE_ARRAY(pendingInt, INT_BITS_MAX-1);
- UNSERIALIZE_ARRAY(activeInt, INT_BITS_MAX-1);
- UNSERIALIZE_ARRAY(iccrpr, CPU_MAX);
- UNSERIALIZE_ARRAY(intPriority, GLOBAL_INT_LINES);
- UNSERIALIZE_ARRAY(cpuTarget, GLOBAL_INT_LINES);
- UNSERIALIZE_ARRAY(intConfig, INT_BITS_MAX * 2);
- UNSERIALIZE_ARRAY(cpuEnabled, CPU_MAX);
- UNSERIALIZE_ARRAY(cpuPriority, CPU_MAX);
- UNSERIALIZE_ARRAY(cpuBpr, CPU_MAX);
- UNSERIALIZE_ARRAY(cpuHighestInt, CPU_MAX);
- UNSERIALIZE_ARRAY(cpuSgiActive, SGI_MAX);
- UNSERIALIZE_ARRAY(cpuSgiPending, SGI_MAX);
- UNSERIALIZE_ARRAY(cpuSgiActiveExt, CPU_MAX);
- UNSERIALIZE_ARRAY(cpuSgiPendingExt, CPU_MAX);
- UNSERIALIZE_ARRAY(cpuPpiActive, CPU_MAX);
- UNSERIALIZE_ARRAY(cpuPpiPending, CPU_MAX);
-
- // Handle checkpoints from before we drained the GIC to prevent
- // in-flight interrupts.
- if (cp.entryExists(Serializable::currentSection(), "interrupt_time")) {
- Tick interrupt_time[CPU_MAX];
- UNSERIALIZE_ARRAY(interrupt_time, CPU_MAX);
-
- for (uint32_t cpu = 0; cpu < CPU_MAX; cpu++) {
- if (interrupt_time[cpu])
- schedule(postIntEvent[cpu], interrupt_time[cpu]);
- }
- }
-
- if (!UNSERIALIZE_OPT_SCALAR(gem5ExtensionsEnabled))
- gem5ExtensionsEnabled = false;
-
- for (uint32_t i=0; i < CPU_MAX; ++i) {
- ScopedCheckpointSection sec(cp, csprintf("bankedRegs%i", i));
- if (cp.sectionExists(Serializable::currentSection())) {
- getBankedRegs(i).unserialize(cp);
- }
- }
-}
-
-void
-Pl390::BankedRegs::unserialize(CheckpointIn &cp)
-{
- UNSERIALIZE_SCALAR(intEnabled);
- UNSERIALIZE_SCALAR(pendingInt);
- UNSERIALIZE_SCALAR(activeInt);
- UNSERIALIZE_ARRAY(intPriority, SGI_MAX + PPI_MAX);
-}
-
-Pl390 *
-Pl390Params::create()
-{
- return new Pl390(this);
-}
+++ /dev/null
-/*
- * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- */
-
-
-/** @file
- * Implementation of a PL390 GIC
- */
-
-#ifndef __DEV_ARM_GIC_PL390_H__
-#define __DEV_ARM_GIC_PL390_H__
-
-#include <vector>
-
-#include "base/addr_range.hh"
-#include "base/bitunion.hh"
-#include "cpu/intr_control.hh"
-#include "dev/arm/base_gic.hh"
-#include "dev/io_device.hh"
-#include "dev/platform.hh"
-#include "params/Pl390.hh"
-
-class Pl390 : public BaseGic, public BaseGicRegisters
-{
- protected:
- // distributor memory addresses
- enum {
- GICD_CTLR = 0x000, // control register
- GICD_TYPER = 0x004, // controller type
- GICD_IIDR = 0x008, // implementer id
- GICD_SGIR = 0xf00, // software generated interrupt
- GICD_PIDR0 = 0xfe0, // distributor peripheral ID0
- GICD_PIDR1 = 0xfe4, // distributor peripheral ID1
- GICD_PIDR2 = 0xfe8, // distributor peripheral ID2
- GICD_PIDR3 = 0xfec, // distributor peripheral ID3
-
- DIST_SIZE = 0x1000,
- };
-
- /**
- * As defined in:
- * "ARM Generic Interrupt Controller Architecture" version 2.0
- * "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1
- */
- static constexpr uint32_t GICD_400_PIDR_VALUE = 0x002bb490;
- static constexpr uint32_t GICD_400_IIDR_VALUE = 0x200143B;
- static constexpr uint32_t GICC_400_IIDR_VALUE = 0x202143B;
-
- static const AddrRange GICD_IGROUPR; // interrupt group (unimplemented)
- static const AddrRange GICD_ISENABLER; // interrupt set enable
- static const AddrRange GICD_ICENABLER; // interrupt clear enable
- static const AddrRange GICD_ISPENDR; // set pending interrupt
- static const AddrRange GICD_ICPENDR; // clear pending interrupt
- static const AddrRange GICD_ISACTIVER; // active bit registers
- static const AddrRange GICD_ICACTIVER; // clear bit registers
- static const AddrRange GICD_IPRIORITYR; // interrupt priority registers
- static const AddrRange GICD_ITARGETSR; // processor target registers
- static const AddrRange GICD_ICFGR; // interrupt config registers
-
- // cpu memory addresses
- enum {
- GICC_CTLR = 0x00, // CPU control register
- GICC_PMR = 0x04, // Interrupt priority mask
- GICC_BPR = 0x08, // binary point register
- GICC_IAR = 0x0C, // interrupt ack register
- GICC_EOIR = 0x10, // end of interrupt
- GICC_RPR = 0x14, // running priority
- GICC_HPPIR = 0x18, // highest pending interrupt
- GICC_ABPR = 0x1c, // aliased binary point
- GICC_APR0 = 0xd0, // active priority register 0
- GICC_APR1 = 0xd4, // active priority register 1
- GICC_APR2 = 0xd8, // active priority register 2
- GICC_APR3 = 0xdc, // active priority register 3
- GICC_IIDR = 0xfc, // cpu interface id register
- };
-
- static const int SGI_MAX = 16; // Number of Software Gen Interrupts
- static const int PPI_MAX = 16; // Number of Private Peripheral Interrupts
-
- /** Mask off SGI's when setting/clearing pending bits */
- static const int SGI_MASK = 0xFFFF0000;
-
- /** Mask for bits that config N:N mode in GICD_ICFGR's */
- static const int NN_CONFIG_MASK = 0x55555555;
-
- static const int CPU_MAX = 256; // Max number of supported CPU interfaces
- static const int SPURIOUS_INT = 1023;
- static const int INT_BITS_MAX = 32;
- static const int INT_LINES_MAX = 1020;
- static const int GLOBAL_INT_LINES = INT_LINES_MAX - SGI_MAX - PPI_MAX;
-
- /** minimum value for Binary Point Register ("IMPLEMENTATION DEFINED");
- chosen for consistency with Linux's in-kernel KVM GIC model */
- static const int GICC_BPR_MINIMUM = 2;
-
- BitUnion32(SWI)
- Bitfield<3,0> sgi_id;
- Bitfield<23,16> cpu_list;
- Bitfield<25,24> list_type;
- EndBitUnion(SWI)
-
- BitUnion32(IAR)
- Bitfield<9,0> ack_id;
- Bitfield<12,10> cpu_id;
- EndBitUnion(IAR)
-
- protected: /* Params */
- /** Address range for the distributor interface */
- const AddrRange distRange;
-
- /** Address range for the CPU interfaces */
- const AddrRange cpuRange;
-
- /** All address ranges used by this GIC */
- const AddrRangeList addrRanges;
-
- /** Latency for a distributor operation */
- const Tick distPioDelay;
-
- /** Latency for a cpu operation */
- const Tick cpuPioDelay;
-
- /** Latency for a interrupt to get to CPU */
- const Tick intLatency;
-
- protected:
- /** Gic enabled */
- bool enabled;
-
- /** Are gem5 extensions available? */
- const bool haveGem5Extensions;
-
- /** gem5 many-core extension enabled by driver */
- bool gem5ExtensionsEnabled;
-
- /** Number of itLines enabled */
- uint32_t itLines;
-
- /** Registers "banked for each connected processor" per ARM IHI0048B */
- struct BankedRegs : public Serializable {
- /** GICD_I{S,C}ENABLER0
- * interrupt enable bits for first 32 interrupts, 1b per interrupt */
- uint32_t intEnabled;
-
- /** GICD_I{S,C}PENDR0
- * interrupt pending bits for first 32 interrupts, 1b per interrupt */
- uint32_t pendingInt;
-
- /** GICD_I{S,C}ACTIVER0
- * interrupt active bits for first 32 interrupts, 1b per interrupt */
- uint32_t activeInt;
-
- /** GICD_IPRIORITYR{0..7}
- * interrupt priority for SGIs and PPIs */
- uint8_t intPriority[SGI_MAX + PPI_MAX];
-
- void serialize(CheckpointOut &cp) const override;
- void unserialize(CheckpointIn &cp) override;
-
- BankedRegs() :
- intEnabled(0), pendingInt(0), activeInt(0), intPriority {0}
- {}
- };
- std::vector<BankedRegs*> bankedRegs;
-
- BankedRegs& getBankedRegs(ContextID);
-
- /** GICD_I{S,C}ENABLER{1..31}
- * interrupt enable bits for global interrupts
- * 1b per interrupt, 32 bits per word, 31 words */
- uint32_t intEnabled[INT_BITS_MAX-1];
-
- uint32_t& getIntEnabled(ContextID ctx, uint32_t ix) {
- if (ix == 0) {
- return getBankedRegs(ctx).intEnabled;
- } else {
- return intEnabled[ix - 1];
- }
- }
-
- /** GICD_I{S,C}PENDR{1..31}
- * interrupt pending bits for global interrupts
- * 1b per interrupt, 32 bits per word, 31 words */
- uint32_t pendingInt[INT_BITS_MAX-1];
-
- uint32_t& getPendingInt(ContextID ctx, uint32_t ix) {
- assert(ix < INT_BITS_MAX);
- if (ix == 0) {
- return getBankedRegs(ctx).pendingInt;
- } else {
- return pendingInt[ix - 1];
- }
- }
-
- /** GICD_I{S,C}ACTIVER{1..31}
- * interrupt active bits for global interrupts
- * 1b per interrupt, 32 bits per word, 31 words */
- uint32_t activeInt[INT_BITS_MAX-1];
-
- uint32_t& getActiveInt(ContextID ctx, uint32_t ix) {
- assert(ix < INT_BITS_MAX);
- if (ix == 0) {
- return getBankedRegs(ctx).activeInt;
- } else {
- return activeInt[ix - 1];
- }
- }
-
- /** read only running priority register, 1 per cpu*/
- uint32_t iccrpr[CPU_MAX];
-
- /** GICD_IPRIORITYR{8..255}
- * an 8 bit priority (lower is higher priority) for each
- * of the global (not replicated per CPU) interrupts.
- */
- uint8_t intPriority[GLOBAL_INT_LINES];
-
- uint8_t& getIntPriority(ContextID ctx, uint32_t ix) {
- assert(ix < INT_LINES_MAX);
- if (ix < SGI_MAX + PPI_MAX) {
- return getBankedRegs(ctx).intPriority[ix];
- } else {
- return intPriority[ix - (SGI_MAX + PPI_MAX)];
- }
- }
-
- /** GICD_ITARGETSR{8..255}
- * an 8 bit cpu target id for each global interrupt.
- */
- uint8_t cpuTarget[GLOBAL_INT_LINES];
-
- uint8_t getCpuTarget(ContextID ctx, uint32_t ix) {
- assert(ctx < sys->numRunningContexts());
- assert(ix < INT_LINES_MAX);
- if (ix < SGI_MAX + PPI_MAX) {
- // "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each
- // field returns a value that corresponds only to the processor
- // reading the register."
- uint32_t ctx_mask;
- if (gem5ExtensionsEnabled) {
- ctx_mask = ctx;
- } else {
- // convert the CPU id number into a bit mask
- ctx_mask = power(2, ctx);
- }
- return ctx_mask;
- } else {
- return cpuTarget[ix - 32];
- }
- }
-
- /** 2 bit per interrupt signaling if it's level or edge sensitive
- * and if it is 1:N or N:N */
- uint32_t intConfig[INT_BITS_MAX*2];
-
- /** CPU enabled */
- bool cpuEnabled[CPU_MAX];
-
- /** CPU priority */
- uint8_t cpuPriority[CPU_MAX];
- uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
-
- /** Binary point registers */
- uint8_t cpuBpr[CPU_MAX];
-
- /** highest interrupt that is interrupting CPU */
- uint32_t cpuHighestInt[CPU_MAX];
-
- /** One bit per cpu per software interrupt that is pending for each possible
- * sgi source. Indexed by SGI number. Each byte in generating cpu id and
- * bits in position is destination id. e.g. 0x4 = CPU 0 generated interrupt
- * for CPU 2. */
- uint64_t cpuSgiPending[SGI_MAX];
- uint64_t cpuSgiActive[SGI_MAX];
-
- /** SGI pending arrays for gem5 GIC extension mode, which instead keeps
- * 16 SGI pending bits for each of the (large number of) CPUs.
- */
- uint32_t cpuSgiPendingExt[CPU_MAX];
- uint32_t cpuSgiActiveExt[CPU_MAX];
-
- /** One bit per private peripheral interrupt. Only upper 16 bits
- * will be used since PPI interrupts are numberred from 16 to 32 */
- uint32_t cpuPpiPending[CPU_MAX];
- uint32_t cpuPpiActive[CPU_MAX];
-
- /** software generated interrupt
- * @param data data to decode that indicates which cpus to interrupt
- */
- void softInt(ContextID ctx, SWI swi);
-
- /** See if some processor interrupt flags need to be enabled/disabled
- * @param hint which set of interrupts needs to be checked
- */
- virtual void updateIntState(int hint);
-
- /** Update the register that records priority of the highest priority
- * active interrupt*/
- void updateRunPri();
-
- /** generate a bit mask to check cpuSgi for an interrupt. */
- uint64_t genSwiMask(int cpu);
-
- int intNumToWord(int num) const { return num >> 5; }
- int intNumToBit(int num) const { return num % 32; }
-
- /**
- * Post an interrupt to a CPU with a delay
- */
- void postInt(uint32_t cpu, Tick when);
-
- /**
- * Deliver a delayed interrupt to the target CPU
- */
- void postDelayedInt(uint32_t cpu);
-
- EventFunctionWrapper *postIntEvent[CPU_MAX];
- int pendingDelayedInterrupts;
-
- public:
- typedef Pl390Params Params;
- const Params *
- params() const
- {
- return dynamic_cast<const Params *>(_params);
- }
- Pl390(const Params *p);
- ~Pl390();
-
- DrainState drain() override;
- void drainResume() override;
-
- void serialize(CheckpointOut &cp) const override;
- void unserialize(CheckpointIn &cp) override;
-
- public: /* PioDevice */
- AddrRangeList getAddrRanges() const override { return addrRanges; }
-
- /** A PIO read to the device, immediately split up into
- * readDistributor() or readCpu()
- */
- Tick read(PacketPtr pkt) override;
-
- /** A PIO read to the device, immediately split up into
- * writeDistributor() or writeCpu()
- */
- Tick write(PacketPtr pkt) override;
-
- public: /* BaseGic */
- void sendInt(uint32_t number) override;
- void clearInt(uint32_t number) override;
-
- void sendPPInt(uint32_t num, uint32_t cpu) override;
- void clearPPInt(uint32_t num, uint32_t cpu) override;
-
- protected:
- /** Handle a read to the distributor portion of the GIC
- * @param pkt packet to respond to
- */
- Tick readDistributor(PacketPtr pkt);
- uint32_t readDistributor(ContextID ctx, Addr daddr,
- size_t resp_sz);
- uint32_t readDistributor(ContextID ctx, Addr daddr) override {
- return readDistributor(ctx, daddr, 4);
- }
-
- /** Handle a read to the cpu portion of the GIC
- * @param pkt packet to respond to
- */
- Tick readCpu(PacketPtr pkt);
- uint32_t readCpu(ContextID ctx, Addr daddr) override;
-
- /** Handle a write to the distributor portion of the GIC
- * @param pkt packet to respond to
- */
- Tick writeDistributor(PacketPtr pkt);
- void writeDistributor(ContextID ctx, Addr daddr,
- uint32_t data, size_t data_sz);
- void writeDistributor(ContextID ctx, Addr daddr,
- uint32_t data) override {
- return writeDistributor(ctx, daddr, data, 4);
- }
-
- /** Handle a write to the cpu portion of the GIC
- * @param pkt packet to respond to
- */
- Tick writeCpu(PacketPtr pkt);
- void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
-};
-
-#endif //__DEV_ARM_GIC_H__
--- /dev/null
+/*
+ * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ * Prakash Ramrakhyani
+ */
+
+#include "dev/arm/gic_v2.hh"
+
+#include "base/trace.hh"
+#include "debug/Checkpoint.hh"
+#include "debug/GIC.hh"
+#include "debug/IPI.hh"
+#include "debug/Interrupt.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+
+const AddrRange GicV2::GICD_IGROUPR (0x080, 0x0ff);
+const AddrRange GicV2::GICD_ISENABLER (0x100, 0x17f);
+const AddrRange GicV2::GICD_ICENABLER (0x180, 0x1ff);
+const AddrRange GicV2::GICD_ISPENDR (0x200, 0x27f);
+const AddrRange GicV2::GICD_ICPENDR (0x280, 0x2ff);
+const AddrRange GicV2::GICD_ISACTIVER (0x300, 0x37f);
+const AddrRange GicV2::GICD_ICACTIVER (0x380, 0x3ff);
+const AddrRange GicV2::GICD_IPRIORITYR(0x400, 0x7ff);
+const AddrRange GicV2::GICD_ITARGETSR (0x800, 0xbff);
+const AddrRange GicV2::GICD_ICFGR (0xc00, 0xcff);
+
+GicV2::GicV2(const Params *p)
+ : BaseGic(p),
+ distRange(RangeSize(p->dist_addr, DIST_SIZE)),
+ cpuRange(RangeSize(p->cpu_addr, p->cpu_size)),
+ addrRanges{distRange, cpuRange},
+ distPioDelay(p->dist_pio_delay),
+ cpuPioDelay(p->cpu_pio_delay), intLatency(p->int_latency),
+ enabled(false), haveGem5Extensions(p->gem5_extensions),
+ itLines(p->it_lines),
+ intEnabled {}, pendingInt {}, activeInt {},
+ intPriority {}, cpuTarget {}, intConfig {},
+ cpuSgiPending {}, cpuSgiActive {},
+ cpuSgiPendingExt {}, cpuSgiActiveExt {},
+ cpuPpiPending {}, cpuPpiActive {},
+ pendingDelayedInterrupts(0)
+{
+ for (int x = 0; x < CPU_MAX; x++) {
+ iccrpr[x] = 0xff;
+ cpuEnabled[x] = false;
+ cpuPriority[x] = 0xff;
+ cpuBpr[x] = GICC_BPR_MINIMUM;
+ // Initialize cpu highest int
+ cpuHighestInt[x] = SPURIOUS_INT;
+ postIntEvent[x] =
+ new EventFunctionWrapper([this, x]{ postDelayedInt(x); },
+ "Post Interrupt to CPU");
+ }
+ DPRINTF(Interrupt, "cpuEnabled[0]=%d cpuEnabled[1]=%d\n", cpuEnabled[0],
+ cpuEnabled[1]);
+
+ gem5ExtensionsEnabled = false;
+}
+
+GicV2::~GicV2()
+{
+ for (int x = 0; x < CPU_MAX; x++)
+ delete postIntEvent[x];
+}
+
+Tick
+GicV2::read(PacketPtr pkt)
+{
+ const Addr addr = pkt->getAddr();
+
+ if (distRange.contains(addr))
+ return readDistributor(pkt);
+ else if (cpuRange.contains(addr))
+ return readCpu(pkt);
+ else
+ panic("Read to unknown address %#x\n", pkt->getAddr());
+}
+
+
+Tick
+GicV2::write(PacketPtr pkt)
+{
+ const Addr addr = pkt->getAddr();
+
+ if (distRange.contains(addr))
+ return writeDistributor(pkt);
+ else if (cpuRange.contains(addr))
+ return writeCpu(pkt);
+ else
+ panic("Write to unknown address %#x\n", pkt->getAddr());
+}
+
+Tick
+GicV2::readDistributor(PacketPtr pkt)
+{
+ const Addr daddr = pkt->getAddr() - distRange.start();
+ const ContextID ctx = pkt->req->contextId();
+
+ DPRINTF(GIC, "gic distributor read register %#x\n", daddr);
+
+ const uint32_t resp = readDistributor(ctx, daddr, pkt->getSize());
+
+ switch (pkt->getSize()) {
+ case 1:
+ pkt->set<uint8_t>(resp);
+ break;
+ case 2:
+ pkt->set<uint16_t>(resp);
+ break;
+ case 4:
+ pkt->set<uint32_t>(resp);
+ break;
+ default:
+ panic("Invalid size while reading Distributor regs in GIC: %d\n",
+ pkt->getSize());
+ }
+
+ pkt->makeAtomicResponse();
+ return distPioDelay;
+}
+
+uint32_t
+GicV2::readDistributor(ContextID ctx, Addr daddr, size_t resp_sz)
+{
+ if (GICD_IGROUPR.contains(daddr)) {
+ return 0; // unimplemented; RAZ (read as zero)
+ }
+
+ if (GICD_ISENABLER.contains(daddr)) {
+ uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
+ assert(ix < 32);
+ return getIntEnabled(ctx, ix);
+ }
+
+ if (GICD_ICENABLER.contains(daddr)) {
+ uint32_t ix = (daddr - GICD_ICENABLER.start()) >> 2;
+ assert(ix < 32);
+ return getIntEnabled(ctx, ix);
+ }
+
+ if (GICD_ISPENDR.contains(daddr)) {
+ uint32_t ix = (daddr - GICD_ISPENDR.start()) >> 2;
+ assert(ix < 32);
+ return getPendingInt(ctx, ix);
+ }
+
+ if (GICD_ICPENDR.contains(daddr)) {
+ uint32_t ix = (daddr - GICD_ICPENDR.start()) >> 2;
+ assert(ix < 32);
+ return getPendingInt(ctx, ix);
+ }
+
+ if (GICD_ISACTIVER.contains(daddr)) {
+ uint32_t ix = (daddr - GICD_ISACTIVER.start()) >> 2;
+ assert(ix < 32);
+ return getActiveInt(ctx, ix);
+ }
+
+ if (GICD_ICACTIVER.contains(daddr)) {
+ uint32_t ix = (daddr - GICD_ICACTIVER.start()) >> 2;
+ assert(ix < 32);
+ return getActiveInt(ctx, ix);
+ }
+
+ if (GICD_IPRIORITYR.contains(daddr)) {
+ Addr int_num = daddr - GICD_IPRIORITYR.start();
+ assert(int_num < INT_LINES_MAX);
+ DPRINTF(Interrupt, "Reading interrupt priority at int# %#x \n",
+ int_num);
+
+ switch (resp_sz) {
+ default: // will panic() after return to caller anyway
+ case 1:
+ return getIntPriority(ctx, int_num);
+ case 2:
+ assert((int_num + 1) < INT_LINES_MAX);
+ return (getIntPriority(ctx, int_num) |
+ getIntPriority(ctx, int_num+1) << 8);
+ case 4:
+ assert((int_num + 3) < INT_LINES_MAX);
+ return (getIntPriority(ctx, int_num) |
+ getIntPriority(ctx, int_num+1) << 8 |
+ getIntPriority(ctx, int_num+2) << 16 |
+ getIntPriority(ctx, int_num+3) << 24);
+ }
+ }
+
+ if (GICD_ITARGETSR.contains(daddr)) {
+ Addr int_num = daddr - GICD_ITARGETSR.start();
+ DPRINTF(GIC, "Reading processor target register for int# %#x \n",
+ int_num);
+ assert(int_num < INT_LINES_MAX);
+
+ if (resp_sz == 1) {
+ return getCpuTarget(ctx, int_num);
+ } else {
+ assert(resp_sz == 4);
+ int_num = mbits(int_num, 31, 2);
+ return (getCpuTarget(ctx, int_num) |
+ getCpuTarget(ctx, int_num+1) << 8 |
+ getCpuTarget(ctx, int_num+2) << 16 |
+ getCpuTarget(ctx, int_num+3) << 24) ;
+ }
+ }
+
+ if (GICD_ICFGR.contains(daddr)) {
+ uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2;
+ assert(ix < 64);
+ /** @todo software generated interrupts and PPIs
+ * can't be configured in some ways */
+ return intConfig[ix];
+ }
+
+ switch(daddr) {
+ case GICD_CTLR:
+ return enabled;
+ case GICD_TYPER:
+ /* The 0x100 is a made-up flag to show that gem5 extensions
+ * are available,
+ * write 0x200 to this register to enable it. */
+ return (((sys->numRunningContexts() - 1) << 5) |
+ (itLines/INT_BITS_MAX -1) |
+ (haveGem5Extensions ? 0x100 : 0x0));
+ case GICD_PIDR0:
+ //ARM defined DevID
+ return (GICD_400_PIDR_VALUE & 0xFF);
+ case GICD_PIDR1:
+ return ((GICD_400_PIDR_VALUE >> 8) & 0xFF);
+ case GICD_PIDR2:
+ return ((GICD_400_PIDR_VALUE >> 16) & 0xFF);
+ case GICD_PIDR3:
+ return ((GICD_400_PIDR_VALUE >> 24) & 0xFF);
+ case GICD_IIDR:
+ /* revision id is resorted to 1 and variant to 0*/
+ return GICD_400_IIDR_VALUE;
+ default:
+ panic("Tried to read Gic distributor at offset %#x\n", daddr);
+ break;
+ }
+}
+
+Tick
+GicV2::readCpu(PacketPtr pkt)
+{
+ const Addr daddr = pkt->getAddr() - cpuRange.start();
+
+ assert(pkt->req->hasContextId());
+ const ContextID ctx = pkt->req->contextId();
+ assert(ctx < sys->numRunningContexts());
+
+ DPRINTF(GIC, "gic cpu read register %#x cpu context: %d\n", daddr,
+ ctx);
+
+ pkt->set<uint32_t>(readCpu(ctx, daddr));
+
+ pkt->makeAtomicResponse();
+ return cpuPioDelay;
+}
+
+uint32_t
+GicV2::readCpu(ContextID ctx, Addr daddr)
+{
+ switch(daddr) {
+ case GICC_IIDR:
+ return GICC_400_IIDR_VALUE;
+ case GICC_CTLR:
+ return cpuEnabled[ctx];
+ case GICC_PMR:
+ return cpuPriority[ctx];
+ case GICC_BPR:
+ return cpuBpr[ctx];
+ case GICC_IAR:
+ if (enabled && cpuEnabled[ctx]) {
+ int active_int = cpuHighestInt[ctx];
+ IAR iar = 0;
+ iar.ack_id = active_int;
+ iar.cpu_id = 0;
+ if (active_int < SGI_MAX) {
+ // this is a software interrupt from another CPU
+ if (!gem5ExtensionsEnabled) {
+ panic_if(!cpuSgiPending[active_int],
+ "Interrupt %d active but no CPU generated it?\n",
+ active_int);
+ for (int x = 0; x < sys->numRunningContexts(); x++) {
+ // See which CPU generated the interrupt
+ uint8_t cpugen =
+ bits(cpuSgiPending[active_int], 7 + 8 * x, 8 * x);
+ if (cpugen & (1 << ctx)) {
+ iar.cpu_id = x;
+ break;
+ }
+ }
+ uint64_t sgi_num = ULL(1) << (ctx + 8 * iar.cpu_id);
+ cpuSgiActive[iar.ack_id] |= sgi_num;
+ cpuSgiPending[iar.ack_id] &= ~sgi_num;
+ } else {
+ uint64_t sgi_num = ULL(1) << iar.ack_id;
+ cpuSgiActiveExt[ctx] |= sgi_num;
+ cpuSgiPendingExt[ctx] &= ~sgi_num;
+ }
+ } else if (active_int < (SGI_MAX + PPI_MAX) ) {
+ uint32_t int_num = 1 << (cpuHighestInt[ctx] - SGI_MAX);
+ cpuPpiActive[ctx] |= int_num;
+ updateRunPri();
+ cpuPpiPending[ctx] &= ~int_num;
+
+ } else {
+ uint32_t int_num = 1 << intNumToBit(cpuHighestInt[ctx]);
+ getActiveInt(ctx, intNumToWord(cpuHighestInt[ctx])) |= int_num;
+ updateRunPri();
+ getPendingInt(ctx, intNumToWord(cpuHighestInt[ctx]))
+ &= ~int_num;
+ }
+
+ DPRINTF(Interrupt,
+ "CPU %d reading IAR.id=%d IAR.cpu=%d, iar=0x%x\n",
+ ctx, iar.ack_id, iar.cpu_id, iar);
+ cpuHighestInt[ctx] = SPURIOUS_INT;
+ updateIntState(-1);
+ platform->intrctrl->clear(ctx, ArmISA::INT_IRQ, 0);
+ return iar;
+ } else {
+ return SPURIOUS_INT;
+ }
+
+ break;
+ case GICC_RPR:
+ return iccrpr[0];
+ case GICC_HPPIR:
+ panic("Need to implement HPIR");
+ break;
+ default:
+ panic("Tried to read Gic cpu at offset %#x\n", daddr);
+ break;
+ }
+}
+
+Tick
+GicV2::writeDistributor(PacketPtr pkt)
+{
+ const Addr daddr = pkt->getAddr() - distRange.start();
+
+ assert(pkt->req->hasContextId());
+ const ContextID ctx = pkt->req->contextId();
+ const size_t data_sz = pkt->getSize();
+
+ uint32_t pkt_data M5_VAR_USED;
+ switch (data_sz)
+ {
+ case 1:
+ pkt_data = pkt->get<uint8_t>();
+ break;
+ case 2:
+ pkt_data = pkt->get<uint16_t>();
+ break;
+ case 4:
+ pkt_data = pkt->get<uint32_t>();
+ break;
+ default:
+ panic("Invalid size when writing to priority regs in Gic: %d\n",
+ data_sz);
+ }
+
+ DPRINTF(GIC, "gic distributor write register %#x size %#x value %#x \n",
+ daddr, data_sz, pkt_data);
+
+ writeDistributor(ctx, daddr, pkt_data, data_sz);
+
+ pkt->makeAtomicResponse();
+ return distPioDelay;
+}
+
+void
+GicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data,
+ size_t data_sz)
+{
+ if (GICD_IGROUPR.contains(daddr)) {
+ return; // unimplemented; WI (writes ignored)
+ }
+
+ if (GICD_ISENABLER.contains(daddr)) {
+ uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
+ assert(ix < 32);
+ getIntEnabled(ctx, ix) |= data;
+ return;
+ }
+
+ if (GICD_ICENABLER.contains(daddr)) {
+ uint32_t ix = (daddr - GICD_ICENABLER.start()) >> 2;
+ assert(ix < 32);
+ getIntEnabled(ctx, ix) &= ~data;
+ return;
+ }
+
+ if (GICD_ISPENDR.contains(daddr)) {
+ uint32_t ix = (daddr - GICD_ISPENDR.start()) >> 2;
+ auto mask = data;
+ if (ix == 0) mask &= SGI_MASK; // Don't allow SGIs to be changed
+ getPendingInt(ctx, ix) |= mask;
+ updateIntState(ix);
+ return;
+ }
+
+ if (GICD_ICPENDR.contains(daddr)) {
+ uint32_t ix = (daddr - GICD_ICPENDR.start()) >> 2;
+ auto mask = data;
+ if (ix == 0) mask &= SGI_MASK; // Don't allow SGIs to be changed
+ getPendingInt(ctx, ix) &= ~mask;
+ updateIntState(ix);
+ return;
+ }
+
+ if (GICD_ISACTIVER.contains(daddr)) {
+ uint32_t ix = (daddr - GICD_ISACTIVER.start()) >> 2;
+ getActiveInt(ctx, ix) |= data;
+ return;
+ }
+
+ if (GICD_ICACTIVER.contains(daddr)) {
+ uint32_t ix = (daddr - GICD_ICACTIVER.start()) >> 2;
+ getActiveInt(ctx, ix) &= ~data;
+ return;
+ }
+
+ if (GICD_IPRIORITYR.contains(daddr)) {
+ Addr int_num = daddr - GICD_IPRIORITYR.start();
+ switch(data_sz) {
+ case 1:
+ getIntPriority(ctx, int_num) = data;
+ break;
+ case 2: {
+ getIntPriority(ctx, int_num) = bits(data, 7, 0);
+ getIntPriority(ctx, int_num + 1) = bits(data, 15, 8);
+ break;
+ }
+ case 4: {
+ getIntPriority(ctx, int_num) = bits(data, 7, 0);
+ getIntPriority(ctx, int_num + 1) = bits(data, 15, 8);
+ getIntPriority(ctx, int_num + 2) = bits(data, 23, 16);
+ getIntPriority(ctx, int_num + 3) = bits(data, 31, 24);
+ break;
+ }
+ default:
+ panic("Invalid size when writing to priority regs in Gic: %d\n",
+ data_sz);
+ }
+
+ updateIntState(-1);
+ updateRunPri();
+ return;
+ }
+
+ if (GICD_ITARGETSR.contains(daddr)) {
+ Addr int_num = daddr - GICD_ITARGETSR.start();
+ // Interrupts 0-31 are read only
+ unsigned offset = SGI_MAX + PPI_MAX;
+ if (int_num >= offset) {
+ unsigned ix = int_num - offset; // index into cpuTarget array
+ if (data_sz == 1) {
+ cpuTarget[ix] = data & 0xff;
+ } else {
+ assert (data_sz == 4);
+ cpuTarget[ix] = bits(data, 7, 0);
+ cpuTarget[ix+1] = bits(data, 15, 8);
+ cpuTarget[ix+2] = bits(data, 23, 16);
+ cpuTarget[ix+3] = bits(data, 31, 24);
+ }
+ updateIntState(int_num >> 2);
+ }
+ return;
+ }
+
+ if (GICD_ICFGR.contains(daddr)) {
+ uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2;
+ assert(ix < INT_BITS_MAX*2);
+ intConfig[ix] = data;
+ if (data & NN_CONFIG_MASK)
+ warn("GIC N:N mode selected and not supported at this time\n");
+ return;
+ }
+
+ switch(daddr) {
+ case GICD_CTLR:
+ enabled = data;
+ DPRINTF(Interrupt, "Distributor enable flag set to = %d\n", enabled);
+ break;
+ case GICD_TYPER:
+ /* 0x200 is a made-up flag to enable gem5 extension functionality.
+ * This reg is not normally written.
+ */
+ gem5ExtensionsEnabled = (data & 0x200) && haveGem5Extensions;
+ DPRINTF(GIC, "gem5 extensions %s\n",
+ gem5ExtensionsEnabled ? "enabled" : "disabled");
+ break;
+ case GICD_SGIR:
+ softInt(ctx, data);
+ break;
+ default:
+ panic("Tried to write Gic distributor at offset %#x\n", daddr);
+ break;
+ }
+}
+
+Tick
+GicV2::writeCpu(PacketPtr pkt)
+{
+ const Addr daddr = pkt->getAddr() - cpuRange.start();
+
+ assert(pkt->req->hasContextId());
+ const ContextID ctx = pkt->req->contextId();
+ const uint32_t data = pkt->get<uint32_t>();
+
+ DPRINTF(GIC, "gic cpu write register cpu:%d %#x val: %#x\n",
+ ctx, daddr, data);
+
+ writeCpu(ctx, daddr, data);
+
+ pkt->makeAtomicResponse();
+ return cpuPioDelay;
+}
+
+void
+GicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
+{
+ switch(daddr) {
+ case GICC_CTLR:
+ cpuEnabled[ctx] = data;
+ break;
+ case GICC_PMR:
+ cpuPriority[ctx] = data;
+ break;
+ case GICC_BPR: {
+ auto bpr = data & 0x7;
+ if (bpr < GICC_BPR_MINIMUM)
+ bpr = GICC_BPR_MINIMUM;
+ cpuBpr[ctx] = bpr;
+ break;
+ }
+ case GICC_EOIR: {
+ const IAR iar = data;
+ if (iar.ack_id < SGI_MAX) {
+ // Clear out the bit that corresponds to the cleared int
+ uint64_t clr_int = ULL(1) << (ctx + 8 * iar.cpu_id);
+ if (!(cpuSgiActive[iar.ack_id] & clr_int) &&
+ !(cpuSgiActiveExt[ctx] & (1 << iar.ack_id)))
+ panic("Done handling a SGI that isn't active?\n");
+ if (gem5ExtensionsEnabled)
+ cpuSgiActiveExt[ctx] &= ~(1 << iar.ack_id);
+ else
+ cpuSgiActive[iar.ack_id] &= ~clr_int;
+ } else if (iar.ack_id < (SGI_MAX + PPI_MAX) ) {
+ uint32_t int_num = 1 << (iar.ack_id - SGI_MAX);
+ if (!(cpuPpiActive[ctx] & int_num))
+ panic("CPU %d Done handling a PPI interrupt "
+ "that isn't active?\n", ctx);
+ cpuPpiActive[ctx] &= ~int_num;
+ } else {
+ uint32_t int_num = 1 << intNumToBit(iar.ack_id);
+ if (!(getActiveInt(ctx, intNumToWord(iar.ack_id)) & int_num))
+ warn("Done handling interrupt that isn't active: %d\n",
+ intNumToBit(iar.ack_id));
+ getActiveInt(ctx, intNumToWord(iar.ack_id)) &= ~int_num;
+ }
+ updateRunPri();
+ DPRINTF(Interrupt, "CPU %d done handling intr IAR = %d from cpu %d\n",
+ ctx, iar.ack_id, iar.cpu_id);
+ break;
+ }
+ case GICC_APR0:
+ case GICC_APR1:
+ case GICC_APR2:
+ case GICC_APR3:
+ warn("GIC APRn write ignored because not implemented: %#x\n", daddr);
+ break;
+ default:
+ panic("Tried to write Gic cpu at offset %#x\n", daddr);
+ break;
+ }
+ if (cpuEnabled[ctx]) updateIntState(-1);
+}
+
+GicV2::BankedRegs&
+GicV2::getBankedRegs(ContextID ctx) {
+ if (bankedRegs.size() <= ctx)
+ bankedRegs.resize(ctx + 1);
+
+ if (!bankedRegs[ctx])
+ bankedRegs[ctx] = new BankedRegs;
+ return *bankedRegs[ctx];
+}
+
+void
+GicV2::softInt(ContextID ctx, SWI swi)
+{
+ if (gem5ExtensionsEnabled) {
+ switch (swi.list_type) {
+ case 0: {
+ // interrupt cpus specified
+ int dest = swi.cpu_list;
+ DPRINTF(IPI, "Generating softIRQ from CPU %d for CPU %d\n",
+ ctx, dest);
+ if (cpuEnabled[dest]) {
+ cpuSgiPendingExt[dest] |= (1 << swi.sgi_id);
+ DPRINTF(IPI, "SGI[%d]=%#x\n", dest,
+ cpuSgiPendingExt[dest]);
+ }
+ } break;
+ case 1: {
+ // interrupt all
+ for (int i = 0; i < sys->numContexts(); i++) {
+ DPRINTF(IPI, "Processing CPU %d\n", i);
+ if (!cpuEnabled[i])
+ continue;
+ cpuSgiPendingExt[i] |= 1 << swi.sgi_id;
+ DPRINTF(IPI, "SGI[%d]=%#x\n", swi.sgi_id,
+ cpuSgiPendingExt[i]);
+ }
+ } break;
+ case 2: {
+ // Interrupt requesting cpu only
+ DPRINTF(IPI, "Generating softIRQ from CPU %d for CPU %d\n",
+ ctx, ctx);
+ if (cpuEnabled[ctx]) {
+ cpuSgiPendingExt[ctx] |= (1 << swi.sgi_id);
+ DPRINTF(IPI, "SGI[%d]=%#x\n", ctx,
+ cpuSgiPendingExt[ctx]);
+ }
+ } break;
+ }
+ } else {
+ switch (swi.list_type) {
+ case 1:
+ // interrupt all
+ uint8_t cpu_list;
+ cpu_list = 0;
+ for (int x = 0; x < sys->numContexts(); x++)
+ cpu_list |= cpuEnabled[x] ? 1 << x : 0;
+ swi.cpu_list = cpu_list;
+ break;
+ case 2:
+ // interrupt requesting cpu only
+ swi.cpu_list = 1 << ctx;
+ break;
+ // else interrupt cpus specified
+ }
+
+ DPRINTF(IPI, "Generating softIRQ from CPU %d for %#x\n", ctx,
+ swi.cpu_list);
+ for (int i = 0; i < sys->numContexts(); i++) {
+ DPRINTF(IPI, "Processing CPU %d\n", i);
+ if (!cpuEnabled[i])
+ continue;
+ if (swi.cpu_list & (1 << i))
+ cpuSgiPending[swi.sgi_id] |= (1 << i) << (8 * ctx);
+ DPRINTF(IPI, "SGI[%d]=%#x\n", swi.sgi_id,
+ cpuSgiPending[swi.sgi_id]);
+ }
+ }
+ updateIntState(-1);
+}
+
+uint64_t
+GicV2::genSwiMask(int cpu)
+{
+ if (cpu > sys->numContexts())
+ panic("Invalid CPU ID\n");
+ return ULL(0x0101010101010101) << cpu;
+}
+
+uint8_t
+GicV2::getCpuPriority(unsigned cpu)
+{
+ // see Table 3-2 in IHI0048B.b (GICv2)
+ // mask some low-order priority bits per BPR value
+ // NB: the GIC prioritization scheme is upside down:
+ // lower values are higher priority; masking off bits
+ // actually creates a higher priority, not lower.
+ return cpuPriority[cpu] & (0xff00 >> (7 - cpuBpr[cpu]));
+}
+
+void
+GicV2::updateIntState(int hint)
+{
+ for (int cpu = 0; cpu < sys->numContexts(); cpu++) {
+ if (!cpuEnabled[cpu])
+ continue;
+
+ /*@todo use hint to do less work. */
+ int highest_int = SPURIOUS_INT;
+ // Priorities below that set in GICC_PMR can be ignored
+ uint8_t highest_pri = getCpuPriority(cpu);
+
+ // Check SGIs
+ for (int swi = 0; swi < SGI_MAX; swi++) {
+ if (!cpuSgiPending[swi] && !cpuSgiPendingExt[cpu])
+ continue;
+ if ((cpuSgiPending[swi] & genSwiMask(cpu)) ||
+ (cpuSgiPendingExt[cpu] & (1 << swi)))
+ if (highest_pri > getIntPriority(cpu, swi)) {
+ highest_pri = getIntPriority(cpu, swi);
+ highest_int = swi;
+ }
+ }
+
+ // Check PPIs
+ if (cpuPpiPending[cpu]) {
+ for (int ppi = 0; ppi < PPI_MAX; ppi++) {
+ if (cpuPpiPending[cpu] & (1 << ppi))
+ if (highest_pri > getIntPriority(cpu, SGI_MAX + ppi)) {
+ highest_pri = getIntPriority(cpu, SGI_MAX + ppi);
+ highest_int = SGI_MAX + ppi;
+ }
+ }
+ }
+
+ bool mp_sys = sys->numRunningContexts() > 1;
+ // Check other ints
+ for (int x = 0; x < (itLines/INT_BITS_MAX); x++) {
+ if (getIntEnabled(cpu, x) & getPendingInt(cpu, x)) {
+ for (int y = 0; y < INT_BITS_MAX; y++) {
+ uint32_t int_nm = x * INT_BITS_MAX + y;
+ DPRINTF(GIC, "Checking for interrupt# %d \n",int_nm);
+ /* Set current pending int as highest int for current cpu
+ if the interrupt's priority higher than current priority
+ and if current cpu is the target (for mp configs only)
+ */
+ if ((bits(getIntEnabled(cpu, x), y)
+ &bits(getPendingInt(cpu, x), y)) &&
+ (getIntPriority(cpu, int_nm) < highest_pri))
+ if ((!mp_sys) ||
+ (gem5ExtensionsEnabled
+ ? (getCpuTarget(cpu, int_nm) == cpu)
+ : (getCpuTarget(cpu, int_nm) & (1 << cpu)))) {
+ highest_pri = getIntPriority(cpu, int_nm);
+ highest_int = int_nm;
+ }
+ }
+ }
+ }
+
+ cpuHighestInt[cpu] = highest_int;
+
+ if (highest_int == SPURIOUS_INT)
+ continue;
+
+ /* @todo make this work for more than one cpu, need to handle 1:N, N:N
+ * models */
+ if (enabled && cpuEnabled[cpu] &&
+ (highest_pri < getCpuPriority(cpu)) &&
+ !(getActiveInt(cpu, intNumToWord(highest_int))
+ & (1 << intNumToBit(highest_int)))) {
+
+ DPRINTF(Interrupt, "Posting interrupt %d to cpu%d\n", highest_int,
+ cpu);
+ postInt(cpu, curTick() + intLatency);
+ }
+ }
+}
+
+void
+GicV2::updateRunPri()
+{
+ for (int cpu = 0; cpu < sys->numContexts(); cpu++) {
+ if (!cpuEnabled[cpu])
+ continue;
+ uint8_t maxPriority = 0xff;
+ for (int i = 0; i < itLines; i++) {
+ if (i < SGI_MAX) {
+ if (((cpuSgiActive[i] & genSwiMask(cpu)) ||
+ (cpuSgiActiveExt[cpu] & (1 << i))) &&
+ (getIntPriority(cpu, i) < maxPriority))
+ maxPriority = getIntPriority(cpu, i);
+ } else if (i < (SGI_MAX + PPI_MAX)) {
+ if ((cpuPpiActive[cpu] & ( 1 << (i - SGI_MAX))) &&
+ (getIntPriority(cpu, i) < maxPriority))
+ maxPriority = getIntPriority(cpu, i);
+
+ } else {
+ if (getActiveInt(cpu, intNumToWord(i))
+ & (1 << intNumToBit(i)))
+ if (getIntPriority(cpu, i) < maxPriority)
+ maxPriority = getIntPriority(cpu, i);
+ }
+ }
+ iccrpr[cpu] = maxPriority;
+ }
+}
+
+void
+GicV2::sendInt(uint32_t num)
+{
+ uint8_t target = getCpuTarget(0, num);
+ DPRINTF(Interrupt, "Received Interrupt number %d, cpuTarget %#x: \n",
+ num, target);
+ if ((target & (target - 1)) && !gem5ExtensionsEnabled)
+ panic("Multiple targets for peripheral interrupts is not supported\n");
+ panic_if(num < SGI_MAX + PPI_MAX,
+ "sentInt() must only be used for interrupts 32 and higher");
+ getPendingInt(target, intNumToWord(num)) |= 1 << intNumToBit(num);
+ updateIntState(intNumToWord(num));
+}
+
+void
+GicV2::sendPPInt(uint32_t num, uint32_t cpu)
+{
+ DPRINTF(Interrupt, "Received PPI %d, cpuTarget %#x: \n",
+ num, cpu);
+ cpuPpiPending[cpu] |= 1 << (num - SGI_MAX);
+ updateIntState(intNumToWord(num));
+}
+
+void
+GicV2::clearInt(uint32_t number)
+{
+ /* @todo assume edge triggered only at the moment. Nothing to do. */
+}
+
+void
+GicV2::clearPPInt(uint32_t num, uint32_t cpu)
+{
+ DPRINTF(Interrupt, "Clearing PPI %d, cpuTarget %#x: \n",
+ num, cpu);
+ cpuPpiPending[cpu] &= ~(1 << (num - SGI_MAX));
+ updateIntState(intNumToWord(num));
+}
+
+void
+GicV2::postInt(uint32_t cpu, Tick when)
+{
+ if (!(postIntEvent[cpu]->scheduled())) {
+ ++pendingDelayedInterrupts;
+ eventq->schedule(postIntEvent[cpu], when);
+ }
+}
+
+void
+GicV2::postDelayedInt(uint32_t cpu)
+{
+ platform->intrctrl->post(cpu, ArmISA::INT_IRQ, 0);
+ --pendingDelayedInterrupts;
+ assert(pendingDelayedInterrupts >= 0);
+ if (pendingDelayedInterrupts == 0)
+ signalDrainDone();
+}
+
+DrainState
+GicV2::drain()
+{
+ if (pendingDelayedInterrupts == 0) {
+ return DrainState::Drained;
+ } else {
+ return DrainState::Draining;
+ }
+}
+
+
+void
+GicV2::drainResume()
+{
+ // There may be pending interrupts if checkpointed from Kvm; post them.
+ updateIntState(-1);
+}
+
+void
+GicV2::serialize(CheckpointOut &cp) const
+{
+ DPRINTF(Checkpoint, "Serializing Arm GIC\n");
+
+ SERIALIZE_SCALAR(enabled);
+ SERIALIZE_SCALAR(itLines);
+ SERIALIZE_ARRAY(intEnabled, INT_BITS_MAX-1);
+ SERIALIZE_ARRAY(pendingInt, INT_BITS_MAX-1);
+ SERIALIZE_ARRAY(activeInt, INT_BITS_MAX-1);
+ SERIALIZE_ARRAY(iccrpr, CPU_MAX);
+ SERIALIZE_ARRAY(intPriority, GLOBAL_INT_LINES);
+ SERIALIZE_ARRAY(cpuTarget, GLOBAL_INT_LINES);
+ SERIALIZE_ARRAY(intConfig, INT_BITS_MAX * 2);
+ SERIALIZE_ARRAY(cpuEnabled, CPU_MAX);
+ SERIALIZE_ARRAY(cpuPriority, CPU_MAX);
+ SERIALIZE_ARRAY(cpuBpr, CPU_MAX);
+ SERIALIZE_ARRAY(cpuHighestInt, CPU_MAX);
+ SERIALIZE_ARRAY(cpuSgiActive, SGI_MAX);
+ SERIALIZE_ARRAY(cpuSgiPending, SGI_MAX);
+ SERIALIZE_ARRAY(cpuSgiActiveExt, CPU_MAX);
+ SERIALIZE_ARRAY(cpuSgiPendingExt, CPU_MAX);
+ SERIALIZE_ARRAY(cpuPpiActive, CPU_MAX);
+ SERIALIZE_ARRAY(cpuPpiPending, CPU_MAX);
+ SERIALIZE_SCALAR(gem5ExtensionsEnabled);
+
+ for (uint32_t i=0; i < bankedRegs.size(); ++i) {
+ if (!bankedRegs[i])
+ continue;
+ bankedRegs[i]->serializeSection(cp, csprintf("bankedRegs%i", i));
+ }
+}
+
+void
+GicV2::BankedRegs::serialize(CheckpointOut &cp) const
+{
+ SERIALIZE_SCALAR(intEnabled);
+ SERIALIZE_SCALAR(pendingInt);
+ SERIALIZE_SCALAR(activeInt);
+ SERIALIZE_ARRAY(intPriority, SGI_MAX + PPI_MAX);
+}
+
+void
+GicV2::unserialize(CheckpointIn &cp)
+{
+ DPRINTF(Checkpoint, "Unserializing Arm GIC\n");
+
+ UNSERIALIZE_SCALAR(enabled);
+ UNSERIALIZE_SCALAR(itLines);
+ UNSERIALIZE_ARRAY(intEnabled, INT_BITS_MAX-1);
+ UNSERIALIZE_ARRAY(pendingInt, INT_BITS_MAX-1);
+ UNSERIALIZE_ARRAY(activeInt, INT_BITS_MAX-1);
+ UNSERIALIZE_ARRAY(iccrpr, CPU_MAX);
+ UNSERIALIZE_ARRAY(intPriority, GLOBAL_INT_LINES);
+ UNSERIALIZE_ARRAY(cpuTarget, GLOBAL_INT_LINES);
+ UNSERIALIZE_ARRAY(intConfig, INT_BITS_MAX * 2);
+ UNSERIALIZE_ARRAY(cpuEnabled, CPU_MAX);
+ UNSERIALIZE_ARRAY(cpuPriority, CPU_MAX);
+ UNSERIALIZE_ARRAY(cpuBpr, CPU_MAX);
+ UNSERIALIZE_ARRAY(cpuHighestInt, CPU_MAX);
+ UNSERIALIZE_ARRAY(cpuSgiActive, SGI_MAX);
+ UNSERIALIZE_ARRAY(cpuSgiPending, SGI_MAX);
+ UNSERIALIZE_ARRAY(cpuSgiActiveExt, CPU_MAX);
+ UNSERIALIZE_ARRAY(cpuSgiPendingExt, CPU_MAX);
+ UNSERIALIZE_ARRAY(cpuPpiActive, CPU_MAX);
+ UNSERIALIZE_ARRAY(cpuPpiPending, CPU_MAX);
+
+ // Handle checkpoints from before we drained the GIC to prevent
+ // in-flight interrupts.
+ if (cp.entryExists(Serializable::currentSection(), "interrupt_time")) {
+ Tick interrupt_time[CPU_MAX];
+ UNSERIALIZE_ARRAY(interrupt_time, CPU_MAX);
+
+ for (uint32_t cpu = 0; cpu < CPU_MAX; cpu++) {
+ if (interrupt_time[cpu])
+ schedule(postIntEvent[cpu], interrupt_time[cpu]);
+ }
+ }
+
+ if (!UNSERIALIZE_OPT_SCALAR(gem5ExtensionsEnabled))
+ gem5ExtensionsEnabled = false;
+
+ for (uint32_t i=0; i < CPU_MAX; ++i) {
+ ScopedCheckpointSection sec(cp, csprintf("bankedRegs%i", i));
+ if (cp.sectionExists(Serializable::currentSection())) {
+ getBankedRegs(i).unserialize(cp);
+ }
+ }
+}
+
+void
+GicV2::BankedRegs::unserialize(CheckpointIn &cp)
+{
+ UNSERIALIZE_SCALAR(intEnabled);
+ UNSERIALIZE_SCALAR(pendingInt);
+ UNSERIALIZE_SCALAR(activeInt);
+ UNSERIALIZE_ARRAY(intPriority, SGI_MAX + PPI_MAX);
+}
+
+GicV2 *
+GicV2Params::create()
+{
+ return new GicV2(this);
+}
--- /dev/null
+/*
+ * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+
+/** @file
+ * Implementation of a GICv2
+ */
+
+#ifndef __DEV_ARM_GICV2_H__
+#define __DEV_ARM_GICV2_H__
+
+#include <vector>
+
+#include "base/addr_range.hh"
+#include "base/bitunion.hh"
+#include "cpu/intr_control.hh"
+#include "dev/arm/base_gic.hh"
+#include "dev/io_device.hh"
+#include "dev/platform.hh"
+#include "params/GicV2.hh"
+
+class GicV2 : public BaseGic, public BaseGicRegisters
+{
+ protected:
+ // distributor memory addresses
+ enum {
+ GICD_CTLR = 0x000, // control register
+ GICD_TYPER = 0x004, // controller type
+ GICD_IIDR = 0x008, // implementer id
+ GICD_SGIR = 0xf00, // software generated interrupt
+ GICD_PIDR0 = 0xfe0, // distributor peripheral ID0
+ GICD_PIDR1 = 0xfe4, // distributor peripheral ID1
+ GICD_PIDR2 = 0xfe8, // distributor peripheral ID2
+ GICD_PIDR3 = 0xfec, // distributor peripheral ID3
+
+ DIST_SIZE = 0x1000,
+ };
+
+ /**
+ * As defined in:
+ * "ARM Generic Interrupt Controller Architecture" version 2.0
+ * "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1
+ */
+ static constexpr uint32_t GICD_400_PIDR_VALUE = 0x002bb490;
+ static constexpr uint32_t GICD_400_IIDR_VALUE = 0x200143B;
+ static constexpr uint32_t GICC_400_IIDR_VALUE = 0x202143B;
+
+ static const AddrRange GICD_IGROUPR; // interrupt group (unimplemented)
+ static const AddrRange GICD_ISENABLER; // interrupt set enable
+ static const AddrRange GICD_ICENABLER; // interrupt clear enable
+ static const AddrRange GICD_ISPENDR; // set pending interrupt
+ static const AddrRange GICD_ICPENDR; // clear pending interrupt
+ static const AddrRange GICD_ISACTIVER; // active bit registers
+ static const AddrRange GICD_ICACTIVER; // clear bit registers
+ static const AddrRange GICD_IPRIORITYR; // interrupt priority registers
+ static const AddrRange GICD_ITARGETSR; // processor target registers
+ static const AddrRange GICD_ICFGR; // interrupt config registers
+
+ // cpu memory addresses
+ enum {
+ GICC_CTLR = 0x00, // CPU control register
+ GICC_PMR = 0x04, // Interrupt priority mask
+ GICC_BPR = 0x08, // binary point register
+ GICC_IAR = 0x0C, // interrupt ack register
+ GICC_EOIR = 0x10, // end of interrupt
+ GICC_RPR = 0x14, // running priority
+ GICC_HPPIR = 0x18, // highest pending interrupt
+ GICC_ABPR = 0x1c, // aliased binary point
+ GICC_APR0 = 0xd0, // active priority register 0
+ GICC_APR1 = 0xd4, // active priority register 1
+ GICC_APR2 = 0xd8, // active priority register 2
+ GICC_APR3 = 0xdc, // active priority register 3
+ GICC_IIDR = 0xfc, // cpu interface id register
+ };
+
+ static const int SGI_MAX = 16; // Number of Software Gen Interrupts
+ static const int PPI_MAX = 16; // Number of Private Peripheral Interrupts
+
+ /** Mask off SGI's when setting/clearing pending bits */
+ static const int SGI_MASK = 0xFFFF0000;
+
+ /** Mask for bits that config N:N mode in GICD_ICFGR's */
+ static const int NN_CONFIG_MASK = 0x55555555;
+
+ static const int CPU_MAX = 256; // Max number of supported CPU interfaces
+ static const int SPURIOUS_INT = 1023;
+ static const int INT_BITS_MAX = 32;
+ static const int INT_LINES_MAX = 1020;
+ static const int GLOBAL_INT_LINES = INT_LINES_MAX - SGI_MAX - PPI_MAX;
+
+ /** minimum value for Binary Point Register ("IMPLEMENTATION DEFINED");
+ chosen for consistency with Linux's in-kernel KVM GIC model */
+ static const int GICC_BPR_MINIMUM = 2;
+
+ BitUnion32(SWI)
+ Bitfield<3,0> sgi_id;
+ Bitfield<23,16> cpu_list;
+ Bitfield<25,24> list_type;
+ EndBitUnion(SWI)
+
+ BitUnion32(IAR)
+ Bitfield<9,0> ack_id;
+ Bitfield<12,10> cpu_id;
+ EndBitUnion(IAR)
+
+ protected: /* Params */
+ /** Address range for the distributor interface */
+ const AddrRange distRange;
+
+ /** Address range for the CPU interfaces */
+ const AddrRange cpuRange;
+
+ /** All address ranges used by this GIC */
+ const AddrRangeList addrRanges;
+
+ /** Latency for a distributor operation */
+ const Tick distPioDelay;
+
+ /** Latency for a cpu operation */
+ const Tick cpuPioDelay;
+
+ /** Latency for a interrupt to get to CPU */
+ const Tick intLatency;
+
+ protected:
+ /** Gic enabled */
+ bool enabled;
+
+ /** Are gem5 extensions available? */
+ const bool haveGem5Extensions;
+
+ /** gem5 many-core extension enabled by driver */
+ bool gem5ExtensionsEnabled;
+
+ /** Number of itLines enabled */
+ uint32_t itLines;
+
+ /** Registers "banked for each connected processor" per ARM IHI0048B */
+ struct BankedRegs : public Serializable {
+ /** GICD_I{S,C}ENABLER0
+ * interrupt enable bits for first 32 interrupts, 1b per interrupt */
+ uint32_t intEnabled;
+
+ /** GICD_I{S,C}PENDR0
+ * interrupt pending bits for first 32 interrupts, 1b per interrupt */
+ uint32_t pendingInt;
+
+ /** GICD_I{S,C}ACTIVER0
+ * interrupt active bits for first 32 interrupts, 1b per interrupt */
+ uint32_t activeInt;
+
+ /** GICD_IPRIORITYR{0..7}
+ * interrupt priority for SGIs and PPIs */
+ uint8_t intPriority[SGI_MAX + PPI_MAX];
+
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
+
+ BankedRegs() :
+ intEnabled(0), pendingInt(0), activeInt(0), intPriority {0}
+ {}
+ };
+ std::vector<BankedRegs*> bankedRegs;
+
+ BankedRegs& getBankedRegs(ContextID);
+
+ /** GICD_I{S,C}ENABLER{1..31}
+ * interrupt enable bits for global interrupts
+ * 1b per interrupt, 32 bits per word, 31 words */
+ uint32_t intEnabled[INT_BITS_MAX-1];
+
+ uint32_t& getIntEnabled(ContextID ctx, uint32_t ix) {
+ if (ix == 0) {
+ return getBankedRegs(ctx).intEnabled;
+ } else {
+ return intEnabled[ix - 1];
+ }
+ }
+
+ /** GICD_I{S,C}PENDR{1..31}
+ * interrupt pending bits for global interrupts
+ * 1b per interrupt, 32 bits per word, 31 words */
+ uint32_t pendingInt[INT_BITS_MAX-1];
+
+ uint32_t& getPendingInt(ContextID ctx, uint32_t ix) {
+ assert(ix < INT_BITS_MAX);
+ if (ix == 0) {
+ return getBankedRegs(ctx).pendingInt;
+ } else {
+ return pendingInt[ix - 1];
+ }
+ }
+
+ /** GICD_I{S,C}ACTIVER{1..31}
+ * interrupt active bits for global interrupts
+ * 1b per interrupt, 32 bits per word, 31 words */
+ uint32_t activeInt[INT_BITS_MAX-1];
+
+ uint32_t& getActiveInt(ContextID ctx, uint32_t ix) {
+ assert(ix < INT_BITS_MAX);
+ if (ix == 0) {
+ return getBankedRegs(ctx).activeInt;
+ } else {
+ return activeInt[ix - 1];
+ }
+ }
+
+ /** read only running priority register, 1 per cpu*/
+ uint32_t iccrpr[CPU_MAX];
+
+ /** GICD_IPRIORITYR{8..255}
+ * an 8 bit priority (lower is higher priority) for each
+ * of the global (not replicated per CPU) interrupts.
+ */
+ uint8_t intPriority[GLOBAL_INT_LINES];
+
+ uint8_t& getIntPriority(ContextID ctx, uint32_t ix) {
+ assert(ix < INT_LINES_MAX);
+ if (ix < SGI_MAX + PPI_MAX) {
+ return getBankedRegs(ctx).intPriority[ix];
+ } else {
+ return intPriority[ix - (SGI_MAX + PPI_MAX)];
+ }
+ }
+
+ /** GICD_ITARGETSR{8..255}
+ * an 8 bit cpu target id for each global interrupt.
+ */
+ uint8_t cpuTarget[GLOBAL_INT_LINES];
+
+ uint8_t getCpuTarget(ContextID ctx, uint32_t ix) {
+ assert(ctx < sys->numRunningContexts());
+ assert(ix < INT_LINES_MAX);
+ if (ix < SGI_MAX + PPI_MAX) {
+ // "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each
+ // field returns a value that corresponds only to the processor
+ // reading the register."
+ uint32_t ctx_mask;
+ if (gem5ExtensionsEnabled) {
+ ctx_mask = ctx;
+ } else {
+ // convert the CPU id number into a bit mask
+ ctx_mask = power(2, ctx);
+ }
+ return ctx_mask;
+ } else {
+ return cpuTarget[ix - 32];
+ }
+ }
+
+ /** 2 bit per interrupt signaling if it's level or edge sensitive
+ * and if it is 1:N or N:N */
+ uint32_t intConfig[INT_BITS_MAX*2];
+
+ /** CPU enabled */
+ bool cpuEnabled[CPU_MAX];
+
+ /** CPU priority */
+ uint8_t cpuPriority[CPU_MAX];
+ uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
+
+ /** Binary point registers */
+ uint8_t cpuBpr[CPU_MAX];
+
+ /** highest interrupt that is interrupting CPU */
+ uint32_t cpuHighestInt[CPU_MAX];
+
+ /** One bit per cpu per software interrupt that is pending for each
+ * possible sgi source. Indexed by SGI number. Each byte in generating cpu
+ * id and bits in position is destination id. e.g. 0x4 = CPU 0 generated
+ * interrupt for CPU 2. */
+ uint64_t cpuSgiPending[SGI_MAX];
+ uint64_t cpuSgiActive[SGI_MAX];
+
+ /** SGI pending arrays for gem5 GIC extension mode, which instead keeps
+ * 16 SGI pending bits for each of the (large number of) CPUs.
+ */
+ uint32_t cpuSgiPendingExt[CPU_MAX];
+ uint32_t cpuSgiActiveExt[CPU_MAX];
+
+ /** One bit per private peripheral interrupt. Only upper 16 bits
+ * will be used since PPI interrupts are numberred from 16 to 32 */
+ uint32_t cpuPpiPending[CPU_MAX];
+ uint32_t cpuPpiActive[CPU_MAX];
+
+ /** software generated interrupt
+ * @param data data to decode that indicates which cpus to interrupt
+ */
+ void softInt(ContextID ctx, SWI swi);
+
+ /** See if some processor interrupt flags need to be enabled/disabled
+ * @param hint which set of interrupts needs to be checked
+ */
+ virtual void updateIntState(int hint);
+
+ /** Update the register that records priority of the highest priority
+ * active interrupt*/
+ void updateRunPri();
+
+ /** generate a bit mask to check cpuSgi for an interrupt. */
+ uint64_t genSwiMask(int cpu);
+
+ int intNumToWord(int num) const { return num >> 5; }
+ int intNumToBit(int num) const { return num % 32; }
+
+ /**
+ * Post an interrupt to a CPU with a delay
+ */
+ void postInt(uint32_t cpu, Tick when);
+
+ /**
+ * Deliver a delayed interrupt to the target CPU
+ */
+ void postDelayedInt(uint32_t cpu);
+
+ EventFunctionWrapper *postIntEvent[CPU_MAX];
+ int pendingDelayedInterrupts;
+
+ public:
+ typedef GicV2Params Params;
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
+ GicV2(const Params *p);
+ ~GicV2();
+
+ DrainState drain() override;
+ void drainResume() override;
+
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
+
+ public: /* PioDevice */
+ AddrRangeList getAddrRanges() const override { return addrRanges; }
+
+ /** A PIO read to the device, immediately split up into
+ * readDistributor() or readCpu()
+ */
+ Tick read(PacketPtr pkt) override;
+
+ /** A PIO read to the device, immediately split up into
+ * writeDistributor() or writeCpu()
+ */
+ Tick write(PacketPtr pkt) override;
+
+ public: /* BaseGic */
+ void sendInt(uint32_t number) override;
+ void clearInt(uint32_t number) override;
+
+ void sendPPInt(uint32_t num, uint32_t cpu) override;
+ void clearPPInt(uint32_t num, uint32_t cpu) override;
+
+ protected:
+ /** Handle a read to the distributor portion of the GIC
+ * @param pkt packet to respond to
+ */
+ Tick readDistributor(PacketPtr pkt);
+ uint32_t readDistributor(ContextID ctx, Addr daddr,
+ size_t resp_sz);
+ uint32_t readDistributor(ContextID ctx, Addr daddr) override {
+ return readDistributor(ctx, daddr, 4);
+ }
+
+ /** Handle a read to the cpu portion of the GIC
+ * @param pkt packet to respond to
+ */
+ Tick readCpu(PacketPtr pkt);
+ uint32_t readCpu(ContextID ctx, Addr daddr) override;
+
+ /** Handle a write to the distributor portion of the GIC
+ * @param pkt packet to respond to
+ */
+ Tick writeDistributor(PacketPtr pkt);
+ void writeDistributor(ContextID ctx, Addr daddr,
+ uint32_t data, size_t data_sz);
+ void writeDistributor(ContextID ctx, Addr daddr,
+ uint32_t data) override {
+ return writeDistributor(ctx, daddr, data, 4);
+ }
+
+ /** Handle a write to the cpu portion of the GIC
+ * @param pkt packet to respond to
+ */
+ Tick writeCpu(PacketPtr pkt);
+ void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
+};
+
+#endif //__DEV_ARM_GIC_H__
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