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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 5aadeb1f1b0dabb849877903bfcd8df1462345c5..d7963493a03aec85146c262544eaee0b31582a1a 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -1020,13 +1020,19 @@ with the proposed microarchitecture: the differences however are key.
   being a bit light on L1 Cache, in favour of large ALUs and proximity
   to Memory, and require a modest amount of "helper" assistance with
   their Virtual Memory Management.
-* ZOLC has the transition points where PEs may take over from the CPU
-  actually embedded into the binary, and there is accompanying
-  hardware-level assistance at the ISA level.  GPUs, which have to
-  work with a wide range of commidity CPUs, cannot in any way expect
+* The proposed architecture has the markup points emdedded into the
+  binary programs
+  where PEs may take over from the CPU, and there is accompanying
+  (planned) hardware-level assistance at the ISA level.  GPUs, which have to
+  work with a wide range of commodity CPUs, cannot in any way expect
   ARM or Intel to add support for GPU Task Scheduling directly into
   the ARM or x86 ISAs!
 
+On this last point it is crucial to note that SVP64 began its inspration
+from a Hybrid CPU-GPU-VPU paradigm (like ICubeCorp's IC3128) and
+consequently has versatility that the separate specialisation of both
+GPU and CPU architectures lack.
+
 **Roadmap summary of Advanced SVP64**
 
 The future direction for SVP64, then, is: