lib.cdc: in AsyncFFSynchronizer(), rename domain= to

 o_domain=.

This is for consistency with other synchronizers.

Fixes #467.

diff --git a/nmigen/lib/cdc.py b/nmigen/lib/cdc.py
index fb62390dbc84610aa474d47d5cd50bdd229e43d4..5a0e9d85213d757b2f6335982ad16abaf50e955e 100644 (file)
--- a/nmigen/lib/cdc.py
+++ b/nmigen/lib/cdc.py
@@ -109,7 +109,7 @@ class AsyncFFSynchronizer(Elaboratable):
         Asynchronous input signal, to be synchronized.
     o : Signal(1), out
         Synchronously released output signal.
-    domain : str
+    o_domain : str
         Name of clock domain to synchronize to.
     stages : int, >=2
         Number of synchronization stages between input and output. The lowest safe number is 2,
@@ -117,13 +117,13 @@ class AsyncFFSynchronizer(Elaboratable):
     async_edge : str
         The edge of the input signal which causes the output to be set. Must be one of "pos" or "neg".
     """
-    def __init__(self, i, o, *, domain="sync", stages=2, async_edge="pos", max_input_delay=None):
+    def __init__(self, i, o, *, o_domain="sync", stages=2, async_edge="pos", max_input_delay=None):
         _check_stages(stages)
 
         self.i = i
         self.o = o
 
-        self._domain = domain
+        self._o_domain = o_domain
         self._stages = stages
 
         if async_edge not in ("pos", "neg"):
@@ -156,7 +156,7 @@ class AsyncFFSynchronizer(Elaboratable):
             m.d.comb += ResetSignal("async_ff").eq(~self.i)
 
         m.d.comb += [
-            ClockSignal("async_ff").eq(ClockSignal(self._domain)),
+            ClockSignal("async_ff").eq(ClockSignal(self._o_domain)),
             self.o.eq(flops[-1])
         ]
 
@@ -204,7 +204,7 @@ class ResetSynchronizer(Elaboratable):
         self._max_input_delay = max_input_delay
 
     def elaborate(self, platform):
-        return AsyncFFSynchronizer(self.arst, ResetSignal(self._domain), domain=self._domain,
+        return AsyncFFSynchronizer(self.arst, ResetSignal(self._domain), o_domain=self._domain,
                 stages=self._stages, max_input_delay=self._max_input_delay)
 
 

diff --git a/nmigen/lib/fifo.py b/nmigen/lib/fifo.py
index d94012f17e834cedfada9820d6ef79f55a80e922..fa5b265cfb0e0829e559fb120713216155496051 100644 (file)
--- a/nmigen/lib/fifo.py
+++ b/nmigen/lib/fifo.py
@@ -413,10 +413,10 @@ class AsyncFIFO(Elaboratable, FIFOInterface):
         # full discussion.
         w_rst = ResetSignal(domain=self._w_domain, allow_reset_less=True)
         r_rst = Signal()
-        
+
         # Async-set-sync-release synchronizer avoids CDC hazards
         rst_cdc = m.submodules.rst_cdc = \
-            AsyncFFSynchronizer(w_rst, r_rst, domain=self._r_domain)
+            AsyncFFSynchronizer(w_rst, r_rst, o_domain=self._r_domain)
 
         # Decode Gray code counter synchronized from write domain to overwrite binary
         # counter in read domain.

diff --git a/nmigen/test/test_lib_cdc.py b/nmigen/test/test_lib_cdc.py
index 5a169ac430db4c87362d251735cd8223f4b87b3e..3647bfac7ea39ceb056790ae722009e89081a787 100644 (file)
--- a/nmigen/test/test_lib_cdc.py
+++ b/nmigen/test/test_lib_cdc.py
@@ -66,7 +66,7 @@ class AsyncFFSynchronizerTestCase(FHDLTestCase):
     def test_edge_wrong(self):
         with self.assertRaisesRegex(ValueError,
                 r"^AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', not 'xxx'$"):
-            AsyncFFSynchronizer(Signal(), Signal(), domain="sync", async_edge="xxx")
+            AsyncFFSynchronizer(Signal(), Signal(), o_domain="sync", async_edge="xxx")
 
     def test_pos_edge(self):
         i = Signal()

diff --git a/nmigen/vendor/intel.py b/nmigen/vendor/intel.py
index 19a54daa70a1e025ad3ce40255eabf54e895aa78..92157f6ef783013a97347b59b6feab5771cbabe8 100644 (file)
--- a/nmigen/vendor/intel.py
+++ b/nmigen/vendor/intel.py
@@ -402,7 +402,7 @@ class IntelPlatform(TemplatedPlatform):
         if async_ff_sync._edge == "pos":
             m.submodules += Instance("altera_std_synchronizer",
                 p_depth=async_ff_sync._stages,
-                i_clk=ClockSignal(async_ff_sync._domain),
+                i_clk=ClockSignal(async_ff_sync._o_domain),
                 i_reset_n=~async_ff_sync.i,
                 i_din=Const(1),
                 o_dout=sync_output,
@@ -410,7 +410,7 @@ class IntelPlatform(TemplatedPlatform):
         else:
             m.submodules += Instance("altera_std_synchronizer",
                 p_depth=async_ff_sync._stages,
-                i_clk=ClockSignal(async_ff_sync._domain),
+                i_clk=ClockSignal(async_ff_sync._o_domain),
                 i_reset_n=async_ff_sync.i,
                 i_din=Const(1),
                 o_dout=sync_output,

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 800b5286e0d59113a522a8ca6a9a6678f6d0edb3..5c35469dff8ce377f214bd3ab24e12bc5335bbff 100644 (file)
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -613,7 +613,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
             m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
 
         m.d.comb += [
-            ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
+            ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._o_domain)),
             async_ff_sync.o.eq(flops[-1])
         ]
 

diff --git a/nmigen/vendor/xilinx_spartan_3_6.py b/nmigen/vendor/xilinx_spartan_3_6.py
index 745dd54ccbfe98d9ef701d7360fd23b26dd3766c..9b10733b2653a51f30d41a443da7b8400e348421 100644 (file)
--- a/nmigen/vendor/xilinx_spartan_3_6.py
+++ b/nmigen/vendor/xilinx_spartan_3_6.py
@@ -456,7 +456,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
             m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
 
         m.d.comb += [
-            ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
+            ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._o_domain)),
             async_ff_sync.o.eq(flops[-1])
         ]
 

diff --git a/nmigen/vendor/xilinx_ultrascale.py b/nmigen/vendor/xilinx_ultrascale.py
index 3a74d54e37298f5b8f642e2bea4eb1ec05619577..937b346fa8b67d1bda697e5c1a41deb19a27bc8a 100644 (file)
--- a/nmigen/vendor/xilinx_ultrascale.py
+++ b/nmigen/vendor/xilinx_ultrascale.py
@@ -429,7 +429,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
             m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
 
         m.d.comb += [
-            ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
+            ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._o_domain)),
             async_ff_sync.o.eq(flops[-1])
         ]