{R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
+ {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
+ {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
{R_028350_SX_MISC, 0, 0, 0},
{R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
{R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
{R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
{R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
{R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
- {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
- {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
+ {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
{R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
{R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
{R_028408_VGT_INDX_OFFSET, 0, 0, 0},
{R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
+ {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
{R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
{R_028414_CB_BLEND_RED, 0, 0, 0},
{R_028418_CB_BLEND_GREEN, 0, 0, 0},
{R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
+ {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
+ {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
{R_028350_SX_MISC, 0, 0, 0},
{R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
{R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
{R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
{R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
{R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
- {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
- {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
+ {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
{R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
{R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
{R_028408_VGT_INDX_OFFSET, 0, 0, 0},
{R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
+ {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
{R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
{R_028414_CB_BLEND_RED, 0, 0, 0},
{R_028418_CB_BLEND_GREEN, 0, 0, 0},