Update CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index e74af6b657193ed16d8f660453b3ce1854c4fbd8..13cfb812b7204ec0ece9cb6e3aadc25698272818 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -17,12 +17,13 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "rename -src"
     - Added "equiv_opt" pass
     - Added "read_aiger" frontend
+    - Added "shregmap -tech xilinx"
     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
     - Added "synth_xilinx -abc9" (experimental)
     - Added "synth_ice40 -abc9" (experimental)
     - Added "synth -abc9" (experimental)
-    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
-    - "synth_xilinx" to now infer wide multiplexers
+    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
+    - "synth_xilinx" to now infer wide multiplexers (-nomux to disable)
 
 
 Yosys 0.7 .. Yosys 0.8