from misoclib.com.uart.phy.serial import UARTPHYSerial
+
class UARTPads:
def __init__(self):
self.rx = Signal()
self.tx = Signal()
+
class UARTMux(Module):
def __init__(self, pads):
self.sel = Signal(max=2)
pads.tx.eq(self.bridge_pads.tx)
)
+
class LiteScopeUART2WB(Module, AutoCSR):
cmds = {
"write" : 0x01,
from migen.flow.plumbing import Buffer
from migen.fhdl.specials import Memory
+
def data_layout(dw):
return [("data", dw, DIR_M_TO_S)]
+
def hit_layout():
return [("hit", 1, DIR_M_TO_S)]
from misoclib.tools.litescope.common import *
+
class LiteScopeTermUnit(Module):
def __init__(self, dw):
self.dw = dw
sink.ack.eq(source.ack)
]
+
class LiteScopeTerm(LiteScopeTermUnit, AutoCSR):
def __init__(self, dw):
LiteScopeTermUnit.__init__(self, dw)
self.mask.eq(self._mask.storage)
]
+
class LiteScopeRangeDetectorUnit(Module):
def __init__(self, dw):
self.dw = dw
sink.ack.eq(source.ack)
]
+
class LiteScopeRangeDetector(LiteScopeRangeDetectorUnit, AutoCSR):
def __init__(self, dw):
LiteScopeRangeDetectorUnit.__init__(self, dw)
self.high.eq(self._high.storage)
]
+
class LiteScopeEdgeDetectorUnit(Module):
def __init__(self, dw):
self.dw = dw
source.hit.eq(rising | falling | both)
]
+
class LiteScopeEdgeDetector(LiteScopeEdgeDetectorUnit, AutoCSR):
def __init__(self, dw):
LiteScopeEdgeDetectorUnit.__init__(self, dw)
from misoclib.tools.litescope.common import *
from migen.flow.plumbing import Buffer
+
class LiteScopeSubSamplerUnit(Module):
def __init__(self, dw):
self.sink = sink = Sink(data_layout(dw))
self.counter.reset.eq(source.stb & source.ack & done)
]
+
class LiteScopeSubSampler(LiteScopeSubSamplerUnit, AutoCSR):
def __init__(self, dw):
LiteScopeSubSamplerUnit.__init__(self, dw)
###
self.comb += self.value.eq(self._value.storage)
+
class LiteScopeRunLengthEncoderUnit(Module):
def __init__(self, dw, length):
self.dw = dw
)
)
+
class LiteScopeRunLengthEncoder(LiteScopeRunLengthEncoderUnit, AutoCSR):
def __init__(self, dw, length=1024):
LiteScopeRunLengthEncoderUnit.__init__(self, dw, length)
###
self.comb += self.enable.eq(self._enable.storage & self.external_enable)
+
class LiteScopeRecorderUnit(Module):
def __init__(self, dw, depth):
self.dw = dw
If(~fifo.sink.ack | (fifo.fifo.level >= self.length), NextState("IDLE"))
)
+
class LiteScopeRecorder(LiteScopeRecorderUnit, AutoCSR):
def __init__(self, dw, depth):
LiteScopeRecorderUnit.__init__(self, dw, depth)
from misoclib.tools.litescope.common import *
+
class LiteScopeSumUnit(Module, AutoCSR):
def __init__(self, ports):
self.sinks = sinks = [Sink(hit_layout()) for i in range(ports)]
for i, sink in enumerate(sinks):
self.comb += sink.ack.eq(sink.stb & source.ack)
+
class LiteScopeSum(LiteScopeSumUnit, AutoCSR):
def __init__(self, ports):
LiteScopeSumUnit.__init__(self, ports)
self.prog_dat.eq(self._prog_dat.storage)
]
+
class LiteScopeTrigger(Module, AutoCSR):
def __init__(self, dw):
self.dw = dw
from misoclib.soc import cpuif
from misoclib.tools.litescope.common import *
+
def _import(default, name):
return importlib.import_module(default + "." + name)
+
def _get_args():
parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
description="""\
from misoclib.tools.litescope.frontend.la import LiteScopeLA
from misoclib.tools.litescope.core.port import LiteScopeTerm
+
class LiteScopeSoC(SoC, AutoCSR):
csr_map = {
"io": 16,
#!/usr/bin/env python3
import argparse, importlib
+
def _get_args():
parser = argparse.ArgumentParser()
parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use")
import time
from misoclib.tools.litescope.host.driver.io import LiteScopeIODriver
+
def led_anim0(io):
for i in range(10):
io.write(0xA5)
io.write(0x5A)
time.sleep(0.1)
+
def led_anim1(io):
for j in range(4):
#Led <<
time.sleep(i*i*0.0020)
led_data = (led_data>>1)
+
def main(wb):
io = LiteScopeIODriver(wb.regs, "io")
wb.open()
from misoclib.tools.litescope.host.driver.la import LiteScopeLADriver
+
def main(wb):
wb.open()
###
from misoclib.tools.litescope.common import *
+
class LiteScopeIO(Module, AutoCSR):
def __init__(self, dw):
self.dw = dw
from mibuild.tools import write_to_file
+
class LiteScopeLA(Module, AutoCSR):
def __init__(self, layout, depth, clk_domain="sys",
with_input_buffer=False,
from liteeth.test.model.etherbone import *
+
class LiteScopeEtherboneDriver:
def __init__(self, ip_address, udp_port=20000, addrmap=None, busword=8, debug=False):
self.ip_address = ip_address
from misoclib.tools.litescope.host.dump import *
from misoclib.tools.litescope.host.driver.truthtable import *
+
class LiteScopeLADriver():
def __init__(self, regs, name, config_csv=None, clk_freq=None, debug=False):
self.regs = regs
import csv
+
class MappedReg:
def __init__(self, readfn, writefn, name, addr, length, busword, mode):
self.readfn = readfn
datas.append((value >> ((self.length-1-i)*self.busword)) & (2**self.busword-1))
self.writefn(self.addr, datas)
+
class MappedRegs:
def __init__(self, d):
self.d = d
pass
raise KeyError("No such register " + attr)
-def build_map(addrmap, busword, readfn, writefn):
+
+def build_map(addrmap, busword, readfn, writefn):
csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
d = {}
for item in csv_reader:
import re
import sys
+
def is_number(x):
try:
_ = float(x)
return False
return True
+
def remove_numbers(seq):
return [x for x in seq if not is_number(x)]
+
def remove_duplicates(seq):
seen = set()
seen_add = seen.add
return [x for x in seq if x not in seen and not seen_add(x)]
+
def get_operands(s):
operands = re.findall("[A-z0-9_]+", s)
operands = remove_duplicates(operands)
operands = remove_numbers(operands)
return sorted(operands)
+
def gen_truth_table(s):
operands = get_operands(s)
width = len(operands)
truth_table.append(eval(s) != 0)
return truth_table
+
def main():
print(gen_truth_table("(A&B&C)|D"))
from struct import *
from misoclib.tools.litescope.host.driver.reg import *
+
def write_b(uart, data):
uart.write(pack('B',data))
+
class LiteScopeUARTDriver:
cmds = {
"write" : 0x01,
d=d>>1
return b.zfill(nb)
+
def get_bits(values, low, high=None):
r = []
if high is None:
r.append(t)
return r
+
class Dat(list):
def __init__(self, width):
self.width = width
last_data = data
return datas
+
class Var:
def __init__(self, name, width, values=[], type="wire", default="x"):
self.type = type
return r
return r
+
class Dump:
def __init__(self):
self.vars = []
from misoclib.tools.litescope.host.dump import *
+
class CSVDump(Dump):
def __init__(self, init_dump=None):
Dump.__init__(self)
from misoclib.tools.litescope.host.dump import *
+
class PythonDump(Dump):
def __init__(self, init_dump=None):
Dump.__init__(self)
from misoclib.tools.litescope.host.dump import *
+
class SigrokDump(Dump):
def __init__(self, init_dump=None, samplerate=50000000):
Dump.__init__(self)
import datetime
from misoclib.tools.litescope.host.dump import *
+
class VCDDump(Dump):
def __init__(self, init_dump=None, timescale="1ps", comment=""):
Dump.__init__(self)
projects / litex.git / commitdiff