Remove setaddr for submodule instanciation

diff --git a/gram/dfii.py b/gram/dfii.py
index 3436e33a92c02b3509238ce3fde421f20b0ea214..45abdb2f73ec2d25fd2c510fd7d787fbfcab5a8e 100644 (file)
--- a/gram/dfii.py
+++ b/gram/dfii.py
@@ -75,7 +75,7 @@ class DFIInjector(Peripheral, Elaboratable):
         m = Module()
 
         for n, phase in enumerate(self._inti.phases):
-            setattr(m.submodules, "pi" + str(n), PhaseInjector(phase))
+            m.submodules += PhaseInjector(phase)
 
         with m.If(self._control.r_data[0]):
             m.d.comb += self.slave.connect(self.master)