sparc.c (sparc_emit_membar_for_model): Add the implied StoreLoad barrier for atomic...

	* config/sparc/sparc.c (sparc_emit_membar_for_model) <SMM_TSO>: Add
	the implied StoreLoad barrier for atomic operations if before.

From-SVN: r201450

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9e0e253745f3b0f327f46ddd025e0b899cf99582..85ef86bc5948dee6fbff9494fd0d2b4d6175148d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-08-02  Eric Botcazou  <ebotcazou@adacore.com>
+
+       * config/sparc/sparc.c (sparc_emit_membar_for_model) <SMM_TSO>: Add
+       the implied StoreLoad barrier for atomic operations if before.
+
 2013-08-02  Jan Hubicka  <jh@suse.cz>
            Martin Liska  <marxin.liska@gmail.com>
 

diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 48c25dcd5cd92ef8475093f10aa2ce04d8221268..87cfacaa72cd2d98c38d53ce611d61b7f5f54bbb 100644 (file)
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -11318,6 +11318,11 @@ sparc_emit_membar_for_model (enum memmodel model,
       /* Total Store Ordering: all memory transactions with store semantics
         are followed by an implied StoreStore.  */
       implied |= StoreStore;
+
+      /* If we're not looking for a raw barrer (before+after), then atomic
+        operations get the benefit of being both load and store.  */
+      if (load_store == 3 && before_after == 1)
+       implied |= StoreLoad;
       /* FALLTHRU */
 
     case SMM_PSO: