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+Date: Sat, 23 May 2020 21:01:34 +0000
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
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+Message-ID: <bug-314-13-4vjEn4F3y1@https.bugs.libre-soc.org/>
+In-Reply-To: <bug-314-13@https.bugs.libre-soc.org/>
+References: <bug-314-13@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 314] Create POWER9 Condition Register
+ pipeline
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