arm: Replace most htog and gtoh with htole and letoh.

We already know what endianness to use when with ARM. In places where
a ISA was being supplied through an argument, those were left as htog
or gtoh.

Change-Id: Iff01e8b09a061d9a72e657cdd4570836e0da933f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22372
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index 9caf016dd5f509b73c16a6b4bfd4fac24155f364..c58aca452756c7d616de119c601fd2294f15e1c8 100644 (file)
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -314,9 +314,9 @@ class ArmStaticInst : public StaticInst
     cSwap(T val, bool big)
     {
         if (big) {
-            return gtobe(val);
+            return letobe(val);
         } else {
-            return gtole(val);
+            return val;
         }
     }
 
@@ -329,17 +329,17 @@ class ArmStaticInst : public StaticInst
             T tVal;
             E eVals[count];
         } conv;
-        conv.tVal = htog(val);
+        conv.tVal = htole(val);
         if (big) {
             for (unsigned i = 0; i < count; i++) {
-                conv.eVals[i] = gtobe(conv.eVals[i]);
+                conv.eVals[i] = letobe(conv.eVals[i]);
             }
         } else {
             for (unsigned i = 0; i < count; i++) {
-                conv.eVals[i] = gtole(conv.eVals[i]);
+                conv.eVals[i] = conv.eVals[i];
             }
         }
-        return gtoh(conv.tVal);
+        return letoh(conv.tVal);
     }
 
     // Perform an interworking branch.

diff --git a/src/arch/arm/isa/insts/crypto.isa b/src/arch/arm/isa/insts/crypto.isa
index 20ba4c486af212efbe17361c7b5ed347f3dc5013..27dc30e32eed306b058bdc7f01345719225b9790 100644 (file)
--- a/src/arch/arm/isa/insts/crypto.isa
+++ b/src/arch/arm/isa/insts/crypto.isa
@@ -58,9 +58,9 @@ let {{
     '''
     for reg in range(4):
         cryptoRegRegRegPrefix += '''
-            srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
-            srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);
-            destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+            srcReg1.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
+            srcReg2.regs[%(reg)d] = htole(FpOp2P%(reg)d_uw);
+            destReg.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
         ''' % { "reg" : reg }
     cryptoRegRegRegPrefix += '''
         unsigned char *output = (unsigned char *)(&destReg.regs[0]);
@@ -71,7 +71,7 @@ let {{
     cryptoSuffix = ""
     for reg in range(4):
         cryptoSuffix += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg }
 
     cryptoRegRegPrefix = '''
@@ -81,8 +81,8 @@ let {{
     '''
     for reg in range(4):
         cryptoRegRegPrefix += '''
-            srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
-            destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+            srcReg1.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
+            destReg.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
         ''' % { "reg" : reg }
 
     cryptoRegRegPrefix += '''

diff --git a/src/arch/arm/isa/insts/crypto64.isa b/src/arch/arm/isa/insts/crypto64.isa
index 64beaf33d86df9e01409be94b758874d9e87df8b..a1de66cd9adf87e05e2df5758bef6bfe42afa617 100644 (file)
--- a/src/arch/arm/isa/insts/crypto64.isa
+++ b/src/arch/arm/isa/insts/crypto64.isa
@@ -57,9 +57,9 @@ let {{
     '''
     for reg in range(4):
         cryptoRegRegRegPrefix += '''
-            srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw);
-            srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw);
-            destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw);
+            srcReg1.regs[%(reg)d] = htole(AA64FpOp1P%(reg)d_uw);
+            srcReg2.regs[%(reg)d] = htole(AA64FpOp2P%(reg)d_uw);
+            destReg.regs[%(reg)d] = htole(AA64FpDestP%(reg)d_uw);
         ''' % { "reg" : reg }
     cryptoRegRegRegPrefix += '''
         unsigned char *output = (unsigned char *)(&destReg.regs[0]);
@@ -70,7 +70,7 @@ let {{
     cryptoSuffix = ""
     for reg in range(4):
         cryptoSuffix += '''
-            AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg }
 
     cryptoRegRegPrefix = '''
@@ -80,8 +80,8 @@ let {{
     '''
     for reg in range(4):
         cryptoRegRegPrefix += '''
-            srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw);
-            destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw);
+            srcReg1.regs[%(reg)d] = htole(AA64FpOp1P%(reg)d_uw);
+            destReg.regs[%(reg)d] = htole(AA64FpDestP%(reg)d_uw);
         ''' % { "reg" : reg }
 
     cryptoRegRegPrefix += '''

diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 4bd3a2584ead488c16c15cb45da4b97207c56404..251e5c2b9edd90eadad87cb1847b110ac4128f7f 100644 (file)
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -218,11 +218,11 @@ let {{
                                     sizeof(memUnion.elements[0]);
             if (((CPSR)Cpsr).e) {
                 for (unsigned i = 0; i < eCount; i++) {
-                    memUnion.elements[i] = gtobe(memUnion.elements[i]);
+                    memUnion.elements[i] = letobe(memUnion.elements[i]);
                 }
             } else {
                 for (unsigned i = 0; i < eCount; i++) {
-                    memUnion.elements[i] = gtole(memUnion.elements[i]);
+                    memUnion.elements[i] = memUnion.elements[i];
                 }
             }
         '''
@@ -234,14 +234,14 @@ let {{
             if reg == regs - 1:
                 mask = ' & mask(%d)' % (32 - 8 * (regs * 4 - size))
             regSetCode += '''
-            FpDestP%(reg)d_uw = gtoh(memUnion.floatRegBits[%(reg)d])%(mask)s;
+            FpDestP%(reg)d_uw = letoh(memUnion.floatRegBits[%(reg)d])%(mask)s;
             ''' % { "reg" : reg, "mask" : mask }
 
         # Pull everything in from registers
         regGetCode = ''
         for reg in range(regs):
             regGetCode += '''
-            memUnion.floatRegBits[%(reg)d] = htog(FpDestP%(reg)d_uw);
+            memUnion.floatRegBits[%(reg)d] = htole(FpDestP%(reg)d_uw);
             ''' % { "reg" : reg }
 
         loadMemAccCode = convCode + regSetCode
@@ -313,12 +313,12 @@ let {{
         unloadConv = ''
         for dReg in range(dRegs):
             loadConv += '''
-                conv1.cRegs[%(sReg0)d] = htog(FpOp1P%(sReg0)d_uw);
-                conv1.cRegs[%(sReg1)d] = htog(FpOp1P%(sReg1)d_uw);
+                conv1.cRegs[%(sReg0)d] = htole(FpOp1P%(sReg0)d_uw);
+                conv1.cRegs[%(sReg1)d] = htole(FpOp1P%(sReg1)d_uw);
             ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) }
             unloadConv += '''
-                FpDestS%(dReg)dP0_uw = gtoh(conv2.cRegs[2 * %(dReg)d + 0]);
-                FpDestS%(dReg)dP1_uw = gtoh(conv2.cRegs[2 * %(dReg)d + 1]);
+                FpDestS%(dReg)dP0_uw = letoh(conv2.cRegs[2 * %(dReg)d + 0]);
+                FpDestS%(dReg)dP1_uw = letoh(conv2.cRegs[2 * %(dReg)d + 1]);
             ''' % { "dReg" : dReg }
         microDeintNeonCode = '''
             const unsigned dRegs = %(dRegs)d;
@@ -359,12 +359,12 @@ let {{
         unloadConv = ''
         for dReg in range(dRegs):
             loadConv += '''
-                conv1.cRegs[2 * %(dReg)d + 0] = htog(FpOp1S%(dReg)dP0_uw);
-                conv1.cRegs[2 * %(dReg)d + 1] = htog(FpOp1S%(dReg)dP1_uw);
+                conv1.cRegs[2 * %(dReg)d + 0] = htole(FpOp1S%(dReg)dP0_uw);
+                conv1.cRegs[2 * %(dReg)d + 1] = htole(FpOp1S%(dReg)dP1_uw);
             ''' % { "dReg" : dReg }
             unloadConv += '''
-                FpDestP%(sReg0)d_uw = gtoh(conv2.cRegs[%(sReg0)d]);
-                FpDestP%(sReg1)d_uw = gtoh(conv2.cRegs[%(sReg1)d]);
+                FpDestP%(sReg0)d_uw = letoh(conv2.cRegs[%(sReg0)d]);
+                FpDestP%(sReg1)d_uw = letoh(conv2.cRegs[%(sReg1)d]);
             ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) }
         microInterNeonCode = '''
             const unsigned dRegs = %(dRegs)d;
@@ -425,8 +425,8 @@ let {{
         baseLoadRegs = ''
         for reg in range(sRegs):
             baseLoadRegs += '''
-                sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d_uw);
-                sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d_uw);
+                sourceRegs.fRegs[%(reg0)d] = htole(FpOp1P%(reg0)d_uw);
+                sourceRegs.fRegs[%(reg1)d] = htole(FpOp1P%(reg1)d_uw);
             ''' % { "reg0" : (2 * reg + 0),
                     "reg1" : (2 * reg + 1) }
         for dRegs in range(sRegs, 5):
@@ -434,12 +434,12 @@ let {{
             loadRegs = baseLoadRegs
             for reg in range(dRegs):
                 loadRegs += '''
-                    destRegs[%(reg)d].fRegs[0] = htog(FpDestS%(reg)dP0_uw);
-                    destRegs[%(reg)d].fRegs[1] = htog(FpDestS%(reg)dP1_uw);
+                    destRegs[%(reg)d].fRegs[0] = htole(FpDestS%(reg)dP0_uw);
+                    destRegs[%(reg)d].fRegs[1] = htole(FpDestS%(reg)dP1_uw);
                 ''' % { "reg" : reg }
                 unloadRegs += '''
-                    FpDestS%(reg)dP0_uw = gtoh(destRegs[%(reg)d].fRegs[0]);
-                    FpDestS%(reg)dP1_uw = gtoh(destRegs[%(reg)d].fRegs[1]);
+                    FpDestS%(reg)dP0_uw = letoh(destRegs[%(reg)d].fRegs[0]);
+                    FpDestS%(reg)dP1_uw = letoh(destRegs[%(reg)d].fRegs[1]);
                 ''' % { "reg" : reg }
             microUnpackNeonCode = '''
             const unsigned perDReg = (2 * sizeof(uint32_t)) / sizeof(Element);
@@ -479,16 +479,16 @@ let {{
         loadRegs = ''
         for reg in range(sRegs):
             loadRegs += '''
-                sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d_uw);
-                sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d_uw);
+                sourceRegs.fRegs[%(reg0)d] = htole(FpOp1P%(reg0)d_uw);
+                sourceRegs.fRegs[%(reg1)d] = htole(FpOp1P%(reg1)d_uw);
             ''' % { "reg0" : (2 * reg + 0),
                     "reg1" : (2 * reg + 1) }
         for dRegs in range(sRegs, 5):
             unloadRegs = ''
             for reg in range(dRegs):
                 unloadRegs += '''
-                    FpDestS%(reg)dP0_uw = gtoh(destRegs[%(reg)d].fRegs[0]);
-                    FpDestS%(reg)dP1_uw = gtoh(destRegs[%(reg)d].fRegs[1]);
+                    FpDestS%(reg)dP0_uw = letoh(destRegs[%(reg)d].fRegs[0]);
+                    FpDestS%(reg)dP1_uw = letoh(destRegs[%(reg)d].fRegs[1]);
                 ''' % { "reg" : reg }
             microUnpackAllNeonCode = '''
             const unsigned perDReg = (2 * sizeof(uint32_t)) / sizeof(Element);
@@ -529,16 +529,16 @@ let {{
         unloadRegs = ''
         for reg in range(dRegs):
             unloadRegs += '''
-                FpDestP%(reg0)d_uw = gtoh(destRegs.fRegs[%(reg0)d]);
-                FpDestP%(reg1)d_uw = gtoh(destRegs.fRegs[%(reg1)d]);
+                FpDestP%(reg0)d_uw = letoh(destRegs.fRegs[%(reg0)d]);
+                FpDestP%(reg1)d_uw = letoh(destRegs.fRegs[%(reg1)d]);
             ''' % { "reg0" : (2 * reg + 0),
                     "reg1" : (2 * reg + 1) }
         for sRegs in range(dRegs, 5):
             loadRegs = ''
             for reg in range(sRegs):
                 loadRegs += '''
-                    sourceRegs[%(reg)d].fRegs[0] = htog(FpOp1S%(reg)dP0_uw);
-                    sourceRegs[%(reg)d].fRegs[1] = htog(FpOp1S%(reg)dP1_uw);
+                    sourceRegs[%(reg)d].fRegs[0] = htole(FpOp1S%(reg)dP0_uw);
+                    sourceRegs[%(reg)d].fRegs[1] = htole(FpOp1S%(reg)dP1_uw);
                 ''' % { "reg" : reg }
             microPackNeonCode = '''
             const unsigned perDReg =

diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index f242451b2b5225eb94a80f4faf34a3cc09875105..033a59b122bee4439edd7d57b85ca9e38027275d 100644 (file)
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -1156,12 +1156,12 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
-                srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);
+                srcReg1.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
+                srcReg2.regs[%(reg)d] = htole(FpOp2P%(reg)d_uw);
             ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+                    destReg.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if standardFpcsr:
@@ -1169,31 +1169,31 @@ let {{
             FPSCR fpscr = fpStandardFPSCRValue((FPSCR)FpscrExc);
             '''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         if pairwise:
             eWalkCode += '''
             for (unsigned i = 0; i < eCount; i++) {
-                Element srcElem1 = gtoh(2 * i < eCount ?
+                Element srcElem1 = letoh(2 * i < eCount ?
                                         srcReg1.elements[2 * i] :
                                         srcReg2.elements[2 * i - eCount]);
-                Element srcElem2 = gtoh(2 * i < eCount ?
+                Element srcElem2 = letoh(2 * i < eCount ?
                                         srcReg1.elements[2 * i + 1] :
                                         srcReg2.elements[2 * i + 1 - eCount]);
                 Element destElem;
                 %(readDest)s
                 %(op)s
-                destReg.elements[i] = htog(destElem);
+                destReg.elements[i] = htole(destElem);
             }
             ''' % { "op" : op, "readDest" : readDestCode }
         else:
             eWalkCode += '''
             for (unsigned i = 0; i < eCount; i++) {
-                Element srcElem1 = gtoh(srcReg1.elements[i]);
-                Element srcElem2 = gtoh(srcReg2.elements[i]);
+                Element srcElem1 = letoh(srcReg1.elements[i]);
+                Element srcElem2 = letoh(srcReg2.elements[i]);
                 Element destElem;
                 %(readDest)s
                 %(op)s
-                destReg.elements[i] = htog(destElem);
+                destReg.elements[i] = htole(destElem);
             }
             ''' % { "op" : op, "readDest" : readDestCode }
         if standardFpcsr:
@@ -1202,7 +1202,7 @@ let {{
             '''
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegRegOp",
@@ -1323,35 +1323,35 @@ let {{
         ''' % (src1Prefix, src2Prefix, destPrefix)
         for reg in range(src1Cnt):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
+                srcReg1.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
         for reg in range(src2Cnt):
             eWalkCode += '''
-                srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);
+                srcReg2.regs[%(reg)d] = htole(FpOp2P%(reg)d_uw);
             ''' % { "reg" : reg }
         if readDest:
             for reg in range(destCnt):
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+                    destReg.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
-            %(src1Prefix)sElement srcElem1 = gtoh(srcReg1.elements[i]);
-            %(src1Prefix)sElement srcElem2 = gtoh(srcReg2.elements[i]);
+            %(src1Prefix)sElement srcElem1 = letoh(srcReg1.elements[i]);
+            %(src1Prefix)sElement srcElem2 = letoh(srcReg2.elements[i]);
             %(destPrefix)sElement destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[i] = htog(destElem);
+            destReg.elements[i] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode,
                 "src1Prefix" : src1Prefix, "src2Prefix" : src2Prefix,
                 "destPrefix" : destPrefix }
         for reg in range(destCnt):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegRegOp",
@@ -1385,34 +1385,34 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
-                srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);
+                srcReg1.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
+                srcReg2.regs[%(reg)d] = htole(FpOp2P%(reg)d_uw);
             ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+                    destReg.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         eWalkCode += '''
         if (imm < 0 && imm >= eCount) {
             fault = std::make_shared<UndefinedInstruction>(machInst, false,
                                                            mnemonic);
         } else {
             for (unsigned i = 0; i < eCount; i++) {
-                Element srcElem1 = gtoh(srcReg1.elements[i]);
-                Element srcElem2 = gtoh(srcReg2.elements[imm]);
+                Element srcElem1 = letoh(srcReg1.elements[i]);
+                Element srcElem2 = letoh(srcReg2.elements[imm]);
                 Element destElem;
                 %(readDest)s
                 %(op)s
-                destReg.elements[i] = htog(destElem);
+                destReg.elements[i] = htole(destElem);
             }
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegRegImmOp",
@@ -1436,35 +1436,35 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
-                srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);;
+                srcReg1.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
+                srcReg2.regs[%(reg)d] = htole(FpOp2P%(reg)d_uw);;
             ''' % { "reg" : reg }
         if readDest:
             for reg in range(2 * rCount):
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+                    destReg.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         eWalkCode += '''
         if (imm < 0 && imm >= eCount) {
             fault = std::make_shared<UndefinedInstruction>(machInst, false,
                                                           mnemonic);
         } else {
             for (unsigned i = 0; i < eCount; i++) {
-                Element srcElem1 = gtoh(srcReg1.elements[i]);
-                Element srcElem2 = gtoh(srcReg2.elements[imm]);
+                Element srcElem1 = letoh(srcReg1.elements[i]);
+                Element srcElem2 = letoh(srcReg2.elements[imm]);
                 BigElement destElem;
                 %(readDest)s
                 %(op)s
-                destReg.elements[i] = htog(destElem);
+                destReg.elements[i] = htole(destElem);
             }
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(2 * rCount):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegRegImmOp",
@@ -1537,25 +1537,25 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcRegs1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
+                srcRegs1.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
-                    destRegs.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+                    destRegs.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destRegs.elements[i]);'
+            readDestCode = 'destElem = letoh(destRegs.elements[i]);'
             if toInt:
-                readDestCode = 'destReg = gtoh(destRegs.regs[i]);'
-        readOpCode = 'Element srcElem1 = gtoh(srcRegs1.elements[i]);'
+                readDestCode = 'destReg = letoh(destRegs.regs[i]);'
+        readOpCode = 'Element srcElem1 = letoh(srcRegs1.elements[i]);'
         if fromInt:
-            readOpCode = 'uint32_t srcReg1 = gtoh(srcRegs1.regs[i]);'
+            readOpCode = 'uint32_t srcReg1 = letoh(srcRegs1.regs[i]);'
         declDest = 'Element destElem;'
-        writeDestCode = 'destRegs.elements[i] = htog(destElem);'
+        writeDestCode = 'destRegs.elements[i] = htole(destElem);'
         if toInt:
             declDest = 'uint32_t destReg;'
-            writeDestCode = 'destRegs.regs[i] = htog(destReg);'
+            writeDestCode = 'destRegs.regs[i] = htole(destReg);'
         eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
             %(readOp)s
@@ -1571,7 +1571,7 @@ let {{
                 "writeDest" : writeDestCode }
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destRegs.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destRegs.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegImmOp",
@@ -1594,28 +1594,28 @@ let {{
         '''
         for reg in range(4):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
+                srcReg1.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
         if readDest:
             for reg in range(2):
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+                    destReg.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
-            BigElement srcElem1 = gtoh(srcReg1.elements[i]);
+            BigElement srcElem1 = letoh(srcReg1.elements[i]);
             Element destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[i] = htog(destElem);
+            destReg.elements[i] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(2):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegImmOp",
@@ -1638,28 +1638,28 @@ let {{
         '''
         for reg in range(2):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
+                srcReg1.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
         if readDest:
             for reg in range(4):
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+                    destReg.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destReg = gtoh(destReg.elements[i]);'
+            readDestCode = 'destReg = letoh(destReg.elements[i]);'
         eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
-            Element srcElem1 = gtoh(srcReg1.elements[i]);
+            Element srcElem1 = letoh(srcReg1.elements[i]);
             BigElement destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[i] = htog(destElem);
+            destReg.elements[i] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(4):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegImmOp",
@@ -1681,28 +1681,28 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
+                srcReg1.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+                    destReg.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
             unsigned j = i;
-            Element srcElem1 = gtoh(srcReg1.elements[i]);
+            Element srcElem1 = letoh(srcReg1.elements[i]);
             Element destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[j] = htog(destElem);
+            destReg.elements[j] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegOp",
@@ -1724,27 +1724,27 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
+                srcReg1.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+                    destReg.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
-            Element srcElem1 = gtoh(srcReg1.elements[imm]);
+            Element srcElem1 = letoh(srcReg1.elements[imm]);
             Element destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[i] = htog(destElem);
+            destReg.elements[i] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegImmOp",
@@ -1766,20 +1766,20 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
-                destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+                srcReg1.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
+                destReg.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
             ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         eWalkCode += op
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
-            FpOp1P%(reg)d_uw = gtoh(srcReg1.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
+            FpOp1P%(reg)d_uw = letoh(srcReg1.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegOp",
@@ -1868,28 +1868,28 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcRegs.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
+                srcRegs.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+                    destReg.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         eWalkCode += '''
         for (unsigned i = 0; i < eCount / 2; i++) {
-            Element srcElem1 = gtoh(srcRegs.elements[2 * i]);
-            Element srcElem2 = gtoh(srcRegs.elements[2 * i + 1]);
+            Element srcElem1 = letoh(srcRegs.elements[2 * i]);
+            Element srcElem2 = letoh(srcRegs.elements[2 * i + 1]);
             BigElement destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[i] = htog(destElem);
+            destReg.elements[i] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegOp",
@@ -1912,28 +1912,28 @@ let {{
         '''
         for reg in range(4):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
+                srcReg1.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
         if readDest:
             for reg in range(2):
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+                    destReg.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
-            BigElement srcElem1 = gtoh(srcReg1.elements[i]);
+            BigElement srcElem1 = letoh(srcReg1.elements[i]);
             Element destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[i] = htog(destElem);
+            destReg.elements[i] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(2):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegOp",
@@ -1956,22 +1956,22 @@ let {{
         if readDest:
             for reg in range(rCount):
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+                    destReg.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
             Element destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[i] = htog(destElem);
+            destReg.elements[i] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegImmOp",
@@ -1994,28 +1994,28 @@ let {{
         '''
         for reg in range(2):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
+                srcReg1.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
             ''' % { "reg" : reg }
         if readDest:
             for reg in range(4):
                 eWalkCode += '''
-                    destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
+                    destReg.regs[%(reg)d] = htole(FpDestP%(reg)d_uw);
                 ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destReg = gtoh(destReg.elements[i]);'
+            readDestCode = 'destReg = letoh(destReg.elements[i]);'
         eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
-            Element srcElem1 = gtoh(srcReg1.elements[i]);
+            Element srcElem1 = letoh(srcReg1.elements[i]);
             BigElement destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[i] = htog(destElem);
+            destReg.elements[i] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(4):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegOp",
@@ -3718,12 +3718,12 @@ let {{
         eWalkCode = simdEnabledCheckCode + '''
         RegVect destReg;
         for (unsigned i = 0; i < eCount; i++) {
-            destReg.elements[i] = htog((Element)Op1);
+            destReg.elements[i] = htole((Element)Op1);
         }
         '''
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegOp",
@@ -3803,13 +3803,13 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-                srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
-                srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);
+                srcReg1.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);
+                srcReg2.regs[%(reg)d] = htole(FpOp2P%(reg)d_uw);
             ''' % { "reg" : reg }
         eWalkCode += op
         for reg in range(rCount):
             eWalkCode += '''
-            FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+            FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
             ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "RegRegRegImmOp",
@@ -3862,15 +3862,15 @@ let {{
             const unsigned length = %(length)d;
             const bool isVtbl = %(isVtbl)s;
 
-            srcReg2.regs[0] = htog(FpOp2P0_uw);
-            srcReg2.regs[1] = htog(FpOp2P1_uw);
+            srcReg2.regs[0] = htole(FpOp2P0_uw);
+            srcReg2.regs[1] = htole(FpOp2P1_uw);
 
-            destReg.regs[0] = htog(FpDestP0_uw);
-            destReg.regs[1] = htog(FpDestP1_uw);
+            destReg.regs[0] = htole(FpDestP0_uw);
+            destReg.regs[1] = htole(FpDestP1_uw);
         ''' % { "length" : length, "isVtbl" : isVtbl }
         for reg in range(8):
             if reg < length * 2:
-                code += 'table.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);\n' % \
+                code += 'table.regs[%(reg)d] = htole(FpOp1P%(reg)d_uw);\n' % \
                         { "reg" : reg }
             else:
                 code += 'table.regs[%(reg)d] = 0;\n' % { "reg" : reg }
@@ -3886,8 +3886,8 @@ let {{
             }
         }
 
-        FpDestP0_uw = gtoh(destReg.regs[0]);
-        FpDestP1_uw = gtoh(destReg.regs[1]);
+        FpDestP0_uw = letoh(destReg.regs[0]);
+        FpDestP1_uw = letoh(destReg.regs[1]);
         '''
         iop = InstObjParams(name, Name,
                             "RegRegRegOp",

diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa
index 2e0ec44952b6cf38ad968b561b40cf002b2966f6..8d48d6ee7ab0a1e14cf48f27219418bd046ff435 100644 (file)
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -72,35 +72,35 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-        srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw);
-        srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw);
+        srcReg1.regs[%(reg)d] = htole(AA64FpOp1P%(reg)d_uw);
+        srcReg2.regs[%(reg)d] = htole(AA64FpOp2P%(reg)d_uw);
         ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
-        destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw);
+        destReg.regs[%(reg)d] = htole(AA64FpDestP%(reg)d_uw);
         ''' % { "reg" : reg }
         if byElem:
             # 2nd operand has to be read fully
             for reg in range(rCount, 4):
                 eWalkCode += '''
-        srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw);
+        srcReg2.regs[%(reg)d] = htole(AA64FpOp2P%(reg)d_uw);
         ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         if pairwise:
             eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
-            Element srcElem1 = gtoh(2 * i < eCount ?
-                                    srcReg1.elements[2 * i] :
-                                    srcReg2.elements[2 * i - eCount]);
-            Element srcElem2 = gtoh(2 * i < eCount ?
-                                    srcReg1.elements[2 * i + 1] :
-                                    srcReg2.elements[2 * i + 1 - eCount]);
+            Element srcElem1 = letoh(2 * i < eCount ?
+                                     srcReg1.elements[2 * i] :
+                                     srcReg2.elements[2 * i - eCount]);
+            Element srcElem2 = letoh(2 * i < eCount ?
+                                     srcReg1.elements[2 * i + 1] :
+                                     srcReg2.elements[2 * i + 1 - eCount]);
             Element destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[i] = htog(destElem);
+            destReg.elements[i] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         else:
@@ -113,19 +113,19 @@ let {{
             eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
             %(scalarCheck)s
-            Element srcElem1 = gtoh(srcReg1.elements[i]);
-            Element srcElem2 = gtoh(srcReg2.elements[%(src2Index)s]);
+            Element srcElem1 = letoh(srcReg1.elements[i]);
+            Element srcElem2 = letoh(srcReg2.elements[%(src2Index)s]);
             Element destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[i] = htog(destElem);
+            destReg.elements[i] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode,
                 "scalarCheck" : scalarCheck if scalar else "",
                 "src2Index" : "imm" if byElem else "i" }
         for reg in range(rCount):
             eWalkCode += '''
-        AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+        AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg }
         if rCount < 4:  # zero upper half
             for reg in range(rCount, 4):
@@ -176,7 +176,7 @@ let {{
             srcReg1 = 2
         for reg in range(src1Cnt):
             eWalkCode += '''
-        srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(srcReg1)d_uw);
+        srcReg1.regs[%(reg)d] = htole(AA64FpOp1P%(srcReg1)d_uw);
         ''' % { "reg" : reg, "srcReg1" : srcReg1 }
             srcReg1 += 1
         srcReg2 = 0
@@ -184,23 +184,23 @@ let {{
             srcReg2 = 2
         for reg in range(src2Cnt):
             eWalkCode += '''
-        srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(srcReg2)d_uw);
+        srcReg2.regs[%(reg)d] = htole(AA64FpOp2P%(srcReg2)d_uw);
         ''' % { "reg" : reg, "srcReg2" : srcReg2 }
             srcReg2 += 1
         if byElem:
             # 2nd operand has to be read fully
             for reg in range(src2Cnt, 4):
                 eWalkCode += '''
-        srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw);
+        srcReg2.regs[%(reg)d] = htole(AA64FpOp2P%(reg)d_uw);
         ''' % { "reg" : reg }
         if readDest:
             for reg in range(destCnt):
                 eWalkCode += '''
-        destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw);
+        destReg.regs[%(reg)d] = htole(AA64FpDestP%(reg)d_uw);
         ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         scalarCheck = '''
             if (i != 0) {
                 destReg.elements[i] = 0;
@@ -210,12 +210,13 @@ let {{
         eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
             %(scalarCheck)s
-            %(src1Prefix)sElement srcElem1 = gtoh(srcReg1.elements[i]);
-            %(src1Prefix)sElement srcElem2 = gtoh(srcReg2.elements[%(src2Index)s]);
+            %(src1Prefix)sElement srcElem1 = letoh(srcReg1.elements[i]);
+            %(src1Prefix)sElement srcElem2 =
+                letoh(srcReg2.elements[%(src2Index)s]);
             %(destPrefix)sElement destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[i] = htog(destElem);
+            destReg.elements[i] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode,
                 "src1Prefix" : src1Prefix, "src2Prefix" : src2Prefix,
@@ -228,7 +229,7 @@ let {{
             destReg = 2
         for reg in range(destCnt):
             eWalkCode += '''
-        AA64FpDestP%(destReg)d_uw = gtoh(destReg.regs[%(reg)d]);
+        AA64FpDestP%(destReg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg, "destReg": destReg }
             destReg += 1
         if destCnt < 4:
@@ -292,15 +293,15 @@ let {{
         '''
         for reg in range(4 if isDup else rCount):
             eWalkCode += '''
-        srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw);
+        srcReg1.regs[%(reg)d] = htole(AA64FpOp1P%(reg)d_uw);
         ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
-        destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw);
+        destReg.regs[%(reg)d] = htole(AA64FpDestP%(reg)d_uw);
         ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         scalarCheck = '''
             if (i != 0) {
                 destReg.elements[i] = 0;
@@ -311,18 +312,18 @@ let {{
         for (unsigned i = 0; i < eCount; i++) {
             %(scalarCheck)s
             unsigned j = i;
-            Element srcElem1 = gtoh(srcReg1.elements[%(src1Index)s]);
+            Element srcElem1 = letoh(srcReg1.elements[%(src1Index)s]);
             Element destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[j] = htog(destElem);
+            destReg.elements[j] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode,
                 "scalarCheck" : scalarCheck if scalar else "",
                 "src1Index" : "imm" if byElem else "i" }
         for reg in range(rCount):
             eWalkCode += '''
-        AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+        AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg }
         if rCount < 4:  # zero upper half
             for reg in range(rCount, 4):
@@ -355,31 +356,31 @@ let {{
         destReg = 0 if not hi else 2
         for reg in range(2):
             eWalkCode += '''
-        srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(destReg)d_uw);
+        srcReg1.regs[%(reg)d] = htole(AA64FpOp1P%(destReg)d_uw);
         ''' % { "reg" : reg, "destReg": destReg }
             destReg += 1
         destReg = 0 if not hi else 2
         if readDest:
             for reg in range(4):
                 eWalkCode += '''
-        destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw);
+        destReg.regs[%(reg)d] = htole(AA64FpDestP%(reg)d_uw);
         ''' % { "reg" : reg }
                 destReg += 1
         readDestCode = ''
         if readDest:
-            readDestCode = 'destReg = gtoh(destReg.elements[i]);'
+            readDestCode = 'destReg = letoh(destReg.elements[i]);'
         eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
-            Element srcElem1 = gtoh(srcReg1.elements[i]);
+            Element srcElem1 = letoh(srcReg1.elements[i]);
             BigElement destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[i] = htog(destElem);
+            destReg.elements[i] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(4):
             eWalkCode += '''
-        AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+        AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "DataX1RegImmOp" if hasImm else "DataX1RegOp",
@@ -406,12 +407,12 @@ let {{
         '''
         for reg in range(4):
             eWalkCode += '''
-        srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw);
+        srcReg1.regs[%(reg)d] = htole(AA64FpOp1P%(reg)d_uw);
         ''' % { "reg" : reg }
         if readDest:
             for reg in range(2):
                 eWalkCode += '''
-        destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw);
+        destReg.regs[%(reg)d] = htole(AA64FpDestP%(reg)d_uw);
         ''' % { "reg" : reg }
         else:
             eWalkCode += '''
@@ -419,7 +420,7 @@ let {{
         ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         scalarCheck = '''
             if (i != 0) {
                 destReg.elements[i] = 0;
@@ -429,18 +430,18 @@ let {{
         eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
             %(scalarCheck)s
-            BigElement srcElem1 = gtoh(srcReg1.elements[i]);
+            BigElement srcElem1 = letoh(srcReg1.elements[i]);
             Element destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[i] = htog(destElem);
+            destReg.elements[i] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode,
                 "scalarCheck" : scalarCheck if scalar else "" }
         destReg = 0 if not hi else 2
         for reg in range(2):
             eWalkCode += '''
-        AA64FpDestP%(destReg)d_uw = gtoh(destReg.regs[%(reg)d]);
+        AA64FpDestP%(destReg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg, "destReg": destReg }
             destReg += 1
         if hi:
@@ -476,13 +477,13 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-        srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw);
-        srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw);
+        srcReg1.regs[%(reg)d] = htole(AA64FpOp1P%(reg)d_uw);
+        srcReg2.regs[%(reg)d] = htole(AA64FpOp2P%(reg)d_uw);
         ''' % { "reg" : reg }
         eWalkCode += op
         for reg in range(rCount):
             eWalkCode += '''
-        AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+        AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg }
         if rCount < 4:
             for reg in range(rCount, 4):
@@ -510,20 +511,20 @@ let {{
         '''
         for reg in range(4):
             eWalkCode += '''
-        srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw);
+        srcReg1.regs[%(reg)d] = htole(AA64FpOp1P%(reg)d_uw);
         ''' % { "reg" : reg }
         for reg in range(rCount):
             eWalkCode += '''
-        destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw);
+        destReg.regs[%(reg)d] = htole(AA64FpDestP%(reg)d_uw);
         ''' % { "reg" : reg }
         eWalkCode += '''
-        Element srcElem1 = gtoh(srcReg1.elements[imm2]);
+        Element srcElem1 = letoh(srcReg1.elements[imm2]);
         Element destElem = srcElem1;
-        destReg.elements[imm1] = htog(destElem);
+        destReg.elements[imm1] = htole(destElem);
         '''
         for reg in range(rCount):
             eWalkCode += '''
-        AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+        AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "DataX1Reg2ImmOp",
@@ -545,19 +546,19 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-        srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw);
+        srcReg1.regs[%(reg)d] = htole(AA64FpOp1P%(reg)d_uw);
         ''' % { "reg" : reg }
         eWalkCode += '''
-        Element srcElem1 = gtoh(srcReg1.elements[0]);
-        Element srcElem2 = gtoh(srcReg1.elements[1]);
+        Element srcElem1 = letoh(srcReg1.elements[0]);
+        Element srcElem2 = letoh(srcReg1.elements[1]);
         Element destElem;
         %(op)s
-        destReg.elements[0] = htog(destElem);
+        destReg.elements[0] = htole(destElem);
         ''' % { "op" : op }
         destCnt = rCount / 2
         for reg in range(destCnt):
             eWalkCode += '''
-        AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+        AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg }
         for reg in range(destCnt, 4):  # zero upper half
             eWalkCode += '''
@@ -586,25 +587,25 @@ let {{
         ''' % destPrefix
         for reg in range(rCount):
             eWalkCode += '''
-        srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw);
+        srcReg1.regs[%(reg)d] = htole(AA64FpOp1P%(reg)d_uw);
         ''' % { "reg" : reg }
         eWalkCode += '''
         destReg.regs[0] = 0;
         %(destPrefix)sElement destElem = 0;
         for (unsigned i = 0; i < eCount; i++) {
-            Element srcElem1 = gtoh(srcReg1.elements[i]);
+            Element srcElem1 = letoh(srcReg1.elements[i]);
             if (i == 0) {
                 destElem = srcElem1;
             } else {
                 %(op)s
             }
         }
-        destReg.elements[0] = htog(destElem);
+        destReg.elements[0] = htole(destElem);
         ''' % { "op" : op, "destPrefix" : destPrefix }
         destCnt = 2 if doubleDest else 1
         for reg in range(destCnt):
             eWalkCode += '''
-        AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+        AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg }
         for reg in range(destCnt, 4):  # zero upper half
             eWalkCode += '''
@@ -635,28 +636,28 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-        srcRegs.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw);
+        srcRegs.regs[%(reg)d] = htole(AA64FpOp1P%(reg)d_uw);
         ''' % { "reg" : reg }
             if readDest:
                 eWalkCode += '''
-        destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw);
+        destReg.regs[%(reg)d] = htole(AA64FpDestP%(reg)d_uw);
         ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         eWalkCode += '''
         for (unsigned i = 0; i < eCount / 2; i++) {
-            Element srcElem1 = gtoh(srcRegs.elements[2 * i]);
-            Element srcElem2 = gtoh(srcRegs.elements[2 * i + 1]);
+            Element srcElem1 = letoh(srcRegs.elements[2 * i]);
+            Element srcElem2 = letoh(srcRegs.elements[2 * i + 1]);
             BigElement destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[i] = htog(destElem);
+            destReg.elements[i] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(rCount):
             eWalkCode += '''
-        AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+        AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg }
         if rCount < 4:  # zero upper half
             for reg in range(rCount, 4):
@@ -684,22 +685,22 @@ let {{
         if readDest:
             for reg in range(rCount):
                 eWalkCode += '''
-        destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw);
+        destReg.regs[%(reg)d] = htole(AA64FpDestP%(reg)d_uw);
         ''' % { "reg" : reg }
         readDestCode = ''
         if readDest:
-            readDestCode = 'destElem = gtoh(destReg.elements[i]);'
+            readDestCode = 'destElem = letoh(destReg.elements[i]);'
         eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
             Element destElem;
             %(readDest)s
             %(op)s
-            destReg.elements[i] = htog(destElem);
+            destReg.elements[i] = htole(destElem);
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(rCount):
             eWalkCode += '''
-        AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+        AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg }
         if rCount < 4:  # zero upper half
             for reg in range(rCount, 4):
@@ -724,12 +725,12 @@ let {{
         eWalkCode = simd64EnabledCheckCode + '''
         RegVect destReg;
         for (unsigned i = 0; i < eCount; i++) {
-            destReg.elements[i] = htog((Element) %sOp1);
+            destReg.elements[i] = htole((Element) %sOp1);
         }
         ''' % gprSpec
         for reg in range(rCount):
             eWalkCode += '''
-        AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+        AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg }
         if rCount < 4:  # zero upper half
             for reg in range(rCount, 4):
@@ -756,13 +757,13 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-        srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw);
-        srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw);
+        srcReg1.regs[%(reg)d] = htole(AA64FpOp1P%(reg)d_uw);
+        srcReg2.regs[%(reg)d] = htole(AA64FpOp2P%(reg)d_uw);
         ''' % { "reg" : reg }
         eWalkCode += op
         for reg in range(rCount):
             eWalkCode += '''
-        AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+        AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg }
         if rCount < 4:  # zero upper half
             for reg in range(rCount, 4):
@@ -789,14 +790,14 @@ let {{
         '''
         for reg in range(rCount):
             eWalkCode += '''
-        destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw);
+        destReg.regs[%(reg)d] = htole(AA64FpDestP%(reg)d_uw);
         ''' % { "reg" : reg }
         eWalkCode += '''
-        destReg.elements[imm] = htog((Element) %sOp1);
+        destReg.elements[imm] = htole((Element) %sOp1);
         ''' % gprSpec
         for reg in range(rCount):
             eWalkCode += '''
-        AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+        AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg }
         iop = InstObjParams(name, Name,
                             "DataX1RegImmOp",
@@ -819,7 +820,7 @@ let {{
         '''
         for reg in range(4):
             eWalkCode += '''
-        srcReg.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw);
+        srcReg.regs[%(reg)d] = htole(AA64FpOp1P%(reg)d_uw);
         ''' % { "reg" : reg }
         if signExt:
             eWalkCode += '''
@@ -861,13 +862,13 @@ let {{
         ''' % { "rCount" : rCount, "length" : length, "isTbl" : isTbl }
         for reg in range(rCount):
             code += '''
-        srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw);
-        destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw);
+        srcReg2.regs[%(reg)d] = htole(AA64FpOp2P%(reg)d_uw);
+        destReg.regs[%(reg)d] = htole(AA64FpDestP%(reg)d_uw);
         ''' % { "reg" : reg }
         for reg in range(16):
             if reg < length * 4:
                 code += '''
-        table.regs[%(reg)d] = htog(AA64FpOp1P%(p)dV%(v)dS_uw);
+        table.regs[%(reg)d] = htole(AA64FpOp1P%(p)dV%(v)dS_uw);
         ''' % { "reg" : reg, "p" : reg % 4, "v" : reg / 4 }
             else:
                 code += '''
@@ -887,7 +888,7 @@ let {{
         '''
         for reg in range(rCount):
             code += '''
-        AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
+        AA64FpDestP%(reg)d_uw = letoh(destReg.regs[%(reg)d]);
         ''' % { "reg" : reg }
         if rCount < 4:  # zero upper half
             for reg in range(rCount, 4):

diff --git a/src/arch/arm/isa/insts/neon64_mem.isa b/src/arch/arm/isa/insts/neon64_mem.isa
index 03ad29409d0f532087ba70db31c4f4556e950344..a7a04b9c8e4c5cafee9cd9458dd69de5e9bac7ad 100644 (file)
--- a/src/arch/arm/isa/insts/neon64_mem.isa
+++ b/src/arch/arm/isa/insts/neon64_mem.isa
@@ -83,15 +83,15 @@ let {{
                 for (unsigned i = 0; i < eCount; i++) {
                     switch (eSize) {
                       case 0x3:  // 64-bit
-                        writeVecElem(&x, (XReg) gtobe(
+                        writeVecElem(&x, (XReg) letobe(
                             (uint64_t) readVecElem(x, i, eSize)), i, eSize);
                         break;
                       case 0x2:  // 32-bit
-                        writeVecElem(&x, (XReg) gtobe(
+                        writeVecElem(&x, (XReg) letobe(
                             (uint32_t) readVecElem(x, i, eSize)), i, eSize);
                         break;
                       case 0x1:  // 16-bit
-                        writeVecElem(&x, (XReg) gtobe(
+                        writeVecElem(&x, (XReg) letobe(
                             (uint16_t) readVecElem(x, i, eSize)), i, eSize);
                         break;
                       default:  // 8-bit
@@ -102,16 +102,16 @@ let {{
                 for (unsigned i = 0; i < eCount; i++) {
                     switch (eSize) {
                       case 0x3:  // 64-bit
-                        writeVecElem(&x, (XReg) gtole(
-                            (uint64_t) readVecElem(x, i, eSize)), i, eSize);
+                        writeVecElem(&x, (XReg)readVecElem(x, i, eSize),
+                                     i, eSize);
                         break;
                       case 0x2:  // 32-bit
-                        writeVecElem(&x, (XReg) gtole(
-                            (uint32_t) readVecElem(x, i, eSize)), i, eSize);
+                        writeVecElem(&x, (XReg)readVecElem(x, i, eSize),
+                                     i, eSize);
                         break;
                       case 0x1:  // 16-bit
-                        writeVecElem(&x, (XReg) gtole(
-                            (uint16_t) readVecElem(x, i, eSize)), i, eSize);
+                        writeVecElem(&x, (XReg)readVecElem(x, i, eSize),
+                                     i, eSize);
                         break;
                       default:  // 8-bit
                         break;  // Nothing to do here
@@ -129,14 +129,14 @@ let {{
         regSetCode = ''
         for reg in range(4):
             regSetCode += '''
-            AA64FpDestP%(reg)d_uw = gtoh(memUnion.floatRegBits[%(reg)d]);
+            AA64FpDestP%(reg)d_uw = letoh(memUnion.floatRegBits[%(reg)d]);
             ''' % { 'reg' : reg }
 
         # Pull everything in from registers
         regGetCode = ''
         for reg in range(4):
             regGetCode += '''
-            memUnion.floatRegBits[%(reg)d] = htog(AA64FpDestP%(reg)d_uw);
+            memUnion.floatRegBits[%(reg)d] = htole(AA64FpDestP%(reg)d_uw);
             ''' % { 'reg' : reg }
 
         loadMemAccCode = convCode + regSetCode

diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index 6d588bab87cbf0f90153689f2a602506dfd485fc..26bcb49699363c12e55692231b93e416597fb24f 100644 (file)
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -74,7 +74,7 @@ Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
 
     uint64_t diffVector;
     parent->read(&diffVector, sizeof(diffVector));
-    diffVector = ArmISA::gtoh(diffVector);
+    diffVector = letoh(diffVector);
 
     int changes = 0;
     for (int i = 0; i < STATE_NUMVALS; i++) {
@@ -92,7 +92,7 @@ Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
     int pos = 0;
     for (int i = 0; i < STATE_NUMVALS; i++) {
         if (changed[i]) {
-            newState[i] = ArmISA::gtoh(values[pos++]);
+            newState[i] = letoh(values[pos++]);
             changed[i] = (newState[i] != oldState[i]);
         }
     }

diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index cacbe3ad56ae8ab2a08e86f9cff1fcb35215d5d5..70024ae68eb22ac586522e058145eb112b8711ae 100644 (file)
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -403,7 +403,7 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
 
     // figure out argc
     IntType argc = argv.size();
-    IntType guestArgc = ArmISA::htog(argc);
+    IntType guestArgc = htole(argc);
 
     //Write out the sentry void *
     IntType sentry_NULL = 0;