+2021-06-27 Mike Frysinger <vapier@gentoo.org>
+
+ * profile.c (frvbf_model_insn_after): Change return to void.
+ (enforce_full_fr_latency, post_wait_for_FR, post_wait_for_FRdouble,
+ post_wait_for_ACC, post_wait_for_CCR, post_wait_for_SPR,
+ post_wait_for_fdiv, post_wait_for_fsqrt,
+ post_wait_for_float): Likewise.
+ * profile.h (post_wait_for_FR, post_wait_for_FRdouble,
+ post_wait_for_ACC, post_wait_for_CCR, post_wait_for_SPR,
+ post_wait_for_fdiv, post_wait_for_fsqrt, post_wait_for_float,
+ post_wait_for_media): Likewise.
+
2021-06-27 Mike Frysinger <vapier@gentoo.org>
* frv.c (frvbf_shift_left_arith_saturate): Add braces to if statement.
}
}
-USI
+void
frvbf_model_branch (SIM_CPU *current_cpu, PCADDR target, int hint)
{
/* Record the hint and branch address for use in profiling. */
/* Calculate how long the post processing for a floating point insn must
wait for resources to become available. */
-int
+void
post_wait_for_FR (SIM_CPU *cpu, INT in_FR)
{
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
/* Calculate how long the post processing for a floating point insn must
wait for resources to become available. */
-int
+void
post_wait_for_FRdouble (SIM_CPU *cpu, INT in_FR)
{
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
}
}
-int
+void
post_wait_for_ACC (SIM_CPU *cpu, INT in_ACC)
{
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
}
}
-int
+void
post_wait_for_CCR (SIM_CPU *cpu, INT in_CCR)
{
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
}
}
-int
+void
post_wait_for_SPR (SIM_CPU *cpu, INT in_SPR)
{
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
}
}
-int
+void
post_wait_for_fdiv (SIM_CPU *cpu, INT slot)
{
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
}
}
-int
+void
post_wait_for_fsqrt (SIM_CPU *cpu, INT slot)
{
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
}
}
-int
+void
post_wait_for_float (SIM_CPU *cpu, INT slot)
{
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
}
}
-int
+void
post_wait_for_media (SIM_CPU *cpu, INT slot)
{
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
void load_wait_for_FRdouble (SIM_CPU *, INT);
void enforce_full_fr_latency (SIM_CPU *, INT);
void enforce_full_acc_latency (SIM_CPU *, INT);
-int post_wait_for_FR (SIM_CPU *, INT);
-int post_wait_for_FRdouble (SIM_CPU *, INT);
-int post_wait_for_ACC (SIM_CPU *, INT);
-int post_wait_for_CCR (SIM_CPU *, INT);
-int post_wait_for_SPR (SIM_CPU *, INT);
-int post_wait_for_fdiv (SIM_CPU *, INT);
-int post_wait_for_fsqrt (SIM_CPU *, INT);
-int post_wait_for_float (SIM_CPU *, INT);
-int post_wait_for_media (SIM_CPU *, INT);
+void post_wait_for_FR (SIM_CPU *, INT);
+void post_wait_for_FRdouble (SIM_CPU *, INT);
+void post_wait_for_ACC (SIM_CPU *, INT);
+void post_wait_for_CCR (SIM_CPU *, INT);
+void post_wait_for_SPR (SIM_CPU *, INT);
+void post_wait_for_fdiv (SIM_CPU *, INT);
+void post_wait_for_fsqrt (SIM_CPU *, INT);
+void post_wait_for_float (SIM_CPU *, INT);
+void post_wait_for_media (SIM_CPU *, INT);
void trace_vliw_wait_cycles (SIM_CPU *);
void handle_resource_wait (SIM_CPU *);