add SVSHAPE setup for parallel/prefix but it refuses to work
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 27 Apr 2023 23:42:14 +0000 (00:42 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Jun 2023 18:51:17 +0000 (19:51 +0100)
correctly right now because SVyd is utterly borked. needs investigating

openpower/isa/simplev.mdwn

index c350b3cf86fadcfdd22663c7119249e00328ff4a..fae79b4c0548ac47ba699ff739307f9e3ac61c8d 100644 (file)
@@ -298,11 +298,18 @@ Pseudo-code:
         SVSHAPE0[0:5] <- (0b0 || SVxd)   # xdim
         SVSHAPE0[12:17] <- (0b0 || SVzd)   # zdim - "striding" (2D DCT)
         mscale <- (0b0 || SVzd) + 1
-        SVSHAPE0[30:31] <- 0b10          # parallel reduce submode
+        SVSHAPE0[30:31] <- 0b10          # parallel reduce/prefix submode
         # copy
         SVSHAPE1[0:31] <- SVSHAPE0[0:31]
-        # set up right operand (left operand 28:29 is zero)
-        SVSHAPE1[28:29] <- 0b01           # right operand
+        # set up submodes: parallel or prefix
+        if (SVyd = 1) then
+            SVSHAPE0[28:29] <- 0b00   # left operand
+            SVSHAPE1[28:29] <- 0b01   # right operand
+        if (SVyd = 2) then
+            SVSHAPE0[28:29] <- 0b10   # left operand
+            SVSHAPE1[28:29] <- 0b11   # right operand
+        SVSHAPE0[28:29] <- 0b00   # left operand
+        SVSHAPE1[28:29] <- 0b01   # right operand
     # set VL, MVL and Vertical-First
     m[0:12] <- vlen * mscale
     maxvl[0:6] <- m[6:12]