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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 81d7a195b6a30d67ed18202a922dec15525d343d..1edb85af44c283853260cc280acc3ba3ace62312 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -918,6 +918,10 @@ on a context-switch. This may make some implementations slower.
 
 *Implementor's Note: many SIMD-based Parallel Reduction Algorithms are
 implemented in hardware with MVs that ensure lane-crossing is minimised.
+The mistake which would be catastrophic to SVP64 to make is to then
+limit the Reduction Sequence for all implementors
+based solely and exclusively on what one
+specific internal microarchitecture does.
 In SIMD ISAs the internal SIMD Architectural design is exposed and imposed on the programmer. Cray-style Vector ISAs on the other hand provide convenient,
 compact and efficient encodings of abstract concepts.
 It is the Implementor's responsibility to produce a design