Remove names from end record statements

These are optional, and vhdlpp from iverilog barfs on them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/fpga/clk_gen_mcmm.vhd b/fpga/clk_gen_mcmm.vhd
index b76995a45a76ebca3a9b119ac4e668c76abdad44..206b02acaca8d2a42cb755db6eb63a8cedf7beee 100644 (file)
--- a/fpga/clk_gen_mcmm.vhd
+++ b/fpga/clk_gen_mcmm.vhd
@@ -22,7 +22,7 @@ architecture rtl of clock_generator is
         clkfbout_mult : real range 2.0 to 64.0;
         clkout_divide : real range 1.0 to 128.0;
         divclk_divide : integer range 1 to 106;
-    end record pll_settings_t;
+    end record;
 
     function gen_pll_settings (
         constant freq_hz : positive)

diff --git a/fpga/clk_gen_plle2.vhd b/fpga/clk_gen_plle2.vhd
index e2c761ca876d23b2e7d89badabdf4ffe6cc87f7f..f82cb53beed019d62aa33527972201855463b434 100644 (file)
--- a/fpga/clk_gen_plle2.vhd
+++ b/fpga/clk_gen_plle2.vhd
@@ -23,7 +23,7 @@ architecture rtl of clock_generator is
     clkfbout_mult : integer range 2 to 64;
     clkout_divide : integer range 1 to 128;
     divclk_divide : integer range 1 to 56;
-  end record pll_settings_t;
+  end record;
 
   function gen_pll_settings (
     constant freq_hz : positive)

diff --git a/wishbone_types.vhdl b/wishbone_types.vhdl
index 24c46d73da891f3e4f33f7f1fed46dd0fdddf531..6055d9c6bba8b2b2323fa5854c345b3fa588f182 100644 (file)
--- a/wishbone_types.vhdl
+++ b/wishbone_types.vhdl
@@ -15,13 +15,13 @@ package wishbone_types is
                stb : std_ulogic;
                sel : std_ulogic_vector(7 downto 0);
                we  : std_ulogic;
-       end record wishbone_master_out;
+       end record;
        constant wishbone_master_out_init : wishbone_master_out := (cyc => '0', stb => '0', we => '0', others => (others => '0'));
 
        type wishbone_slave_out is record
                dat : wishbone_data_type;
                ack : std_ulogic;
-       end record wishbone_slave_out;
+       end record;
        constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', others => (others => '0'));
 
 end package wishbone_types;