ruby: removed last level cache support

Removed the last level cache support and MOESI_hammer's dependency on it.
Replaces the LLC support with the more generic MachineType count.

diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index 66bb85cf9b1a2a5d64954910cfea4337a8ed48a6..4bdfcb23d17edd5ba8def37c2d5c7e506817109d 100644 (file)
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -379,7 +379,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
       out_msg.MessageSize := MessageSizeType:Request_Control;
-      TBEs[address].NumPendingMsgs := getNumberOfLastLevelCaches(); // One from each other cache (n-1) plus the memory (+1)
+      TBEs[address].NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each other cache (n-1) plus the memory (+1)
     }
   }
 
@@ -390,7 +390,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
       out_msg.MessageSize := MessageSizeType:Request_Control;
-      TBEs[address].NumPendingMsgs := getNumberOfLastLevelCaches(); // One from each other cache (n-1) plus the memory (+1)
+      TBEs[address].NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each other cache (n-1) plus the memory (+1)
     }
   }
 

diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
index 57433dd3db83735db6a4546646fcf5ee056e0ad5..3cbeb84315c3dda88d8226fdbf4b44a67bdeea72 100644 (file)
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -320,7 +320,7 @@ machine(Directory, "AMD Hammer-like protocol")
       //
       // One ack for each last-level cache
       //
-      TBEs[address].NumPendingMsgs := getNumberOfLastLevelCaches();
+      TBEs[address].NumPendingMsgs := machineCount(MachineType:L1Cache);
       //
       // Assume initially that the caches store a clean copy and that memory
       // will provide the data
@@ -468,7 +468,7 @@ machine(Directory, "AMD Hammer-like protocol")
   }
 
   action(f_forwardRequest, "f", desc="Forward requests") {
-    if (getNumberOfLastLevelCaches() > 1) {
+    if (machineCount(MachineType:L1Cache) > 1) {
       peek(requestQueue_in, RequestMsg) {
         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
           out_msg.Address := address;

diff --git a/src/mem/protocol/RubySlicc_ComponentMapping.sm b/src/mem/protocol/RubySlicc_ComponentMapping.sm
index 891820c46fa7d8e584e50f91daccc6beada22b11..3c777e965e602418227ba5ad041689dc012c085b 100644 (file)
--- a/src/mem/protocol/RubySlicc_ComponentMapping.sm
+++ b/src/mem/protocol/RubySlicc_ComponentMapping.sm
@@ -29,7 +29,7 @@
 
 // Mapping functions
 
-int getNumberOfLastLevelCaches();
+int machineCount(MachineType machType);
 
 // NodeID map_address_to_node(Address addr);
 MachineID mapAddressToRange(Address addr, MachineType type, int low, int high);

diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc
index 4d37b000781b27eef9b646f5f65b5c9231675596..0821201e7be4e803374e9f45155cb001a31b5fbe 100644 (file)
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc
@@ -31,8 +31,4 @@
 #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
 #include "mem/ruby/system/CacheMemory.hh"
 
-int getNumberOfLastLevelCaches()
-{
-  return CacheMemory::numberOfLastLevelCaches();
-}
 

diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
index 69424c4143d43e761266ed1d91a4e922f3f0264f..5ffd0f295b60f48f88ad75b99d15e0ff95c27a78 100644 (file)
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
@@ -42,6 +42,7 @@
 #include "mem/ruby/common/NetDest.hh"
 #include "mem/protocol/GenericMachineType.hh"
 #include "mem/ruby/system/DirectoryMemory.hh"
+#include "mem/protocol/MachineType.hh"
 
 #ifdef MACHINETYPE_L1Cache
 #define MACHINETYPE_L1CACHE_ENUM MachineType_L1Cache
@@ -67,9 +68,6 @@
 #define MACHINETYPE_DMA_ENUM MachineType_NUM
 #endif
 
-// used to determine the number of acks to wait for
-int getNumberOfLastLevelCaches();
-
 // used to determine the home directory
 // returns a value between 0 and total_directories_within_the_system
 inline
@@ -152,5 +150,8 @@ extern inline GenericMachineType ConvertMachToGenericMach(MachineType machType)
   }
 }
 
+extern inline int machineCount(MachineType machType) {
+    return MachineType_base_count(machType);
+}
 
 #endif  // COMPONENTMAPPINGFNS_H

diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc
index 8c51121837ecca7d8056a4f82300760b6959ad2a..110dce2d0af5489d1c668b77e2707db030758ddd 100644 (file)
--- a/src/mem/ruby/system/CacheMemory.cc
+++ b/src/mem/ruby/system/CacheMemory.cc
@@ -28,9 +28,6 @@
 
 #include "mem/ruby/system/CacheMemory.hh"
 
-int CacheMemory::m_num_last_level_caches = 0;
-MachineType CacheMemory::m_last_level_machine_type = MachineType_FIRST;
-
 // ******************* Definitions *******************
 
 // Output operator definition
@@ -75,19 +72,6 @@ void CacheMemory::init()
     else
       assert(false);
 
-  m_num_last_level_caches = 
-    MachineType_base_count(MachineType_FIRST);
-#if 0
-  for (uint32 i=0; i<argv.size(); i+=2) {
-      if (m_last_level_machine_type < m_controller->getMachineType()) {
-        m_num_last_level_caches = 
-          MachineType_base_count(m_controller->getMachineType());
-        m_last_level_machine_type = 
-          m_controller->getMachineType();
-      } 
-  }
-#endif
-
   m_cache.setSize(m_cache_num_sets);
   m_locked.setSize(m_cache_num_sets);
   for (int i = 0; i < m_cache_num_sets; i++) {
@@ -112,13 +96,6 @@ CacheMemory::~CacheMemory()
   }
 }
 
-int
-CacheMemory::numberOfLastLevelCaches()
-{ 
-  return m_num_last_level_caches; 
-}
-
-
 void CacheMemory::printConfig(ostream& out)
 {
   out << "Cache config: " << m_cache_name << endl;

diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index f70427f2d6e2fa9c57b2277e0f5418e402ec96c3..74eb5d68df6027e7439f911b2dc04ed562f6e3f3 100644 (file)
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -106,8 +106,6 @@ public:
   AccessPermission getPermission(const Address& address) const;
   void changePermission(const Address& address, AccessPermission new_perm);
 
-  static int numberOfLastLevelCaches();
-
   int getLatency() const { return m_latency; }
 
   // Hook for checkpointing the contents of the cache
@@ -172,12 +170,6 @@ private:
   int m_cache_num_sets;
   int m_cache_num_set_bits;
   int m_cache_assoc;
-
-  static Vector< CacheMemory* > m_all_caches;
-  
-  static int m_num_last_level_caches;
-  static MachineType m_last_level_machine_type;
-
 };
 
 #endif //CACHEMEMORY_H