**ISA Comparison Table to DRAFT SVP64** - discussion and research at <https://bugs.libre-soc.org/show_bug.cgi?id=893>
-|ISA <br>name |No <br>opcodes|No <br>intrinsics|Taxonomy / <br>Class|setvl <br> scalable|Predicate <br> Masks|Twin <br>Pred|Vector <br>regs |128-bit <br> ops |Bigint |LDST <br>F/First|Data-dep<br> Fail-first|Pred-<br> Result|HW<br> Matrix|DCT/FFT <br>HW|
-|---------------|--------------|-----------------|--------------------|-------------------|--------------------|-------------|----------------|-----------------|-------|----------------|-----------------------|----------------|-------------|--------------|
-|SVP64 |5 [^1] |see [^2] |Scalable [^3] |yes |yes |yes [^4] |no [^5] |see [^6] |yes[^7]|yes [^8] |yes [^9] |yes [^10] |yes [^11] | yes[^12] |
-|VSX |700+ |700?[^27] |PackedSIMD |no |no |no |yes [^13] |yes |no |no |no |no |yes [^14] | no |
-|NEON |~250 [^15] |7088 [^28] |PackedSIMD |no |no |no |yes |see [^35] |no |no |no |no |no | no |
-|SVE2 |~1000 [^16] |6040 [^29] |Predicated SIMD[^17]|no [^17] |yes |no |yes |see [^35] |no |yes [^8] |no |no |yes [^33] | no |
-|AVX512 [^18] |~1000s [^19] |7256 [^30] |Predicated SIMD |no |yes |no |yes |see [^35] |no |no |no |no |yes [^34] | no |
-|RVV [^20] |~190 [^21] |~25000[^31] |Scalable[^22] |yes |yes |no |yes |yes [^23] |no |yes |no |no |no | no |
-|Aurora SX[^24] |~200 [^25] |unknown [^32] |Scalable [^26] |yes |yes |no |yes |no |no |no |no |no |? | no |
+|ISA <br>name |No <br>opcodes|No <br>intrinsics|Taxonomy / <br>Class|setvl <br> scalable|Predicate <br> Masks|Twin <br>Pred|Vector <br>regs |128-bit <br> ops |Bigint |LDST <br>F/First|Data-dep<br> Fail-first|Pred-<br> Result|HW<br> Matrix|DCT/FFT <br>HW|
+|---------------|--------------|-----------------|--------------------|-------------------|--------------------|-------------|----------------|-----------------|--------|----------------|-----------------------|----------------|-------------|--------------|
+|SVP64 |5 [^1] |see [^2] |Scalable [^3] |yes |yes |yes [^4] |no [^5] |see [^6] |yes[^7] |yes [^8] |yes [^9] |yes [^10] |yes [^11] | yes[^12] |
+|VSX |700+ |700?[^27] |PackedSIMD |no |no |no |yes [^13] |yes |no |no |no |no |yes [^14] | no |
+|NEON |~250 [^15] |7088 [^28] |PackedSIMD |no |no |no |yes |see [^35] |no |no |no |no |no | no |
+|SVE2 |~1000 [^16] |6040 [^29] |Predicated SIMD[^17]|no [^17] |yes |no |yes |see [^35] |no |yes [^8] |no |no |yes [^33] | no |
+|AVX512 [^18] |~1000s [^19] |7256 [^30] |Predicated SIMD |no |yes |no |yes |see [^35] |no |no |no |no |yes [^34] | no |
+|RVV [^20] |~190 [^21] |~25000[^31] |Scalable[^22] |yes |yes |no |yes |yes [^23] |no |yes |no |no |no | no |
+|Aurora SX[^24] |~200 [^25] |unknown [^32] |Scalable [^26] |yes |yes |no |yes |no |no |no |no |no |? | no |
+|66000[^36] |~200 |unknown |AutoVec[^36] |see [^36] |no [^36] |no |see [^36] |no |yes[^37]|see [^36] |no |no |no | no |
[^1]: plus EXT001 24-bit prefixing using 25% of EXT001 space. See [[sv/svp64]]
[^3]: A 2-Dimensional Scalable Vector ISA **specifically designed for the Power ISA** with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]]
which is very hard to tell at a glance if it is power-2 or non-power-2
[^34]: [Advanced matrix Extensions](https://en.wikipedia.org/wiki/Advanced_Matrix_Extensions) supports BF16 and INT8 only. Separate regfile, power-of-two "tiles". Not general-purpose at all.
[^35]: Although registers may be 128-bit in NEON, SVE2, and AVX, unlike VSX there are very few (or no) actual arithmetic 128-bit operations. Only RVV and SVP64 have the possibility of 128-bit ops
+[^36]: Mitch Alsup's MyISA 66000 is available on request. An extremely powerful RISC ISA with an auto-vectorisation LOOP construct built-in as an extension named VVM. Classified as "Vertical-First".
+[^37]: MyISA 66000 has a CARRY register up to 64-bit. Repeated application of FMA or ADD (esp. within Auto-Vectored LOOPS) automatically and inherently creates big-int operations with zero effort.
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