soc: fix register_rom

diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
index 3d90fd63cf15a94304083c4cec1dc66750593200..f7d479a0a92f3e83bf13deb714e713f59771ceea 100644 (file)
--- a/misoclib/soc/__init__.py
+++ b/misoclib/soc/__init__.py
@@ -27,6 +27,7 @@ class SoC(Module):
                "timer0":               1,
        }
        mem_map = {
+               "rom":          0x00000000, # (shadow @0x80000000)
                "sram":         0x10000000, # (shadow @0x90000000)
                "sdram":        0x40000000, # (shadow @0xc0000000)
                "csr":          0x60000000, # (shadow @0xe0000000)
@@ -34,7 +35,7 @@ class SoC(Module):
        def __init__(self, platform, clk_freq, cpu_or_bridge=None,
                                with_cpu=True, cpu_type="lm32", cpu_reset_address=0x00000000,
                                                           cpu_boot_file="software/bios/bios.bin",
-                               with_rom=False, rom_size=0xa000,
+                               with_rom=False, rom_size=0x8000,
                                with_sram=True, sram_size=4096,
                                with_sdram=False, sdram_size=64*1024,
                                with_csr=True, csr_data_width=8, csr_address_width=14,
@@ -86,7 +87,7 @@ class SoC(Module):
 
                        if with_rom:
                                self.submodules.rom = wishbone.SRAM(rom_size, read_only=True)
-                               self.register_mem("rom", self.cpu_reset_address, self.rom.bus, rom_size)
+                               self.register_rom(self.rom.bus, rom_size)
 
                        if with_sram:
                                self.submodules.sram = wishbone.SRAM(sram_size)
@@ -140,9 +141,9 @@ class SoC(Module):
                if size is not None:
                        self.add_memory_region(name, address, size)
 
-       # XXX for retro-compatibilty, we should maybe use directly register_mem in targets
-       def register_rom(self, interface):
-               self.register_mem("rom", self.cpu_reset_address, interface, size=self.rom_size)
+       def register_rom(self, interface, rom_size=0xa000):
+               self.add_wb_slave(mem_decoder(self.mem_map["rom"]), interface)
+               self.add_memory_region("rom", self.cpu_reset_address, rom_size)
 
        def check_csr_region(self, name, origin):
                for n, o, l, obj in self.csr_regions: