liteeth/core/mac: minor cleanup

diff --git a/misoclib/com/liteeth/core/mac/__init__.py b/misoclib/com/liteeth/core/mac/__init__.py
index 14bbf74b522e0362c860f44dfb19b0c3f7ea773f..acb226d6975c4e37ce186b06c90d5699003ab603 100644 (file)
--- a/misoclib/com/liteeth/core/mac/__init__.py
+++ b/misoclib/com/liteeth/core/mac/__init__.py
@@ -5,8 +5,10 @@ from misoclib.com.liteeth.core.mac.frontend.wishbone import LiteEthMACWishboneIn
 
 
 class LiteEthMAC(Module, AutoCSR):
-    def __init__(self, phy, dw, interface="crossbar", endianness="big",
-            with_preamble_crc=True):
+    def __init__(self, phy, dw,
+                 interface="crossbar",
+                 endianness="big",
+                 with_preamble_crc=True):
         self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_preamble_crc)
         self.csrs = []
         if interface == "crossbar":
@@ -24,10 +26,8 @@ class LiteEthMAC(Module, AutoCSR):
             self.comb += Port.connect(self.interface, self.core)
             self.ev, self.bus = self.interface.sram.ev, self.interface.bus
             self.csrs = self.interface.get_csrs() + self.core.get_csrs()
-        elif interface == "dma":
-            raise NotImplementedError
         else:
-            raise ValueError(interface + " not supported by LiteEthMac!")
+            raise NotImplementedError
 
     def get_csrs(self):
         return self.csrs