arch-riscv,util: Add m5op.S for riscv to enable pseudo inst use

This change adds assembly code for riscv pseudo instructions so
that they can be used with riscv benchmarks.

Change-Id: Ic979fd375e7750e92f52b900bf39e351f629fe2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38515
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/util/m5/README.md b/util/m5/README.md
index cbdff1d12f795232814125ea7b5aa82ec55c48e4..9bae1531ac403e5fa445cfb2ab9fdd979a644cd9 100644 (file)
--- a/util/m5/README.md
+++ b/util/m5/README.md
@@ -98,6 +98,7 @@ first identify what ABI(s) you're targetting.
  thumb   | ARM thumb    | instruction
  sparc   | 64 bit SPARC | instruction
  x86     | amd64/x86_64 | instruction, address
+ riscv   | 64 bit RISCV | instruction
 
 ## SCons
 
@@ -166,6 +167,7 @@ scons x86.CROSS_COMPILE=x86_64-linux-gnu- build/x86/out/m5
  thumb   | arm       | arm-linux-gnueabihf-
  sparc   | sparc64   | sparc64-linux-gnu-
  x86     | x86_64    |
+ riscv   | riscv64   | riscv64-linux-gnu-
 
 Note that the default setting for the x86 cross compiler prefix is blank,
 meaning that the native/host compiler will be used. If building on a non-x86
@@ -254,6 +256,7 @@ varies based on the ABI.
  thumb   | instruction
  sparc   | instruction
  x86     | address
+ riscv   | instruction
 
 The default is usually to use a magic instruction, which for most ABIs is the
 only mechanism that's supported, and is what the m5 utility would

diff --git a/util/m5/src/abi/riscv/SConsopts b/util/m5/src/abi/riscv/SConsopts
new file mode 100644 (file)
index 0000000..e46ef74
--- /dev/null
+++ b/util/m5/src/abi/riscv/SConsopts
@@ -0,0 +1,32 @@
+# Copyright 2020 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Import('*')
+
+env['ABI'] = 'riscv'
+get_abi_opt('CROSS_COMPILE', 'riscv64-linux-gnu-')
+get_abi_opt('QEMU_ARCH', 'riscv64')
+
+env['CALL_TYPE']['inst'].impl('m5op.S', 'verify_inst.cc', default=True)

diff --git a/util/m5/src/abi/riscv/m5op.S b/util/m5/src/abi/riscv/m5op.S
new file mode 100644 (file)
index 0000000..babe854
--- /dev/null
+++ b/util/m5/src/abi/riscv/m5op.S
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include <gem5/asm/generic/m5ops.h>
+
+// riscv pseudo instructions have bit 1:0 (QUADRANT) = 0x3,
+// bit 6:2 (OPCODE) = 0x1e, and bit 31:25 (M5FUNC) specifies
+// the function performed by pseudo instruction
+
+.macro m5op_func, name, func
+        .globl \name
+        \name:
+        .long 0x0000007b | (\func << 25)
+        ret
+.endm
+
+.text
+#define M5OP(name, func) m5op_func name, func;
+        M5OP_FOREACH
+#undef M5OP

diff --git a/util/m5/src/abi/riscv/verify_inst.cc b/util/m5/src/abi/riscv/verify_inst.cc
new file mode 100644 (file)
index 0000000..055cb8a
--- /dev/null
+++ b/util/m5/src/abi/riscv/verify_inst.cc
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2020 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include <gtest/gtest.h>
+
+#include "call_type/verify_inst.hh"
+
+void
+abi_verify_inst(const siginfo_t &info, int func)
+{
+    EXPECT_EQ((func << 1), *(uint8_t *)((uintptr_t)info.si_addr + 3));
+}