opcodes/riscv-dis.c: Tidying with spacing
authorTsukasa OI <research_trasio@irq.a4lg.com>
Sat, 27 Aug 2022 13:07:34 +0000 (13:07 +0000)
committerTsukasa OI <research_trasio@irq.a4lg.com>
Fri, 14 Oct 2022 05:21:41 +0000 (05:21 +0000)
Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.

This commit takes care of improper spacing for code clarity.

opcodes/ChangeLog:

* riscv-dis.c (riscv_disassemble_insn): Tidying with spacing.

opcodes/riscv-dis.c

index 2d1faf26eb3ebc1c691b92265baf633f9d47d91d..088d0d91080344bbad3bdc4ae2e2cf824f14bfcf 100644 (file)
@@ -715,7 +715,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
        }
 
       /* If arch has the Zfinx extension, replace FPR with GPR.  */
-      if(riscv_subset_supports (&riscv_rps_dis, "zfinx"))
+      if (riscv_subset_supports (&riscv_rps_dis, "zfinx"))
        riscv_fpr_names = riscv_gpr_names;
 
       for (; op->name; op++)