type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM
mem_mode=timing
mem_ranges=2147483648:2415919103
-memories=system.realview.nvmem system.physmem system.realview.vram
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/z/stever/hg/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu0.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu0.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu0.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu0.l2cache.tags]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
[system.cpu0.tracer]
type=ExeTracer
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu1.toL2Bus.slave[5]
[system.cpu1.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu1.toL2Bus.slave[4]
[system.cpu1.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu1.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu1.l2cache.tags]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
[system.cpu1.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 31 2014 10:01:44
-gem5 started Oct 31 2014 11:28:00
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
+gem5 compiled Mar 15 2015 20:30:55
+gem5 started Mar 15 2015 20:31:14
+gem5 executing on zizzer2
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
- 0: system.cpu0.isa: ISA system set to: 0x5a2b680 0x5a2b680
- 0: system.cpu1.isa: ISA system set to: 0x5a2b680 0x5a2b680
+info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+ 0: system.cpu0.isa: ISA system set to: 0x36c6a30 0x36c6a30
+ 0: system.cpu1.isa: ISA system set to: 0x36c6a30 0x36c6a30
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
+info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: Read CNTFREQ_EL0 frequency
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2843665155500 because m5_exit instruction encountered
+Exiting @ tick 2846097440000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.846001 # Number of seconds simulated
-sim_ticks 2846001096000 # Number of ticks simulated
-final_tick 2846001096000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.846097 # Number of seconds simulated
+sim_ticks 2846097440000 # Number of ticks simulated
+final_tick 2846097440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 163513 # Simulator instruction rate (inst/s)
-host_op_rate 197998 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3697981305 # Simulator tick rate (ticks/s)
-host_mem_usage 648920 # Number of bytes of host memory used
-host_seconds 769.61 # Real time elapsed on the host
-sim_insts 125841424 # Number of instructions simulated
-sim_ops 152380857 # Number of ops (including micro ops) simulated
+host_inst_rate 101530 # Simulator instruction rate (inst/s)
+host_op_rate 122947 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2278332577 # Simulator tick rate (ticks/s)
+host_mem_usage 584920 # Number of bytes of host memory used
+host_seconds 1249.20 # Real time elapsed on the host
+sim_insts 126830911 # Number of instructions simulated
+sim_ops 153585651 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 9664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1676864 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 1253436 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8602112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 9344 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1671232 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 1335292 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 8458880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 217536 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 601248 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 396864 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 606496 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 432576 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12760092 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1676864 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 217536 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1894400 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8825856 # Number of bytes written to this memory
+system.physmem.bytes_read::total 12733532 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 1671232 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 217280 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1888512 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8840256 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8843600 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 151 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 26201 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 20110 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 134408 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8858000 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 146 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 26113 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 21389 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 132170 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 3399 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 9418 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 6201 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 3395 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 9500 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 6759 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 199925 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 137904 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 199510 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 138129 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 142340 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 3396 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 589200 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 440420 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 3022526 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 142565 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 3283 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 587201 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 469166 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 2972098 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 472 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 76436 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 211261 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 139446 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 76343 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 213097 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 151989 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4483516 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 589200 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 76436 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 665636 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3101143 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6221 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4474032 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 587201 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 76343 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 663544 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3106097 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6220 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3107378 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3101143 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 3396 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 589200 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 446641 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 3022526 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 3112332 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3106097 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 3283 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 587201 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 475386 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 472 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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-system.physmem.totGap 2846000520000 # Total gap between requests
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 28 # Read request sizes (log2)
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system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::96-111 33 0.51% 97.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127 29 0.44% 97.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143 13 0.20% 98.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159 13 0.20% 98.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175 4 0.06% 98.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191 22 0.34% 98.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207 18 0.28% 99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223 8 0.12% 99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239 6 0.09% 99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271 3 0.05% 99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303 3 0.05% 99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319 5 0.08% 99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335 5 0.08% 99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351 7 0.11% 99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367 9 0.14% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383 1 0.02% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399 1 0.02% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::432-447 1 0.02% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511 2 0.03% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527 2 0.03% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543 2 0.03% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559 2 0.03% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::576-591 1 0.02% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-655 1 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703 1 0.02% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::896-911 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6522 # Writes before turning the bus around for reads
-system.physmem.totQLat 5658505376 # Total ticks spent queuing
-system.physmem.totMemAccLat 9404886626 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 999035000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 28319.86 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6524 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6524 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 23.737891 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.670801 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 40.283485 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 6175 94.65% 94.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 90 1.38% 96.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63 23 0.35% 96.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79 12 0.18% 96.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 26 0.40% 96.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 32 0.49% 97.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127 26 0.40% 97.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 10 0.15% 98.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159 20 0.31% 98.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 5 0.08% 98.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 20 0.31% 98.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 23 0.35% 99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 7 0.11% 99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 7 0.11% 99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 1 0.02% 99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 3 0.05% 99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 2 0.03% 99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 5 0.08% 99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 4 0.06% 99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 4 0.06% 99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 14 0.21% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399 2 0.03% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415 1 0.02% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::464-479 1 0.02% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 2 0.03% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 3 0.05% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::576-591 1 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6524 # Writes before turning the bus around for reads
+system.physmem.totQLat 5679096455 # Total ticks spent queuing
+system.physmem.totMemAccLat 9417677705 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 996955000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 28482.21 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 47069.86 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 47232.21 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.48 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.92 # Average system write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 4.47 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing
-system.physmem.readRowHits 166469 # Number of row buffer hits during reads
-system.physmem.writeRowHits 97300 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.31 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 62.80 # Row buffer hit rate for writes
-system.physmem.avgGap 7519374.46 # Average gap between requests
-system.physmem.pageHitRate 74.35 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 351842400 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 191977500 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 804437400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 508297680 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 185886816960 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 83070715860 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1634730471750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1905544559550 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.552036 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2719396100671 # Time in different power states
-system.physmem_0.memoryStateTime::REF 95034160000 # Time in different power states
+system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing
+system.physmem.readRowHits 166067 # Number of row buffer hits during reads
+system.physmem.writeRowHits 97473 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 62.93 # Row buffer hit rate for writes
+system.physmem.avgGap 7523405.91 # Average gap between requests
+system.physmem.pageHitRate 74.39 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 359115120 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 195945750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 815841000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 515833920 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 83249453610 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1634629745250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1905658854330 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.570214 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2719227401175 # Time in different power states
+system.physmem_0.memoryStateTime::REF 95037280000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 31570722329 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 31827968825 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 335701800 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 183170625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 754049400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 495506160 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 185886816960 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 82302536835 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1635404313000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1905362094780 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.487923 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2720522847414 # Time in different power states
-system.physmem_1.memoryStateTime::REF 95034160000 # Time in different power states
+system.physmem_1.actEnergy 326697840 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 178257750 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 739401000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 487697760 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 82096607520 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1635641013750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1905362595300 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.466120 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2720918284391 # Time in different power states
+system.physmem_1.memoryStateTime::REF 95037280000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 30442207586 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 30141762609 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 20635824 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 13602989 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 1045571 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 13187813 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 9323038 # Number of BTB hits
+system.cpu0.branchPred.lookups 20630955 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 13593557 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 1040069 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 13124579 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 9315197 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 70.694345 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 3366354 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 208367 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 70.975206 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 3367508 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 204886 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 68383 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 68383 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45560 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22823 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 68383 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 68383 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 68383 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 6747 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 9430.747147 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 8234.841596 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 6251.099816 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383 6572 97.41% 97.41% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767 158 2.34% 99.75% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.10% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 6747 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 69457 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 69457 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46535 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22922 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 69457 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 69457 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 69457 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 6849 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 9469.922616 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 8283.824538 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 6457.338241 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383 6642 96.98% 96.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767 191 2.79% 99.77% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.10% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 6849 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 5180 76.77% 76.77% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1567 23.23% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 6747 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 68383 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 5259 76.78% 76.78% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1590 23.22% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 6849 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69457 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 68383 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6747 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69457 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6849 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6747 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 75130 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6849 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 76306 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 17310932 # DTB read hits
-system.cpu0.dtb.read_misses 62315 # DTB read misses
-system.cpu0.dtb.write_hits 14537397 # DTB write hits
-system.cpu0.dtb.write_misses 6068 # DTB write misses
+system.cpu0.dtb.read_hits 17312533 # DTB read hits
+system.cpu0.dtb.read_misses 63301 # DTB read misses
+system.cpu0.dtb.write_hits 14536158 # DTB write hits
+system.cpu0.dtb.write_misses 6156 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1366 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 1946 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 3522 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1254 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 1942 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 545 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 17373247 # DTB read accesses
-system.cpu0.dtb.write_accesses 14543465 # DTB write accesses
+system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 17375834 # DTB read accesses
+system.cpu0.dtb.write_accesses 14542314 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 31848329 # DTB hits
-system.cpu0.dtb.misses 68383 # DTB misses
-system.cpu0.dtb.accesses 31916712 # DTB accesses
+system.cpu0.dtb.hits 31848691 # DTB hits
+system.cpu0.dtb.misses 69457 # DTB misses
+system.cpu0.dtb.accesses 31918148 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 3838 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 3838 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3532 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 3838 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 3838 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 3838 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 2413 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 9817.861169 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 8667.312532 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 5173.169908 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191 854 35.39% 35.39% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383 1509 62.54% 97.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.12% 98.05% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767 46 1.91% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 3833 # Table walker walks requested
+system.cpu0.itb.walker.walksShort 3833 # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3526 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 3833 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 3833 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 3833 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 2419 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 9485.117817 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 8378.584027 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 4911.792845 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191 918 37.95% 37.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383 1466 60.60% 98.55% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575 5 0.21% 98.76% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767 29 1.20% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 2413 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 2419 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 2114 87.61% 87.61% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 299 12.39% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 2413 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 2119 87.60% 87.60% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M 300 12.40% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 2419 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3838 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3838 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3833 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3833 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2413 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2413 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 6251 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 38726658 # ITB inst hits
-system.cpu0.itb.inst_misses 3838 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2419 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2419 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 6252 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 38694088 # ITB inst hits
+system.cpu0.itb.inst_misses 3833 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2219 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 7377 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 7309 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 38730496 # ITB inst accesses
-system.cpu0.itb.hits 38726658 # DTB hits
-system.cpu0.itb.misses 3838 # DTB misses
-system.cpu0.itb.accesses 38730496 # DTB accesses
-system.cpu0.numCycles 164623207 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 38697921 # ITB inst accesses
+system.cpu0.itb.hits 38694088 # DTB hits
+system.cpu0.itb.misses 3833 # DTB misses
+system.cpu0.itb.accesses 38697921 # DTB accesses
+system.cpu0.numCycles 164664294 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 79533802 # Number of instructions committed
-system.cpu0.committedOps 95718607 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 5045973 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 1856 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 5527394503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.069852 # CPI: cycles per instruction
-system.cpu0.ipc 0.483126 # IPC: instructions per cycle
+system.cpu0.committedInsts 79545676 # Number of instructions committed
+system.cpu0.committedOps 95726645 # Number of ops (including micro ops) committed
+system.cpu0.discardedOps 5037895 # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends 1845 # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles 5527555817 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi 2.070060 # CPI: cycles per instruction
+system.cpu0.ipc 0.483078 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 1858 # number of quiesce instructions executed
-system.cpu0.tickCycles 128554371 # Number of cycles that the object actually ticked
-system.cpu0.idleCycles 36068836 # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements 714653 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 500.517650 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 30439123 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 715165 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 42.562378 # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce 1847 # number of quiesce instructions executed
+system.cpu0.tickCycles 127989646 # Number of cycles that the object actually ticked
+system.cpu0.idleCycles 36674648 # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements 713904 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 500.482804 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 30358451 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 714416 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 42.494080 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 348749500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.517650 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977574 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.977574 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.482804 # Average occupied blocks per requestor
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 63710880 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 63710880 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 16167111 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 16167111 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 13468154 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 13468154 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 380067 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 380067 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361342 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 361342 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 29635265 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 29635265 # number of demand (read+write) hits
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-system.cpu0.dcache.overall_hits::total 29635265 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 537159 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 537159 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 529716 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 529716 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6447 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 6447 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20264 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 20264 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1066875 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1066875 # number of demand (read+write) misses
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-system.cpu0.dcache.overall_misses::total 1066875 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6690812322 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 6690812322 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8678584493 # number of WriteReq miss cycles
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-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104630740 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 104630740 # number of LoadLockedReq miss cycles
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-system.cpu0.dcache.StoreCondReq_miss_latency::total 454305285 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 153000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 153000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 15369396815 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 15369396815 # number of demand (read+write) miss cycles
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-system.cpu0.dcache.overall_miss_latency::total 15369396815 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 16704270 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 16704270 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 13997870 # number of WriteReq accesses(hits+misses)
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-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386514 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 386514 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381606 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 381606 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 30702140 # number of demand (read+write) accesses
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-system.cpu0.dcache.overall_accesses::total 30702140 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032157 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.032157 # miss rate for ReadReq accesses
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-system.cpu0.dcache.WriteReq_miss_rate::total 0.037843 # miss rate for WriteReq accesses
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-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016680 # miss rate for LoadLockedReq accesses
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-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053102 # miss rate for StoreCondReq accesses
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-system.cpu0.dcache.demand_miss_rate::total 0.034749 # miss rate for demand accesses
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-system.cpu0.dcache.overall_miss_rate::total 0.034749 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12455.925195 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12455.925195 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16383.466788 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 16383.466788 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16229.368699 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16229.368699 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22419.329106 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22419.329106 # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses 63703980 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 63703980 # Number of data accesses
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+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386669 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 386669 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381771 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 381771 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 30240763 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 30240763 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 30698803 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 30698803 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028536 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.028536 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041250 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.041250 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298050 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298050 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054499 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054499 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053129 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053129 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034420 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.034420 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038353 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.038353 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13233.962530 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13233.962530 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15832.775675 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 15832.775675 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15072.520619 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15072.520619 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22376.288912 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22376.288912 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14405.995843 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14405.995843 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14405.995843 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14405.995843 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14675.361826 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14675.361826 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12973.755893 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 12973.755893 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 516062 # number of writebacks
-system.cpu0.dcache.writebacks::total 516062 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 42087 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 42087 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 229086 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 229086 # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 271173 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 271173 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 271173 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 271173 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 495072 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 495072 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 300630 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 300630 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6447 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6447 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20264 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 20264 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 795702 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 795702 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 795702 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 795702 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5420342985 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5420342985 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4742244244 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4742244244 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94933760 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94933760 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 423201715 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 423201715 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 147000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 147000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10162587229 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 10162587229 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10162587229 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 10162587229 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276747000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276747000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3261903001 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3261903001 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7538650001 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7538650001 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029637 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029637 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021477 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021477 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016680 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016680 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053102 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053102 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.025917 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.025917 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10948.595326 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10948.595326 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15774.354669 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15774.354669 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14725.261362 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14725.261362 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20884.411518 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.411518 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 513522 # number of writebacks
+system.cpu0.dcache.writebacks::total 513522 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 72271 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 72271 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 253439 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 253439 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14656 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14656 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 325710 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 325710 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 325710 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 325710 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391297 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 391297 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323871 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 323871 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103394 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 103394 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6417 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6417 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20283 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 20283 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 715168 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 715168 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 818562 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 818562 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4428376943 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4428376943 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4906976685 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4906976685 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1616801678 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1616801678 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 95832009 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95832009 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 422721232 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 422721232 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 436500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 436500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9335353628 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 9335353628 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10952155306 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 10952155306 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276481750 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276481750 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3261665000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3261665000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7538146750 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7538146750 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024087 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024087 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023141 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023141 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225731 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225731 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016596 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016596 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053129 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053129 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023649 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.023649 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026664 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.026664 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11317.175810 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11317.175810 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15151.022120 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15151.022120 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15637.287251 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15637.287251 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14934.082749 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14934.082749 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20841.159197 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20841.159197 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12771.850805 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12771.850805 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12771.850805 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12771.850805 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13053.371555 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13053.371555 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13379.750472 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13379.750472 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 1970130 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.783768 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 36748265 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1970642 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 18.647865 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 6452193250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.783768 # Average occupied blocks per requestor
+system.cpu0.icache.tags.replacements 1969157 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.783924 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 36716761 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 1969669 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 18.641082 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 6455779250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.783924 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999578 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 230 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 79408512 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 79408512 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 36748265 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 36748265 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 36748265 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 36748265 # number of demand (read+write) hits
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-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.035934 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.145067 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157671 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157671 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010905 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.026439 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036152 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.185051 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075961 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010905 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.026439 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036152 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.185051 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.164053 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29850.706714 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16070.247934 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39588.437872 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 24533.565603 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 32091.248642 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53498.080753 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53498.080753 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20212.609271 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20212.609271 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14702.299751 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14702.299751 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 116499 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 116499 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38767.974866 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38767.974866 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29850.706714 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16070.247934 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39588.437872 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29885.177687 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33619.682585 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29850.706714 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16070.247934 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39588.437872 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29885.177687 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53498.080753 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45630.907306 # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163120 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23400.009493 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30053.081217 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58459.199979 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58459.199979 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20172.381963 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20172.381963 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14669.747940 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14669.747940 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 345999 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 345999 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38178.292804 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38178.292804 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27791.679436 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31655.164692 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27791.679436 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58459.199979 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45977.272768 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 2704309 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 2644372 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 19133 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 19133 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 516061 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 357573 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 65952 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43054 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 89535 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 298181 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 284517 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3948091 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2342949 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11777 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 172611 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 6475428 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126338880 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86633336 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17628 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 325620 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 213315464 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 705686 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 3997625 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 3.147566 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.354669 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 2703667 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 2643606 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 19130 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 19130 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 513519 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 304285 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 88848 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42983 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 113085 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 297594 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 284124 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3946133 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2385460 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11633 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174179 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 6517405 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126276224 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86385120 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17096 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 327200 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 213005640 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 651207 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 3963380 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 3.135029 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.341755 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 3407711 85.24% 85.24% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 589914 14.76% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 3428208 86.50% 86.50% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 535172 13.50% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 3997625 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 2250942493 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 3963380 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 2258643996 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 117029497 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 116241999 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 2966538511 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 2965047043 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1219549045 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 1230256203 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 7373994 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 7364491 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 91216246 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 92392742 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 18670420 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 6078179 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 807720 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 9612678 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 6998038 # Number of BTB hits
+system.cpu1.branchPred.lookups 18842889 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 6205402 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 629106 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 9920552 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 7177439 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 72.800088 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 8300224 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 592338 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 72.349190 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 8245946 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 413041 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 26198 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 26198 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19047 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7151 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 26198 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 26198 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 26198 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 2710 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 9322.699631 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 8294.308784 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 5681.860876 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191 1066 39.34% 39.34% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1510 55.72% 95.06% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575 65 2.40% 97.45% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767 58 2.14% 99.59% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.67% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151 6 0.22% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::90112-98303 3 0.11% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 2710 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 1205143764 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 1205143764 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 1205143764 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 2001 73.84% 73.84% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 709 26.16% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 2710 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26198 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 26188 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 26188 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19132 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7056 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 26188 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 26188 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 26188 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 2719 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 9780.159618 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 8826.212048 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 5631.617808 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191 919 33.80% 33.80% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1662 61.13% 94.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575 68 2.50% 97.43% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767 62 2.28% 99.71% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.11% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.07% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 2719 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 1631340764 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 1631340764 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 1631340764 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 2011 73.96% 73.96% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 708 26.04% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 2719 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26188 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26198 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2710 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26188 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2719 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2710 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 28908 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2719 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 28907 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 10899944 # DTB read hits
-system.cpu1.dtb.read_misses 24664 # DTB read misses
-system.cpu1.dtb.write_hits 6857896 # DTB write hits
-system.cpu1.dtb.write_misses 1534 # DTB write misses
+system.cpu1.dtb.read_hits 11112548 # DTB read hits
+system.cpu1.dtb.read_misses 24192 # DTB read misses
+system.cpu1.dtb.write_hits 6961122 # DTB write hits
+system.cpu1.dtb.write_misses 1996 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2060 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 145 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 340 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2061 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 279 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 10924608 # DTB read accesses
-system.cpu1.dtb.write_accesses 6859430 # DTB write accesses
+system.cpu1.dtb.perms_faults 278 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 11136740 # DTB read accesses
+system.cpu1.dtb.write_accesses 6963118 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 17757840 # DTB hits
-system.cpu1.dtb.misses 26198 # DTB misses
-system.cpu1.dtb.accesses 17784038 # DTB accesses
+system.cpu1.dtb.hits 18073670 # DTB hits
+system.cpu1.dtb.misses 26188 # DTB misses
+system.cpu1.dtb.accesses 18099858 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 2253 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 2253 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1 177 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2076 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 2253 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 2253 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 2253 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walks 2252 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 2252 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2071 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 2252 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 2252 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 2252 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 9627.345845 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 8644.762201 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 4978.900312 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-4095 184 16.44% 16.44% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191 161 14.39% 30.83% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287 501 44.77% 75.60% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383 236 21.09% 96.69% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 96.78% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671 13 1.16% 97.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.88% 99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 9763.181412 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 8935.720507 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 4528.605471 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-4095 139 12.42% 12.42% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191 170 15.19% 27.61% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287 525 46.92% 74.53% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383 253 22.61% 97.14% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479 2 0.18% 97.32% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.88% 99.20% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.63% 99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 1204569264 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 1204569264 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 1204569264 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 955 85.34% 85.34% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 164 14.66% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walksPending::samples 1630766264 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 1630766264 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 1630766264 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 951 84.99% 84.99% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 168 15.01% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2253 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2253 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2252 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2252 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 3372 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 39818327 # ITB inst hits
-system.cpu1.itb.inst_misses 2253 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin::total 3371 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 39781680 # ITB inst hits
+system.cpu1.itb.inst_misses 2252 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1840 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1899 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 39820580 # ITB inst accesses
-system.cpu1.itb.hits 39818327 # DTB hits
-system.cpu1.itb.misses 2253 # DTB misses
-system.cpu1.itb.accesses 39820580 # DTB accesses
-system.cpu1.numCycles 115094455 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 39783932 # ITB inst accesses
+system.cpu1.itb.hits 39781680 # DTB hits
+system.cpu1.itb.misses 2252 # DTB misses
+system.cpu1.itb.accesses 39783932 # DTB accesses
+system.cpu1.numCycles 114623988 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 46307622 # Number of instructions committed
-system.cpu1.committedOps 56662250 # Number of ops (including micro ops) committed
-system.cpu1.discardedOps 4905736 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 2805 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 5576292649 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 2.485432 # CPI: cycles per instruction
-system.cpu1.ipc 0.402345 # IPC: instructions per cycle
+system.cpu1.committedInsts 47285235 # Number of instructions committed
+system.cpu1.committedOps 57859006 # Number of ops (including micro ops) committed
+system.cpu1.discardedOps 5005620 # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends 2776 # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles 5576963738 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi 2.424097 # CPI: cycles per instruction
+system.cpu1.ipc 0.412525 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2806 # number of quiesce instructions executed
-system.cpu1.tickCycles 98408596 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 16685859 # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements 195662 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 474.092793 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 17323078 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 195999 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 88.383502 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 90082708500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.092793 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925962 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.925962 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 88 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.658203 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 35540406 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 35540406 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 10562839 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 10562839 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 6561699 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 6561699 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 92378 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 92378 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71754 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 71754 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 17124538 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 17124538 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 17124538 # number of overall hits
-system.cpu1.dcache.overall_hits::total 17124538 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 188265 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 188265 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 144615 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 144615 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4906 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 4906 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23743 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 23743 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 332880 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 332880 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 332880 # number of overall misses
-system.cpu1.dcache.overall_misses::total 332880 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2782453534 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 2782453534 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3892497330 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 3892497330 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 87637747 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 87637747 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 559501111 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 559501111 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 370500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 370500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 6674950864 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 6674950864 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 6674950864 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 6674950864 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 10751104 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 10751104 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 6706314 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 6706314 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97284 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 97284 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95497 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 95497 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 17457418 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 17457418 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 17457418 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 17457418 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.017511 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.017511 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021564 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.021564 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050430 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.050430 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248626 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248626 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.019068 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.019068 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019068 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.019068 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14779.452017 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14779.452017 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26916.276527 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 26916.276527 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17863.380962 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17863.380962 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23564.886956 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23564.886956 # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce 2776 # number of quiesce instructions executed
+system.cpu1.tickCycles 97884766 # Number of cycles that the object actually ticked
+system.cpu1.idleCycles 16739222 # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements 194739 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 472.948438 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 17633406 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 195100 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 90.381374 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 90504077500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.948438 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923727 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.923727 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 55 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.705078 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 36178407 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 36178407 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 10725883 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 10725883 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 6668052 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 6668052 # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49984 # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total 49984 # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80051 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 80051 # number of LoadLockedReq hits
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+system.cpu1.dcache.StoreCondReq_hits::total 71499 # number of StoreCondReq hits
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+system.cpu1.dcache.overall_hits::total 17443919 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 157968 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 157968 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 144726 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 144726 # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30816 # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total 30816 # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16919 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 16919 # number of LoadLockedReq misses
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+system.cpu1.dcache.StoreCondReq_misses::total 23678 # number of StoreCondReq misses
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+system.cpu1.dcache.demand_misses::total 302694 # number of demand (read+write) misses
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+system.cpu1.dcache.overall_misses::total 333510 # number of overall misses
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+system.cpu1.dcache.ReadReq_miss_latency::total 2315952429 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3861386324 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 3861386324 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316030492 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 316030492 # number of LoadLockedReq miss cycles
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+system.cpu1.dcache.StoreCondReq_miss_latency::total 557062155 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 124000 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 124000 # number of StoreCondFailReq miss cycles
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+system.cpu1.dcache.demand_miss_latency::total 6177338753 # number of demand (read+write) miss cycles
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+system.cpu1.dcache.overall_miss_latency::total 6177338753 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 10883851 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 10883851 # number of ReadReq accesses(hits+misses)
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+system.cpu1.dcache.WriteReq_accesses::total 6812778 # number of WriteReq accesses(hits+misses)
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+system.cpu1.dcache.LoadLockedReq_accesses::total 96970 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu1.dcache.StoreCondReq_accesses::total 95177 # number of StoreCondReq accesses(hits+misses)
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+system.cpu1.dcache.demand_accesses::total 17696629 # number of demand (read+write) accesses
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+system.cpu1.dcache.overall_accesses::total 17777429 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014514 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.014514 # miss rate for ReadReq accesses
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+system.cpu1.dcache.WriteReq_miss_rate::total 0.021243 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381386 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381386 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174477 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174477 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248779 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248779 # miss rate for StoreCondReq accesses
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+system.cpu1.dcache.demand_miss_rate::total 0.017105 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018760 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.018760 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14660.896061 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14660.896061 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26680.667772 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 26680.667772 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18679.029021 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18679.029021 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23526.571290 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23526.571290 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20052.123480 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 20052.123480 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20052.123480 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 20052.123480 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20407.866535 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20407.866535 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18522.199493 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 18522.199493 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 120164 # number of writebacks
-system.cpu1.dcache.writebacks::total 120164 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 15759 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 15759 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52033 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 52033 # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 67792 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 67792 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 67792 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 67792 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172506 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 172506 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92582 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 92582 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4906 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4906 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23743 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 23743 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 265088 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 265088 # number of demand (read+write) MSHR misses
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-system.cpu1.dcache.overall_mshr_misses::total 265088 # number of overall MSHR misses
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-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2304438945 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2314812844 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2314812844 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 80267253 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 80267253 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 522512389 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 522512389 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 358500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 358500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4619251789 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 4619251789 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4619251789 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 4619251789 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322402500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322402500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1844154499 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1844154499 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4166556999 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166556999 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016045 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.016045 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013805 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013805 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050430 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050430 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248626 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248626 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.015185 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.015185 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015185 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.015185 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13358.601701 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13358.601701 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25002.839040 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25002.839040 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16361.038117 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16361.038117 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22007.007918 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22007.007918 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 119475 # number of writebacks
+system.cpu1.dcache.writebacks::total 119475 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16075 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 16075 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52265 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 52265 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12035 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12035 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 68340 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 68340 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 68340 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 68340 # number of overall MSHR hits
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+system.cpu1.dcache.ReadReq_mshr_misses::total 141893 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92461 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 92461 # number of WriteReq MSHR misses
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+system.cpu1.dcache.SoftPFReq_mshr_misses::total 29935 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4884 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4884 # number of LoadLockedReq MSHR misses
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+system.cpu1.dcache.StoreCondReq_mshr_misses::total 23678 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 234354 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 234354 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 264289 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 264289 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1871458583 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1871458583 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2300176813 # number of WriteReq MSHR miss cycles
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+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 487265761 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79878753 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79878753 # number of LoadLockedReq MSHR miss cycles
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+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 119500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 119500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4171635396 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 4171635396 # number of demand (read+write) MSHR miss cycles
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+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322015751 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322015751 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1843986000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1843986000 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166001751 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013037 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013037 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013572 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013572 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.370483 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.370483 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050366 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050366 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248779 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248779 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013243 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.013243 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014867 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.014867 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13189.224155 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13189.224155 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24877.265150 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24877.265150 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16277.459863 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16277.459863 # average SoftPFReq mshr miss latency
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-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17425.352294 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17425.352294 # average overall mshr miss latency
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system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
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-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8633.706071 # average overall miss latency
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system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
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system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
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-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4396.054830 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2144.688544 # Average occupied blocks per requestor
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+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1009576164 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total 3845884973 # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9469000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2205184749 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2214653749 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1754353500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1754353500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9469000 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3959538249 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3969007249 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.401845 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.080252 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.949225 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.949225 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.960241 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.960241 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.559621 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.559621 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022388 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.079186 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.021988 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.428848 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.102090 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022388 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.079186 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.021988 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.428848 # mshr miss rate for overall accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.947996 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947996 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.958863 # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.958863 # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.546801 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.546801 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439737 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.104183 # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439737 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.124466 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15397.298227 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18475.608133 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35413.300077 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35413.300077 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15957.484300 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15957.484300 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15100.211457 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15100.211457 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32362.948722 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32362.948722 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21170.759053 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22377.297493 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21170.759053 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35413.300077 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24720.789733 # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123779 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15573.986058 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18476.484941 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42252.287771 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 42252.287771 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15940.014772 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15940.014772 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15081.828305 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15081.828305 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 97000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 97000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32781.531259 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32781.531259 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21167.321458 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22327.514398 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21167.321458 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42252.287771 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25481.924738 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 1549513 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 1217389 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 11941 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 11941 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 120163 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 34752 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 76638 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42182 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 86369 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 85047 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 67036 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1899176 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 835933 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7082 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62248 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 2804439 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60773632 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25876936 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11012 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 115596 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 86777176 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 610005 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1929839 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 3.274006 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.446012 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq 1546268 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 1215347 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 11936 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 11936 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 119475 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 29668 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 76508 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42110 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 86467 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 85086 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 67037 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1896584 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 833808 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7155 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62301 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 2799848 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60690688 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25792980 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11328 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 116228 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 86611224 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 603822 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1920664 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 3.272089 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.445035 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 1401052 72.60% 72.60% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 528787 27.40% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 1398073 72.79% 72.79% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 522591 27.21% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1929839 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 840003478 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 1920664 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 837814982 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 80148998 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 80458500 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 1425055438 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 1423116171 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 412471555 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 410915491 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 4329500 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 4323500 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 33365476 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 33252737 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 31015 # Transaction distribution
-system.iobus.trans_dist::ReadResp 31015 # Transaction distribution
+system.iobus.trans_dist::ReadReq 31003 # Transaction distribution
+system.iobus.trans_dist::ReadResp 31003 # Transaction distribution
system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
system.iobus.trans_dist::WriteResp 23198 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
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-system.iocache.overall_miss_latency::total 32660377 # number of overall miss cycles
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
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system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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-system.l2c.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1024::4 29429 # Occupied blocks per task id
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17762.012109 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17818.385732 # average UpgradeReq mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.membus.trans_dist::ReadResp 215369 # Transaction distribution
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-system.membus.trans_dist::WriteResp 31074 # Transaction distribution
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+system.membus.trans_dist::WriteResp 31066 # Transaction distribution
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system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
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system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14196 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663493 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 785643 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 894551 # Packet count per connected master and slave (bytes)
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+system.membus.pkt_count_system.iocache.mem_side::total 108912 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 892875 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19286572 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 19478976 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 24114432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 124537 # Total snoops (count)
-system.membus.snoop_fanout::samples 508980 # Request fanout histogram
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+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19273388 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 19465716 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 24102196 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 123912 # Total snoops (count)
+system.membus.snoop_fanout::samples 507941 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 508980 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 507941 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 508980 # Request fanout histogram
-system.membus.reqLayer0.occupancy 88720999 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 507941 # Request fanout histogram
+system.membus.reqLayer0.occupancy 88612000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 12492999 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 12528499 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1167594605 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1167691410 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1174957130 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1172073016 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 37546467 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 37476242 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 518257 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 518242 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 31074 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 31074 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 232242 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 80802 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 41230 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 122032 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 51798 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 51798 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1084621 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 339731 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1424352 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34113464 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5575752 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 39689216 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 290726 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 922102 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.039605 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.195030 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 516720 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 516705 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 31066 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 31066 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 232835 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 79932 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 41134 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 121066 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 51762 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 51762 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1083099 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 338756 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1421855 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34093856 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5618324 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 39712180 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 288702 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 920160 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.039660 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.195160 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 885582 96.04% 96.04% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 36520 3.96% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 883666 96.03% 96.03% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 36494 3.97% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 922102 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 794355306 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 920160 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 787000770 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 342000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 683518313 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 681574777 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 260405210 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 259216519 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
ata1.00: configured for UDMA/33\r
scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)\r
+sd 0:0:0:0: Attached scsi generic sg0 type 0\r
sd 0:0:0:0: [sda] Write Protect is off\r
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-sd 0:0:0:0: Attached scsi generic sg0 type 0\r
sda: sda1\r
sd 0:0:0:0: [sda] Attached SCSI disk\r
e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
TCP: cubic registered\r
NET: Registered protocol family 10\r
NET: Registered protocol family 17\r
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 12:00:00 UTC (1230811200)\r
+rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)\r
ALSA device list:\r
No soundcards found.\r
\0input: AT Raw Set 2 keyboard as /devices/smb.14/motherboard.15/iofpga.17/1c060000.kmi/serio0/input/input0\r
\rinit started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)\r
\rstarting pid 680, tty '': '/etc/rc.d/rc.local'\r
warning: can't open /etc/mtab: No such file or directory\r
-Thu Jan 1 12:00:02 UTC 2009\r
+Thu Jan 1 00:00:02 UTC 2009\r
S: devpts\r
-Thu Jan 1 12:00:02 UTC 2009\r
+Thu Jan 1 00:00:02 UTC 2009\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM
mem_mode=timing
mem_ranges=2147483648:2415919103
-memories=system.realview.vram system.physmem system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/z/stever/hg/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 31 2014 10:01:44
-gem5 started Oct 31 2014 11:27:21
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
+gem5 compiled Mar 15 2015 20:30:55
+gem5 started Mar 15 2015 20:31:14
+gem5 executing on zizzer2
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
- 0: system.cpu.isa: ISA system set to: 0x5580680 0x5580680
+info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+ 0: system.cpu.isa: ISA system set to: 0x3fbcc30 0x3fbcc30
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
+info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: Read CNTFREQ_EL0 frequency
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2852222670000 because m5_exit instruction encountered
+Exiting @ tick 2852831758500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.853442 # Number of seconds simulated
-sim_ticks 2853442108500 # Number of ticks simulated
-final_tick 2853442108500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.852832 # Number of seconds simulated
+sim_ticks 2852831758500 # Number of ticks simulated
+final_tick 2852831758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 171765 # Simulator instruction rate (inst/s)
-host_op_rate 207684 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4374009836 # Simulator tick rate (ticks/s)
-host_mem_usage 619996 # Number of bytes of host memory used
-host_seconds 652.36 # Real time elapsed on the host
-sim_insts 112053421 # Number of instructions simulated
-sim_ops 135485276 # Number of ops (including micro ops) simulated
+host_inst_rate 111123 # Simulator instruction rate (inst/s)
+host_op_rate 134357 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2834419538 # Simulator tick rate (ticks/s)
+host_mem_usage 554504 # Number of bytes of host memory used
+host_seconds 1006.50 # Real time elapsed on the host
+sim_insts 111845135 # Number of instructions simulated
+sim_ops 135229426 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 7296 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 7744 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1671680 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9169380 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1669888 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9170532 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10849380 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1671680 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1671680 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7972992 # Number of bytes written to this memory
+system.physmem.bytes_read::total 10849188 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1669888 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1669888 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7971008 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7990516 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 114 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 7988532 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 121 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 26120 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 143791 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 26092 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 143809 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 170041 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 124578 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 170038 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 124547 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 128959 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 2557 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 128928 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 2714 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 585847 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3213445 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3802208 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 585847 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 585847 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2794166 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 6141 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2800308 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2794166 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 2557 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 585344 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3214537 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3802954 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 585344 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 585344 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2794069 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2800211 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2794069 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 2714 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 585847 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3219587 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6602516 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 170041 # Number of read requests accepted
-system.physmem.writeReqs 165183 # Number of write requests accepted
-system.physmem.readBursts 170041 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 165183 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10875008 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9072064 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10849380 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 10308852 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 23407 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4604 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 10431 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10779 # Per bank write bursts
-system.physmem.perBankRdBursts::2 11040 # Per bank write bursts
-system.physmem.perBankRdBursts::3 10735 # Per bank write bursts
-system.physmem.perBankRdBursts::4 13061 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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-system.physmem.totGap 2853441702500 # Total gap between requests
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 541 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::mean 322.802648 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 189.147121 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 338.470119 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22296 36.08% 36.08% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::256-383 6637 10.74% 70.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3539 5.73% 75.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2616 4.23% 80.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1600 2.59% 82.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1149 1.86% 84.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1212 1.96% 86.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8279 13.40% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 61793 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 28.927818 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 584.509202 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 5873 99.98% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::224-239 6 0.10% 99.03% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::672-687 1 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703 1 0.02% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5873 # Writes before turning the bus around for reads
-system.physmem.totQLat 1685079736 # Total ticks spent queuing
-system.physmem.totMemAccLat 4871117236 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 849610000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9916.78 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::240-255 2 0.03% 99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 2 0.03% 99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 4 0.07% 99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 7 0.12% 99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 3 0.05% 99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 2 0.03% 99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 6 0.10% 99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 9 0.15% 99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 2 0.03% 99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415 3 0.05% 99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::464-479 2 0.03% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511 2 0.03% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 1 0.02% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 5 0.08% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559 2 0.03% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::560-575 5 0.08% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads
+system.physmem.totQLat 1723441444 # Total ticks spent queuing
+system.physmem.totMemAccLat 4909966444 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 849740000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10140.99 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28666.78 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 28890.99 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW 3.17 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing
-system.physmem.readRowHits 140217 # Number of row buffer hits during reads
-system.physmem.writeRowHits 109661 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 27.38 # Average write queue length when enqueuing
+system.physmem.readRowHits 140236 # Number of row buffer hits during reads
+system.physmem.writeRowHits 109426 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.52 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 77.35 # Row buffer hit rate for writes
-system.physmem.avgGap 8512044.79 # Average gap between requests
+system.physmem.writeRowHitRate 77.36 # Row buffer hit rate for writes
+system.physmem.avgGap 8511087.30 # Average gap between requests
system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 242267760 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 132189750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 692507400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 468860400 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 83617160895 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1638712655250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1910238133215 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.452112 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2726011845150 # Time in different power states
-system.physmem_0.memoryStateTime::REF 95282460000 # Time in different power states
+system.physmem_0.actEnergy 243129600 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 132660000 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 692905200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 468925200 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 83554754445 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1638403001250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1909828199775 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.450935 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2725489926444 # Time in different power states
+system.physmem_0.memoryStateTime::REF 95262180000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 32147776350 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 32075649806 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 224857080 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 122689875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 632876400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 449634240 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 82395435150 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1639784344500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1909982329005 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.362464 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2727805815350 # Time in different power states
-system.physmem_1.memoryStateTime::REF 95282460000 # Time in different power states
+system.physmem_1.actEnergy 223413120 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 121902000 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 632681400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 447521760 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 82328316795 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1639478823750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1909565482905 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.358845 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2727297379194 # Time in different power states
+system.physmem_1.memoryStateTime::REF 95262180000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 30353736650 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 30272102306 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 31053109 # Number of BP lookups
-system.cpu.branchPred.condPredicted 16852863 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2525514 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 18620216 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 13364906 # Number of BTB hits
+system.cpu.branchPred.lookups 31016169 # Number of BP lookups
+system.cpu.branchPred.condPredicted 16821620 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2509164 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 18454178 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 13299317 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 71.776321 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 7853668 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1516989 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 72.066699 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 7885459 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1501288 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 65844 # Table walker walks requested
-system.cpu.dtb.walker.walksShort 65844 # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43330 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22514 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples 65844 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 65844 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 65844 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 7786 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 11086.116106 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 8821.657087 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 7338.018596 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-16383 6073 78.00% 78.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::16384-32767 1707 21.92% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks 66365 # Table walker walks requested
+system.cpu.dtb.walker.walksShort 66365 # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43579 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22786 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples 66365 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0 66365 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 66365 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 7796 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 11013.949461 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 8730.002722 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 7624.437396 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-16383 6093 78.16% 78.16% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::16384-32767 1696 21.75% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::163840-180223 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 7786 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::229376-245759 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 7796 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 6400 82.20% 82.20% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M 1386 17.80% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 7786 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65844 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::4K 6406 82.17% 82.17% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M 1390 17.83% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 7796 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66365 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65844 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7786 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66365 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7796 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7786 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 73630 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7796 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 74161 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 24757406 # DTB read hits
-system.cpu.dtb.read_misses 59085 # DTB read misses
-system.cpu.dtb.write_hits 19449348 # DTB write hits
-system.cpu.dtb.write_misses 6759 # DTB write misses
+system.cpu.dtb.read_hits 24709745 # DTB read hits
+system.cpu.dtb.read_misses 59626 # DTB read misses
+system.cpu.dtb.write_hits 19412201 # DTB write hits
+system.cpu.dtb.write_misses 6739 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4357 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 1268 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 1766 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 4351 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 1292 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 1782 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 739 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 24816491 # DTB read accesses
-system.cpu.dtb.write_accesses 19456107 # DTB write accesses
+system.cpu.dtb.perms_faults 733 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 24769371 # DTB read accesses
+system.cpu.dtb.write_accesses 19418940 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 44206754 # DTB hits
-system.cpu.dtb.misses 65844 # DTB misses
-system.cpu.dtb.accesses 44272598 # DTB accesses
+system.cpu.dtb.hits 44121946 # DTB hits
+system.cpu.dtb.misses 66365 # DTB misses
+system.cpu.dtb.accesses 44188311 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 5446 # Table walker walks requested
-system.cpu.itb.walker.walksShort 5446 # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2 5122 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples 5446 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 5446 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 5446 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 3184 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 11253.454774 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 8989.562910 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 7050.042435 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-8191 1281 40.23% 40.23% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::8192-16383 1185 37.22% 77.45% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-24575 717 22.52% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks 5448 # Table walker walks requested
+system.cpu.itb.walker.walksShort 5448 # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1 319 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2 5129 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0 5448 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 3189 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 11214.016933 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 8947.518192 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 7056.251032 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191 1295 40.61% 40.61% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383 1177 36.91% 77.52% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575 716 22.45% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 3184 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 3189 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 2875 90.30% 90.30% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M 309 9.70% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 3184 # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::4K 2879 90.28% 90.28% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M 310 9.72% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 3189 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5446 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 5446 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5448 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 5448 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3184 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 3184 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 8630 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 57726188 # ITB inst hits
-system.cpu.itb.inst_misses 5446 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3189 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 3189 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 8637 # Table walker requests started/completed, data/inst
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system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2973 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2978 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 8450 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 8467 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 57731634 # ITB inst accesses
-system.cpu.itb.hits 57726188 # DTB hits
-system.cpu.itb.misses 5446 # DTB misses
-system.cpu.itb.accesses 57731634 # DTB accesses
-system.cpu.numCycles 317415724 # number of cpu cycles simulated
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+system.cpu.itb.accesses 57594097 # DTB accesses
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 112053421 # Number of instructions committed
-system.cpu.committedOps 135485276 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 7764036 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts 111845135 # Number of instructions committed
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system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles 5389516808 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi 2.832718 # CPI: cycles per instruction
-system.cpu.ipc 0.353018 # IPC: instructions per cycle
+system.cpu.quiesceCycles 5390158471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
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+system.cpu.ipc 0.354427 # IPC: instructions per cycle
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed
-system.cpu.tickCycles 228406815 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 89008909 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 842109 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.947879 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 42706608 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 842621 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 50.683057 # Average number of references to valid blocks.
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+system.cpu.dcache.tags.replacements 842581 # number of replacements
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+system.cpu.dcache.tags.avg_refs 50.455122 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.947879 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu.dcache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 176191359 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 176191359 # Number of data accesses
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system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.writebacks::total 697919 # number of writebacks
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system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
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system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68000 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68000 # average SCUpgradeReq mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.cpu.toL2Bus.trans_dist::ReadReq 3579627 # Transaction distribution
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system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
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system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
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system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
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system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
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system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
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-system.membus.trans_dist::ReadResp 71726 # Transaction distribution
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+system.membus.trans_dist::ReadExReq 129383 # Transaction distribution
+system.membus.trans_dist::ReadExResp 129383 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446695 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554255 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446633 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554193 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 663142 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 663080 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16522776 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16686485 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16520600 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16684309 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 21321941 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 504 # Total snoops (count)
-system.membus.snoop_fanout::samples 332271 # Request fanout histogram
+system.membus.pkt_size::total 21319765 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 505 # Total snoops (count)
+system.membus.snoop_fanout::samples 332236 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 332271 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 332236 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 332271 # Request fanout histogram
-system.membus.reqLayer0.occupancy 90362500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 332236 # Request fanout histogram
+system.membus.reqLayer0.occupancy 90365500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1704000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1715000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1022735199 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1025055153 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 997821410 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 997764949 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 37468495 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 37471493 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
TCP: cubic registered\r
NET: Registered protocol family 10\r
NET: Registered protocol family 17\r
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 12:00:00 UTC (1230811200)\r
+rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)\r
ALSA device list:\r
No soundcards found.\r
\0input: AT Raw Set 2 keyboard as /devices/smb.14/motherboard.15/iofpga.17/1c060000.kmi/serio0/input/input0\r
\rinit started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)\r
\rstarting pid 673, tty '': '/etc/rc.d/rc.local'\r
warning: can't open /etc/mtab: No such file or directory\r
-Thu Jan 1 12:00:02 UTC 2009\r
+Thu Jan 1 00:00:02 UTC 2009\r
S: devpts\r
-Thu Jan 1 12:00:02 UTC 2009\r
+Thu Jan 1 00:00:02 UTC 2009\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/dist/m5/system/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/dist/m5/system/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/dist/m5/system/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM64
mem_mode=timing
mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.vram system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/z/stever/hg/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/dist/m5/system/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu0.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu0.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu0.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu0.l2cache.tags]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
[system.cpu0.tracer]
type=ExeTracer
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu1.toL2Bus.slave[5]
[system.cpu1.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu1.toL2Bus.slave[4]
[system.cpu1.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu1.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu1.l2cache.tags]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
[system.cpu1.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 29 2014 09:18:22
-gem5 started Oct 29 2014 10:35:48
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
+gem5 compiled Mar 15 2015 20:30:55
+gem5 started Mar 15 2015 20:31:14
+gem5 executing on zizzer2
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
- 0: system.cpu0.isa: ISA system set to: 0x5394b00 0x5394b00
- 0: system.cpu1.isa: ISA system set to: 0x5394b00 0x5394b00
+info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu0.isa: ISA system set to: 0x3d33a20 0x3d33a20
+ 0: system.cpu1.isa: ISA system set to: 0x3d33a20 0x3d33a20
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 47349475204500 because m5_exit instruction encountered
+Exiting @ tick 47397610926500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 47.357291 # Number of seconds simulated
-sim_ticks 47357290872500 # Number of ticks simulated
-final_tick 47357290872500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.397611 # Number of seconds simulated
+sim_ticks 47397610926500 # Number of ticks simulated
+final_tick 47397610926500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 179609 # Simulator instruction rate (inst/s)
-host_op_rate 211253 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9509351214 # Simulator tick rate (ticks/s)
-host_mem_usage 764316 # Number of bytes of host memory used
-host_seconds 4980.08 # Real time elapsed on the host
-sim_insts 894465242 # Number of instructions simulated
-sim_ops 1052057457 # Number of ops (including micro ops) simulated
+host_inst_rate 110253 # Simulator instruction rate (inst/s)
+host_op_rate 129665 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5829907242 # Simulator tick rate (ticks/s)
+host_mem_usage 703216 # Number of bytes of host memory used
+host_seconds 8130.08 # Real time elapsed on the host
+sim_insts 896366789 # Number of instructions simulated
+sim_ops 1054186264 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 141696 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 131328 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 8696576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 13989464 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 21378112 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 133248 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 113344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3297088 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 7559072 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 13082368 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 433472 # Number of bytes read from this memory
-system.physmem.bytes_read::total 68955768 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 8696576 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 3297088 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 11993664 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 79042240 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 107072 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 78336 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 7782464 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 12802520 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 15762560 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 159744 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 154688 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 3994240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 12481056 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 14503040 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 448448 # Number of bytes read from this memory
+system.physmem.bytes_read::total 68274168 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 7782464 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 3994240 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 11776704 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 79542656 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 79063056 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 2214 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2052 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
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system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 260 # Number of times write queue was full causing retry
-system.physmem.totGap 47357288950000 # Total gap between requests
+system.physmem.numWrRetry 309 # Number of times write queue was full causing retry
+system.physmem.totGap 47397609004000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 37 # Read request sizes (log2)
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2601 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::samples 1066280 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 176.199272 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 107.583604 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 245.477591 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 681708 63.93% 63.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 204893 19.22% 83.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 51569 4.84% 87.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 24658 2.31% 90.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 19159 1.80% 92.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 12349 1.16% 93.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8689 0.81% 94.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 7706 0.72% 94.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 55549 5.21% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1066280 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 82344 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 13.080819 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 137.450182 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 82341 100.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15 44683 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 64606 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::30 102100 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::48 3166 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 2471 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 1786 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::52 1195 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::56 725 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 739 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 598 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 535 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 533 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 628 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 443 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 770 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 1060336 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 176.818458 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 107.808098 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 246.499626 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 676218 63.77% 63.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 204682 19.30% 83.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 51639 4.87% 87.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 24739 2.33% 90.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 18449 1.74% 92.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 11998 1.13% 93.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 8607 0.81% 93.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 7827 0.74% 94.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 56177 5.30% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1060336 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 82745 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 12.888404 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 137.186201 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 82742 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 82344 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 82344 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 22.569343 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 19.983627 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 21.346474 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31 74619 90.62% 90.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47 3701 4.49% 95.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63 1617 1.96% 97.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79 776 0.94% 98.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95 389 0.47% 98.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111 290 0.35% 98.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127 467 0.57% 99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143 184 0.22% 99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159 57 0.07% 99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175 20 0.02% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191 62 0.08% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207 36 0.04% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223 12 0.01% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239 4 0.00% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255 2 0.00% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271 2 0.00% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287 5 0.01% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303 3 0.00% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319 10 0.01% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335 13 0.02% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351 9 0.01% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367 24 0.03% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399 5 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415 3 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431 3 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::432-447 1 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-463 1 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479 3 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 82745 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 82745 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 22.515342 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 19.971264 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 20.554947 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 75024 90.67% 90.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 3669 4.43% 95.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63 1611 1.95% 97.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79 792 0.96% 98.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 419 0.51% 98.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 279 0.34% 98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127 435 0.53% 99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 203 0.25% 99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159 68 0.08% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 22 0.03% 99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 73 0.09% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 36 0.04% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 10 0.01% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 7 0.01% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 4 0.00% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 3 0.00% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 1 0.00% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 7 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 9 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 7 0.01% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 11 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 22 0.03% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 7 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415 4 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527 5 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543 4 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559 3 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::576-591 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703 3 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 5 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::560-575 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::576-591 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::592-607 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::656-671 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 82344 # Writes before turning the bus around for reads
-system.physmem.totQLat 41096385470 # Total ticks spent queuing
-system.physmem.totMemAccLat 61293060470 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 5385780000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 38152.68 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::720-735 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 82745 # Writes before turning the bus around for reads
+system.physmem.totQLat 40375015102 # Total ticks spent queuing
+system.physmem.totMemAccLat 60371177602 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 5332310000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 37858.84 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 56902.68 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.46 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.51 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.46 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 56608.84 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.52 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.47 # Average write queue length when enqueuing
-system.physmem.readRowHits 809420 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1059902 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.14 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 57.03 # Row buffer hit rate for writes
-system.physmem.avgGap 15866789.39 # Average gap between requests
-system.physmem.pageHitRate 63.68 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 4185760320 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2283897000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4164435600 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 6207198480 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3093147866640 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1197399382470 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27364022846250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31671411386760 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.775859 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45522011263316 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1581363940000 # Time in different power states
+system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.99 # Average write queue length when enqueuing
+system.physmem.readRowHits 803348 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1065807 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 75.33 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 57.21 # Row buffer hit rate for writes
+system.physmem.avgGap 15910609.09 # Average gap between requests
+system.physmem.pageHitRate 63.80 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 4142388600 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 2260231875 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 4140419400 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 6138335520 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3095781190320 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1201204741230 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27384875125500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 31698542432445 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.779401 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 45556660870724 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1582710220000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 253913912184 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 258234748026 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 3875316480 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2114508000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4237256400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 5835557520 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3093147866640 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1190113153695 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27370414275000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31669737933735 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.740522 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45532636458203 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1581363940000 # Time in different power states
+system.physmem_1.actEnergy 3873751560 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 2113654125 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 4177906200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 5934111840 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3095781190320 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1188231262785 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 27396255369750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 31696367246580 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.733509 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 45575630122499 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1582710220000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 243288251797 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 239268979001 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 151571686 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 107212809 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 6769997 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 114323741 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 82790418 # Number of BTB hits
+system.cpu0.branchPred.lookups 133516333 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 94941201 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 6028887 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 100948341 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 73074204 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 72.417520 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 17895403 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 1177591 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 72.387722 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 15498997 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 1074405 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 310912 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 310912 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11841 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90150 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 310912 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 310912 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 310912 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 101991 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 19193.830760 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 17232.192163 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 15084.416179 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 100737 98.77% 98.77% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1058 1.04% 99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 37 0.04% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 76 0.07% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 58 0.06% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 274493 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 274493 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8574 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 74935 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 274493 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 274493 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 274493 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 83509 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 18665.041972 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 16952.057368 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 12810.377808 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 82824 99.18% 99.18% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 578 0.69% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 32 0.04% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 36 0.04% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 27 0.03% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 101991 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 83509 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 90150 88.39% 88.39% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 11841 11.61% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 101991 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 310912 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 74935 89.73% 89.73% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 8574 10.27% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 83509 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 274493 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 310912 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101991 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 274493 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 83509 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101991 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 412903 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 83509 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 358002 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 98035121 # DTB read hits
-system.cpu0.dtb.read_misses 261233 # DTB read misses
-system.cpu0.dtb.write_hits 86222704 # DTB write hits
-system.cpu0.dtb.write_misses 49679 # DTB write misses
+system.cpu0.dtb.read_hits 84777209 # DTB read hits
+system.cpu0.dtb.read_misses 227212 # DTB read misses
+system.cpu0.dtb.write_hits 75760151 # DTB write hits
+system.cpu0.dtb.write_misses 47281 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 42277 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 2349 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 10561 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 33980 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 2153 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 9225 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 12531 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 98296354 # DTB read accesses
-system.cpu0.dtb.write_accesses 86272383 # DTB write accesses
+system.cpu0.dtb.perms_faults 11068 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 85004421 # DTB read accesses
+system.cpu0.dtb.write_accesses 75807432 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 184257825 # DTB hits
-system.cpu0.dtb.misses 310912 # DTB misses
-system.cpu0.dtb.accesses 184568737 # DTB accesses
+system.cpu0.dtb.hits 160537360 # DTB hits
+system.cpu0.dtb.misses 274493 # DTB misses
+system.cpu0.dtb.accesses 160811853 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 67664 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 67664 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 693 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59407 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 67664 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 67664 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 67664 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 60100 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 21688.993677 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 19128.313408 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 17789.670668 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767 55182 91.82% 91.82% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535 3533 5.88% 97.70% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303 493 0.82% 98.52% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071 740 1.23% 99.75% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.03% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607 25 0.04% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375 48 0.08% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143 24 0.04% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679 15 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 60100 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 61212 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 61212 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 587 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52411 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 61212 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 61212 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 61212 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 52998 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 21062.649289 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 19099.820516 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 14417.313367 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767 48615 91.73% 91.73% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535 3682 6.95% 98.68% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303 228 0.43% 99.11% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071 379 0.72% 99.82% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.04% 99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375 22 0.04% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911 7 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679 9 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 52998 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 59407 98.85% 98.85% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 693 1.15% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 60100 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 52411 98.89% 98.89% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 587 1.11% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 52998 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 67664 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 67664 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61212 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61212 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60100 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60100 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 127764 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 272362835 # ITB inst hits
-system.cpu0.itb.inst_misses 67664 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52998 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52998 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 114210 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 238748421 # ITB inst hits
+system.cpu0.itb.inst_misses 61212 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 29878 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 24001 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 206888 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 196095 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 272430499 # ITB inst accesses
-system.cpu0.itb.hits 272362835 # DTB hits
-system.cpu0.itb.misses 67664 # DTB misses
-system.cpu0.itb.accesses 272430499 # DTB accesses
-system.cpu0.numCycles 1079786982 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 238809633 # ITB inst accesses
+system.cpu0.itb.hits 238748421 # DTB hits
+system.cpu0.itb.misses 61212 # DTB misses
+system.cpu0.itb.accesses 238809633 # DTB accesses
+system.cpu0.numCycles 949769690 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 504924574 # Number of instructions committed
-system.cpu0.committedOps 592395738 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 49310302 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 4906 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 93635655345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.138511 # CPI: cycles per instruction
-system.cpu0.ipc 0.467615 # IPC: instructions per cycle
+system.cpu0.committedInsts 439719858 # Number of instructions committed
+system.cpu0.committedOps 516807751 # Number of ops (including micro ops) committed
+system.cpu0.discardedOps 45409758 # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends 3855 # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles 93846100118 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi 2.159943 # CPI: cycles per instruction
+system.cpu0.ipc 0.462975 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 13863 # number of quiesce instructions executed
-system.cpu0.tickCycles 807512344 # Number of cycles that the object actually ticked
-system.cpu0.idleCycles 272274638 # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements 6269899 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 502.388707 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 174903450 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 6270410 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 27.893463 # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce 12790 # number of quiesce instructions executed
+system.cpu0.tickCycles 712933683 # Number of cycles that the object actually ticked
+system.cpu0.idleCycles 236836007 # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements 5519291 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 480.702778 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 152151321 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 5519802 # Sample count of references to valid blocks.
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 33958968357 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1816137650 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1816137650 # number of LoadLockedReq MSHR miss cycles
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-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3868892109 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2341500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2341500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 80025073061 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5766564749 # number of ReadReq MSHR uncacheable cycles
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-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.043034 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043034 # mshr miss rate for ReadReq accesses
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-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018093 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.754546 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.754546 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.067900 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.067900 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095826 # mshr miss rate for StoreCondReq accesses
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-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13198.751645 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13198.751645 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17520.593206 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17520.593206 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39268.456339 # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39268.456339 # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12907.505472 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12907.505472 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19498.007353 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19498.007353 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 3800112 # number of writebacks
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+system.cpu0.dcache.ReadReq_mshr_hits::total 429398 # number of ReadReq MSHR hits
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+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12965.456147 # average ReadReq mshr miss latency
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+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22414.083927 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39823.524219 # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39823.524219 # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12825.797597 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12825.797597 # average LoadLockedReq mshr miss latency
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system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
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-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14357.621160 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14357.621160 # average overall mshr miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 10307657 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.930132 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 261841431 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 10308169 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 25.401352 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 23262861250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930132 # Average occupied blocks per requestor
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+system.cpu0.icache.tags.tagsinuse 511.930140 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 229100961 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 9445413 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 24.255261 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 24039613250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930140 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 249 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu0.icache.tags.data_accesses 554607398 # Number of data accesses
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-system.cpu0.icache.ReadReq_hits::total 261841431 # number of ReadReq hits
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-system.cpu0.icache.ReadReq_miss_latency::total 103403812050 # number of ReadReq miss cycles
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-system.cpu0.icache.overall_miss_latency::total 103403812050 # number of overall miss cycles
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-system.cpu0.icache.ReadReq_miss_rate::total 0.037877 # miss rate for ReadReq accesses
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-system.cpu0.icache.demand_miss_rate::total 0.037877 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037877 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.037877 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10031.239470 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10031.239470 # average ReadReq miss latency
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-system.cpu0.icache.demand_avg_miss_latency::total 10031.239470 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10031.239470 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10031.239470 # average overall miss latency
+system.cpu0.icache.tags.tag_accesses 486538188 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 486538188 # Number of data accesses
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+system.cpu0.icache.ReadReq_hits::total 229100961 # number of ReadReq hits
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+system.cpu0.icache.overall_hits::total 229100961 # number of overall hits
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+system.cpu0.icache.overall_misses::total 9445422 # number of overall misses
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system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
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system.cpu0.l2cache.tags.warmup_cycle 5822698500 # Cycle when the warmup percentage was hit.
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+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.538902 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.817105 # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.817105 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.210133 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.210133 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021620 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.051384 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.083404 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192091 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.117225 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021620 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.051384 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.083404 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192091 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.224862 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.224862 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023759 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052115 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080130 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256301 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.135114 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023759 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052115 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080130 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256301 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.186936 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 29763.331275 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26938.772911 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44997.202450 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 44997.202450 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43674.769924 # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43674.769924 # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20418.408310 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20418.408310 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15115.924084 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15115.924084 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 389899.600000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 389899.600000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41290.896998 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41290.896998 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32716.022553 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28945.720413 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32716.022553 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44997.202450 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34931.503009 # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.184057 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26709.503385 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25473.948849 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 52502.734204 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 52502.734204 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43489.607650 # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43489.607650 # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20266.143903 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20266.143903 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14939.483112 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14939.483112 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1165000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1165000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39938.078665 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39938.078665 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29497.482424 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27348.089069 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29497.482424 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 52502.734204 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34037.079428 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 17791242 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 15586246 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 31969 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 31969 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 4374599 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 1496771 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1185210 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 863337 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 459789 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 354172 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 478714 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1428335 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1300035 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20720970 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18253192 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 368054 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1214499 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 40556715 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 663070976 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 695774006 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1328184 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4426744 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1364599910 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 5020747 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 27005623 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 3.173372 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.378569 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 16517621 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 14068332 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 33225 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 33225 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 3800110 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 1086057 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1148168 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 786224 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 477409 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 332434 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 482483 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1303516 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1171227 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18995457 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16182353 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 335795 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1061304 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 36574909 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 607854592 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 610383865 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1223600 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3866424 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1223328481 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 4849156 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 24579773 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 3.184734 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.388082 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 22323591 82.66% 82.66% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 4682032 17.34% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 20039056 81.53% 81.53% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 4540717 18.47% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 27005623 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 16474086937 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 24579773 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 14682015163 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 218344490 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 205334987 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 15570026567 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 14272912820 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 9017811583 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 7968080178 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 202360718 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 183071466 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 661550198 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 578323929 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 120391711 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 86208358 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 5520869 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 91435615 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 66348303 # Number of BTB hits
+system.cpu1.branchPred.lookups 139172899 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 99233401 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 6252869 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 105205307 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 76618629 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 72.562866 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 13861535 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 936317 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 72.827722 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 16237430 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 1026400 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 259478 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 259478 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8847 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 78200 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 259478 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 259478 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 259478 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 87047 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 19103.472745 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17330.859199 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 14131.069495 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767 82878 95.21% 95.21% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535 3197 3.67% 98.88% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303 459 0.53% 99.41% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071 357 0.41% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839 35 0.04% 99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607 16 0.02% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375 26 0.03% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143 18 0.02% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911 28 0.03% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679 18 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 87047 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 492358444 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 492358444 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 492358444 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 78200 89.84% 89.84% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 8847 10.16% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 87047 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 259478 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 295412 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 295412 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11437 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91734 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 295412 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 295412 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 295412 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 103171 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 19450.829041 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 17494.566732 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15964.350233 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 101752 98.62% 98.62% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1198 1.16% 99.79% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 37 0.04% 99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 80 0.08% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 73 0.07% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 103171 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 1267166444 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 1267166444 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 1267166444 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 91734 88.91% 88.91% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 11437 11.09% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 103171 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 295412 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 259478 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87047 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 295412 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 103171 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87047 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 346525 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 103171 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 398583 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 76628852 # DTB read hits
-system.cpu1.dtb.read_misses 212787 # DTB read misses
-system.cpu1.dtb.write_hits 67332330 # DTB write hits
-system.cpu1.dtb.write_misses 46691 # DTB write misses
+system.cpu1.dtb.read_hits 90130445 # DTB read hits
+system.cpu1.dtb.read_misses 246227 # DTB read misses
+system.cpu1.dtb.write_hits 78064785 # DTB write hits
+system.cpu1.dtb.write_misses 49185 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 32755 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 660 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 6687 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 41873 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 864 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 7939 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 10091 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 76841639 # DTB read accesses
-system.cpu1.dtb.write_accesses 67379021 # DTB write accesses
+system.cpu1.dtb.perms_faults 11435 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 90376672 # DTB read accesses
+system.cpu1.dtb.write_accesses 78113970 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 143961182 # DTB hits
-system.cpu1.dtb.misses 259478 # DTB misses
-system.cpu1.dtb.accesses 144220660 # DTB accesses
+system.cpu1.dtb.hits 168195230 # DTB hits
+system.cpu1.dtb.misses 295412 # DTB misses
+system.cpu1.dtb.accesses 168490642 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 59975 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 59975 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 467 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50555 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 59975 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 59975 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 59975 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 51022 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 21947.479421 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 19426.626910 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 17730.380785 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 49865 97.73% 97.73% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 1035 2.03% 99.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.09% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 47 0.09% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 12 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks 68039 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 68039 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 556 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57997 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 68039 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 68039 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 68039 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 58553 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 22020.763957 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 19263.180418 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 18942.782929 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 56928 97.22% 97.22% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 1459 2.49% 99.72% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 45 0.08% 99.79% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 89 0.15% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 13 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 51022 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 491673944 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 491673944 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 491673944 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 50555 99.08% 99.08% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 467 0.92% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 51022 # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::total 58553 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 1266435944 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 1266435944 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 1266435944 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 57997 99.05% 99.05% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 556 0.95% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 58553 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59975 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59975 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68039 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 68039 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51022 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51022 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 110997 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 214508261 # ITB inst hits
-system.cpu1.itb.inst_misses 59975 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58553 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58553 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 126592 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 249268487 # ITB inst hits
+system.cpu1.itb.inst_misses 68039 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 23598 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 30522 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 213038 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 226060 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 214568236 # ITB inst accesses
-system.cpu1.itb.hits 214508261 # DTB hits
-system.cpu1.itb.misses 59975 # DTB misses
-system.cpu1.itb.accesses 214568236 # DTB accesses
-system.cpu1.numCycles 819770260 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 249336526 # ITB inst accesses
+system.cpu1.itb.hits 249268487 # DTB hits
+system.cpu1.itb.misses 68039 # DTB misses
+system.cpu1.itb.accesses 249336526 # DTB accesses
+system.cpu1.numCycles 932637373 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 389540668 # Number of instructions committed
-system.cpu1.committedOps 459661719 # Number of ops (including micro ops) committed
-system.cpu1.discardedOps 43651844 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 5040 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 93895466763 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 2.104454 # CPI: cycles per instruction
-system.cpu1.ipc 0.475183 # IPC: instructions per cycle
+system.cpu1.committedInsts 456646931 # Number of instructions committed
+system.cpu1.committedOps 537378513 # Number of ops (including micro ops) committed
+system.cpu1.discardedOps 48077866 # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends 5781 # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles 93863478723 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi 2.042360 # CPI: cycles per instruction
+system.cpu1.ipc 0.489630 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 5089 # number of quiesce instructions executed
-system.cpu1.tickCycles 643812229 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 175958031 # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements 4705434 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 416.508572 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 136862260 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 4705946 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 29.082837 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8379321114000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.508572 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.813493 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.813493 # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce 5811 # number of quiesce instructions executed
+system.cpu1.tickCycles 738281563 # Number of cycles that the object actually ticked
+system.cpu1.idleCycles 194355810 # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements 5504177 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 462.121005 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 159889231 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 5504689 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 29.046006 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 8380046591500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 462.121005 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.902580 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.902580 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 290353323 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 290353323 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 70292866 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 70292866 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 62721831 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 62721831 # number of WriteReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 37138 # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total 37138 # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1710890 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1710890 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1626994 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 1626994 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 133014697 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 133014697 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 133014697 # number of overall hits
-system.cpu1.dcache.overall_hits::total 133014697 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 3624776 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 3624776 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 2086736 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 2086736 # number of WriteReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 382666 # number of WriteInvalidateReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::total 382666 # number of WriteInvalidateReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 105529 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 105529 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 188259 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 188259 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 5711512 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 5711512 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 5711512 # number of overall misses
-system.cpu1.dcache.overall_misses::total 5711512 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 50593739173 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 50593739173 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 36769582633 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 36769582633 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 10366896775 # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 10366896775 # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 1534806603 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 1534806603 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3974138991 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 3974138991 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3324999 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3324999 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 87363321806 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 87363321806 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 87363321806 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 87363321806 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 73917642 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 73917642 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 64808567 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 64808567 # number of WriteReq accesses(hits+misses)
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-system.cpu1.dcache.WriteInvalidateReq_accesses::total 419804 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1816419 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 1816419 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1815253 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 1815253 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 138726209 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 138726209 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 138726209 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 138726209 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049038 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.049038 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032198 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.032198 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.911535 # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.911535 # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.058097 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.058097 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103710 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103710 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041171 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.041171 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041171 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.041171 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13957.756058 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13957.756058 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17620.620257 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 17620.620257 # average WriteReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27091.240860 # average WriteInvalidateReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27091.240860 # average WriteInvalidateReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14543.932028 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14543.932028 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21109.954855 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21109.954855 # average StoreCondReq miss latency
+system.cpu1.dcache.tags.tag_accesses 339217340 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 339217340 # Number of data accesses
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+system.cpu1.dcache.ReadReq_misses::total 3601145 # number of ReadReq misses
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+system.cpu1.dcache.SoftPFReq_misses::total 662253 # number of SoftPFReq misses
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+system.cpu1.dcache.WriteInvalidateReq_misses::total 453115 # number of WriteInvalidateReq misses
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+system.cpu1.dcache.LoadLockedReq_misses::total 186074 # number of LoadLockedReq misses
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+system.cpu1.dcache.demand_misses::total 5901783 # number of demand (read+write) misses
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+system.cpu1.dcache.ReadReq_miss_latency::total 55051091271 # number of ReadReq miss cycles
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+system.cpu1.dcache.WriteReq_miss_latency::total 39953352540 # number of WriteReq miss cycles
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+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3321500 # number of StoreCondFailReq miss cycles
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+system.cpu1.dcache.SoftPFReq_accesses::total 896349 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 528553 # number of WriteInvalidateReq accesses(hits+misses)
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+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2030433 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu1.dcache.overall_accesses::total 162224916 # number of overall (read+write) accesses
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+system.cpu1.dcache.ReadReq_miss_rate::total 0.041802 # miss rate for ReadReq accesses
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+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.738834 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.857274 # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.857274 # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091643 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091643 # miss rate for LoadLockedReq accesses
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+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095496 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036582 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.036582 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040463 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.040463 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15287.107648 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15287.107648 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17366.205609 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 17366.205609 # average WriteReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28309.237935 # average WriteInvalidateReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 28309.237935 # average WriteInvalidateReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15232.772596 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15232.772596 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20661.064859 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20661.064859 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15296.005997 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15296.005997 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15296.005997 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15296.005997 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16097.583359 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 16097.583359 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14473.480007 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14473.480007 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 3043303 # number of writebacks
-system.cpu1.dcache.writebacks::total 3043303 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 326021 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 326021 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 860988 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 860988 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 76 # number of WriteInvalidateReq MSHR hits
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-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 32 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 32 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 53 # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 1187009 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 1187009 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 1187009 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 1187009 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3298755 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 3298755 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1225748 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 1225748 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 382590 # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 382590 # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 105497 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 105497 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 188206 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 188206 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 4524503 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 4524503 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 4524503 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 4524503 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40628902084 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40628902084 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20156955784 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20156955784 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9784547475 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 9784547475 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1375359879 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1375359879 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3682414982 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3682414982 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2828501 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2828501 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60785857868 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 60785857868 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 60785857868 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 60785857868 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 684362251 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 684362251 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 814922500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 814922500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1499284751 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1499284751 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044627 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044627 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018913 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018913 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.911354 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.911354 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058080 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058080 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103680 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103680 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032615 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.032615 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032615 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.032615 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12316.435165 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12316.435165 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16444.616499 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16444.616499 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25574.498745 # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25574.498745 # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13036.957250 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13036.957250 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19565.874531 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19565.874531 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 3506045 # number of writebacks
+system.cpu1.dcache.writebacks::total 3506045 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 409825 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 409825 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 940543 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 940543 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 72 # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 72 # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45181 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45181 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 47 # number of StoreCondReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::total 47 # number of StoreCondReq MSHR hits
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+system.cpu1.dcache.demand_mshr_hits::total 1350368 # number of demand (read+write) MSHR hits
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+system.cpu1.dcache.overall_mshr_hits::total 1350368 # number of overall MSHR hits
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+system.cpu1.dcache.ReadReq_mshr_misses::total 3191320 # number of ReadReq MSHR misses
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+system.cpu1.dcache.WriteReq_mshr_misses::total 1360095 # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 661949 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 661949 # number of SoftPFReq MSHR misses
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+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 453043 # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 140893 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 140893 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193713 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 193713 # number of StoreCondReq MSHR misses
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+system.cpu1.dcache.demand_mshr_misses::total 4551415 # number of demand (read+write) MSHR misses
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+system.cpu1.dcache.overall_mshr_misses::total 5213364 # number of overall MSHR misses
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+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42631813644 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22019784779 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22019784779 # number of WriteReq MSHR miss cycles
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+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13605448576 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12141090903 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12141090903 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1806083972 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1806083972 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3702335044 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3702335044 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2795500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2795500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 64651598423 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 64651598423 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 78257046999 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 78257046999 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 498907500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 498907500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 556628501 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 556628501 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1055536001 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1055536001 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037045 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037045 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.738495 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.738495 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.857138 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.857138 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069391 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069391 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095472 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095472 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028212 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.028212 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032137 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.032137 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13358.677176 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13358.677176 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16189.887309 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16189.887309 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20553.620560 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20553.620560 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26798.981340 # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26798.981340 # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12818.833952 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12818.833952 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19112.475900 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19112.475900 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13434.814358 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13434.814358 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13434.814358 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13434.814358 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14204.724997 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14204.724997 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15010.854220 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15010.854220 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 8513181 # number of replacements
-system.cpu1.icache.tags.tagsinuse 507.039853 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 205775695 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 8513693 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 24.169969 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 8369241421000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.039853 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990312 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.990312 # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements 9392574 # number of replacements
+system.cpu1.icache.tags.tagsinuse 507.206734 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 239643264 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 9393086 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 25.512730 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 8370013399000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.206734 # Average occupied blocks per requestor
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+system.cpu1.icache.tags.occ_percent::total 0.990638 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 437092471 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 437092471 # Number of data accesses
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-system.cpu1.icache.ReadReq_hits::total 205775695 # number of ReadReq hits
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-system.cpu1.icache.overall_hits::total 205775695 # number of overall hits
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-system.cpu1.icache.ReadReq_misses::total 8513694 # number of ReadReq misses
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-system.cpu1.icache.demand_misses::total 8513694 # number of demand (read+write) misses
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-system.cpu1.icache.overall_misses::total 8513694 # number of overall misses
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-system.cpu1.icache.ReadReq_miss_latency::total 84159322077 # number of ReadReq miss cycles
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-system.cpu1.icache.demand_miss_latency::total 84159322077 # number of demand (read+write) miss cycles
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-system.cpu1.icache.overall_miss_latency::total 84159322077 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 214289389 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 214289389 # number of ReadReq accesses(hits+misses)
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-system.cpu1.icache.demand_accesses::total 214289389 # number of demand (read+write) accesses
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-system.cpu1.icache.overall_accesses::total 214289389 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039730 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.039730 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039730 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.039730 # miss rate for demand accesses
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-system.cpu1.icache.overall_miss_rate::total 0.039730 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9885.171123 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 9885.171123 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9885.171123 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 9885.171123 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9885.171123 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 9885.171123 # average overall miss latency
+system.cpu1.icache.tags.tag_accesses 507465788 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 507465788 # Number of data accesses
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+system.cpu1.icache.ReadReq_hits::total 239643264 # number of ReadReq hits
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+system.cpu1.icache.overall_miss_latency::total 93629377858 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 249036351 # number of ReadReq accesses(hits+misses)
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+system.cpu1.icache.overall_accesses::total 249036351 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037718 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.037718 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037718 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.037718 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037718 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.037718 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9967.902763 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 9967.902763 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9967.902763 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 9967.902763 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9967.902763 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 9967.902763 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
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-system.cpu1.icache.ReadReq_mshr_misses::total 8513694 # number of ReadReq MSHR misses
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+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.249486 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.138603 # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.249486 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191906 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 23524.613506 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23038.594142 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36143.355229 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36143.355229 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30445.827572 # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30445.827572 # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19406.762982 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19406.762982 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14569.405435 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14569.405435 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 393582.833333 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 393582.833333 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31760.741811 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31760.741811 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25647.897107 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24293.872687 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25647.897107 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36143.355229 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28557.983969 # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186252 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26660.088082 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25037.672304 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46384.470766 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46384.470766 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32812.266011 # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32812.266011 # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19486.318153 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19486.318153 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14796.710109 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14796.710109 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 261333.333333 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261333.333333 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33792.425824 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33792.425824 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27982.771658 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26022.436146 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27982.771658 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46384.470766 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31231.631271 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 15445485 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 12769085 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 6630 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 6630 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 3043303 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 1203167 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1105360 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 381381 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 459466 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 345603 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 466676 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1177489 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1018273 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17027569 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13630896 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 329758 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1060916 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 32049139 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 544882176 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 508019480 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1204400 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3883720 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1057989776 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 5539420 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 22773399 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 3.231012 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.421480 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq 16687989 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 14334572 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 4962 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 4962 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 3506045 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 1053826 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1133141 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 451918 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 452249 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 341136 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 469204 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1304040 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1151075 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18786353 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15676887 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371904 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1206650 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 36041794 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 601163264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 587975003 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1349240 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4407712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 1194895219 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 5002181 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 24473447 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 3.192626 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.394362 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 17512462 76.90% 76.90% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 5260937 23.10% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 19759234 80.74% 80.74% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 4714213 19.26% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 22773399 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 12190933688 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 24473447 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 13845201909 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 175938985 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 163397980 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 12781364350 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 14102728136 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 7076644304 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 8209870082 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 179556153 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 203661942 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 575808723 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 656138927 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40350 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40350 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136657 # Transaction distribution
-system.iobus.trans_dist::WriteResp 29929 # Transaction distribution
+system.iobus.trans_dist::ReadReq 40316 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40316 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136601 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29873 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47838 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47648 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122720 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231214 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231214 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122530 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231224 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231224 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 354014 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47858 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47668 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155850 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338872 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7338872 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155660 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338912 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7338912 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7496808 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 7496658 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36180000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 607629108 # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy 607453407 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
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+system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.190900 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.212817 # mshr miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.765143 # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.484776 # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.678929 # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.600521 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.586709 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.593738 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.596623 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.586703 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.591741 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.575848 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.512878 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.547492 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.196315 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.203255 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.091569 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.238947 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.232334 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.231370 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.196315 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.203255 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.091569 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.238947 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.232334 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.231370 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80848.279354 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77016.382199 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 99617.771443 # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33583.928144 # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32063.710201 # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33250.137211 # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17840.886677 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17796.886334 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17819.536552 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17860.137471 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.412203 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17840.755008 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77480.654562 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72287.514629 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 75289.979524 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79571.498531 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75673.036756 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 96426.453406 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79571.498531 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75673.036756 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 96426.453406 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 988965 # Transaction distribution
-system.membus.trans_dist::ReadResp 988965 # Transaction distribution
-system.membus.trans_dist::WriteReq 38599 # Transaction distribution
-system.membus.trans_dist::WriteResp 38599 # Transaction distribution
-system.membus.trans_dist::Writeback 1235035 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 669572 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 669572 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 443245 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 300309 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 118634 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution
-system.membus.trans_dist::ReadExReq 147271 # Transaction distribution
-system.membus.trans_dist::ReadExResp 130046 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122720 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 979077 # Transaction distribution
+system.membus.trans_dist::ReadResp 979077 # Transaction distribution
+system.membus.trans_dist::WriteReq 38187 # Transaction distribution
+system.membus.trans_dist::WriteResp 38187 # Transaction distribution
+system.membus.trans_dist::Writeback 1242854 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 666717 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 666717 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 428866 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 287024 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 113399 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution
+system.membus.trans_dist::ReadExReq 145453 # Transaction distribution
+system.membus.trans_dist::ReadExResp 128623 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122530 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26568 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5280771 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 5430111 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335842 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 335842 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5765953 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155850 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25066 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5227832 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 5375480 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336065 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 336065 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5711545 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155660 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53136 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 176778952 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 176989262 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14092480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 14092480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 191081742 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 645066 # Total snoops (count)
-system.membus.snoop_fanout::samples 3693594 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50132 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 176401096 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 176608212 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14106432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14106432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 190714644 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 622043 # Total snoops (count)
+system.membus.snoop_fanout::samples 3659684 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3693594 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3659684 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3693594 # Request fanout histogram
-system.membus.reqLayer0.occupancy 110078000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3659684 # Request fanout histogram
+system.membus.reqLayer0.occupancy 109555497 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 22086998 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 20982498 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 11288947920 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 11300972211 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 6557942197 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 6484776493 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 151922124 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 151978377 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 5164890 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 5157651 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38599 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38599 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 2504876 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 938982 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp 832112 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 498168 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 313155 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 811323 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 114 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 303337 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 303337 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8953428 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6273029 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 15226457 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 302864374 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 197929240 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 500793614 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1680481 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 9632863 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.012020 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.108976 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 5072106 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 5064869 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38187 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38187 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 2487202 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 936242 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 829317 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 482057 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 299353 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 781410 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 127 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 300573 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 300573 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8029813 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6984147 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 15013960 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 269549433 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 226408539 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 495957972 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1618057 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 9487188 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.012211 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.109827 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 9517074 98.80% 98.80% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 115789 1.20% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 9371339 98.78% 98.78% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 115849 1.22% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 9632863 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 8806822228 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 9487188 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 8381122122 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2518500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 2527500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 5125474266 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 4575963989 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4045471741 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4435446795 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000019] Console: colour dummy device 80x25\r
-[ 0.000021] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000022] pid_max: default: 32768 minimum: 301\r
-[ 0.000033] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000034] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000131] hw perfevents: no hardware support available\r
-[ 0.060036] CPU1: Booted secondary processor\r
-[ 1.080071] CPU2: failed to come online\r
-[ 2.100137] CPU3: failed to come online\r
-[ 2.100139] Brought up 2 CPUs\r
-[ 2.100140] SMP: Total of 2 processors activated.\r
-[ 2.100190] devtmpfs: initialized\r
-[ 2.100793] atomic64_test: passed\r
-[ 2.100838] regulator-dummy: no parameters\r
-[ 2.101214] NET: Registered protocol family 16\r
-[ 2.101343] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 2.101351] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 2.101748] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 2.101750] Serial: AMBA PL011 UART driver\r
-[ 2.101922] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 2.101956] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 2.102494] console [ttyAMA0] enabled\r
-[ 2.102553] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 2.102585] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 2.102617] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 2.102647] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 2.140272] 3V3: 3300 mV \r
-[ 2.140314] vgaarb: loaded\r
-[ 2.140359] SCSI subsystem initialized\r
-[ 2.140388] libata version 3.00 loaded.\r
-[ 2.140440] usbcore: registered new interface driver usbfs\r
-[ 2.140458] usbcore: registered new interface driver hub\r
-[ 2.140480] usbcore: registered new device driver usb\r
-[ 2.140506] pps_core: LinuxPPS API ver. 1 registered\r
-[ 2.140514] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 2.140532] PTP clock support registered\r
-[ 2.140657] Switched to clocksource arch_sys_counter\r
-[ 2.141767] NET: Registered protocol family 2\r
-[ 2.141832] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 2.141848] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 2.141863] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 2.141883] TCP: reno registered\r
-[ 2.141889] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.141901] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.141933] NET: Registered protocol family 1\r
-[ 2.141985] RPC: Registered named UNIX socket transport module.\r
-[ 2.141995] RPC: Registered udp transport module.\r
-[ 2.142003] RPC: Registered tcp transport module.\r
-[ 2.142011] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 2.142022] PCI: CLS 0 bytes, default 64\r
-[ 2.142178] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 2.142262] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 2.144252] fuse init (API version 7.23)\r
-[ 2.144348] msgmni has been set to 469\r
-[ 2.144441] io scheduler noop registered\r
-[ 2.144502] io scheduler cfq registered (default)\r
-[ 2.144877] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 2.144889] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 2.144900] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 2.144912] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 2.144921] pci_bus 0000:00: scanning bus\r
-[ 2.144930] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 2.144942] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 2.144956] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.144993] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 2.145004] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 2.145014] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 2.145025] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 2.145035] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 2.145045] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 2.145056] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.145094] pci_bus 0000:00: fixups for bus\r
-[ 2.145101] pci_bus 0000:00: bus scan returning with max=00\r
-[ 2.145112] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 2.145130] pci 0000:00:00.0: fixup irq: got 33\r
-[ 2.145138] pci 0000:00:00.0: assigning IRQ 33\r
-[ 2.145148] pci 0000:00:01.0: fixup irq: got 34\r
-[ 2.145156] pci 0000:00:01.0: assigning IRQ 34\r
-[ 2.145166] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 2.145178] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 2.145191] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 2.145203] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 2.145214] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 2.145225] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 2.145236] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 2.145246] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 2.145736] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 2.145999] ata_piix 0000:00:01.0: version 2.13\r
-[ 2.146009] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 2.146029] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 2.146283] scsi0 : ata_piix\r
-[ 2.146361] scsi1 : ata_piix\r
-[ 2.146393] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 2.146405] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 2.146514] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 2.146526] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 2.146540] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 2.146551] e1000 0000:00:00.0: enabling bus mastering\r
-[ 2.290688] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 2.290697] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 2.290723] ata1.00: configured for UDMA/33\r
-[ 2.290764] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 2.290877] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 2.290883] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 2.290933] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 2.290942] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 2.290962] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 2.291097] sda: sda1\r
-[ 2.291216] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 2.410964] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 2.410977] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 2.411000] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 2.411009] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 2.411031] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 2.411042] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 2.411120] usbcore: registered new interface driver usb-storage\r
-[ 2.411175] mousedev: PS/2 mouse device common for all mice\r
-[ 2.411347] usbcore: registered new interface driver usbhid\r
-[ 2.411357] usbhid: USB HID core driver\r
-[ 2.411384] TCP: cubic registered\r
-[ 2.411391] NET: Registered protocol family 17\r
-\0[ 2.411706] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 2.411738] devtmpfs: mounted\r
-[ 2.411771] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 0.000024] Console: colour dummy device 80x25\r
+[ 0.000026] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000028] pid_max: default: 32768 minimum: 301\r
+[ 0.000040] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000041] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000162] hw perfevents: no hardware support available\r
+[ 0.060041] CPU1: Booted secondary processor\r
+[ 1.080077] CPU2: failed to come online\r
+[ 2.100147] CPU3: failed to come online\r
+[ 2.100150] Brought up 2 CPUs\r
+[ 2.100151] SMP: Total of 2 processors activated.\r
+[ 2.100222] devtmpfs: initialized\r
+[ 2.100720] atomic64_test: passed\r
+[ 2.100765] regulator-dummy: no parameters\r
+[ 2.101110] NET: Registered protocol family 16\r
+[ 2.101240] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 2.101248] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 2.101774] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 2.101778] Serial: AMBA PL011 UART driver\r
+[ 2.101977] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 2.102014] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 2.102559] console [ttyAMA0] enabled\r
+[ 2.102714] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 2.102776] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 2.102840] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 2.102896] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 2.140326] 3V3: 3300 mV \r
+[ 2.140386] vgaarb: loaded\r
+[ 2.140451] SCSI subsystem initialized\r
+[ 2.140500] libata version 3.00 loaded.\r
+[ 2.140582] usbcore: registered new interface driver usbfs\r
+[ 2.140606] usbcore: registered new interface driver hub\r
+[ 2.140634] usbcore: registered new device driver usb\r
+[ 2.140679] pps_core: LinuxPPS API ver. 1 registered\r
+[ 2.140690] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 2.140713] PTP clock support registered\r
+[ 2.140890] Switched to clocksource arch_sys_counter\r
+[ 2.142410] NET: Registered protocol family 2\r
+[ 2.142497] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 2.142513] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 2.142530] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 2.142553] TCP: reno registered\r
+[ 2.142559] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.142571] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.142606] NET: Registered protocol family 1\r
+[ 2.142648] RPC: Registered named UNIX socket transport module.\r
+[ 2.142658] RPC: Registered udp transport module.\r
+[ 2.142666] RPC: Registered tcp transport module.\r
+[ 2.142674] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 2.142686] PCI: CLS 0 bytes, default 64\r
+[ 2.142917] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 2.143025] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 2.145169] fuse init (API version 7.23)\r
+[ 2.145284] msgmni has been set to 469\r
+[ 2.145389] io scheduler noop registered\r
+[ 2.145440] io scheduler cfq registered (default)\r
+[ 2.145841] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 2.145854] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 2.145865] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 2.145877] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 2.145887] pci_bus 0000:00: scanning bus\r
+[ 2.145897] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 2.145910] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 2.145924] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.145958] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 2.145969] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 2.145980] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 2.145990] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 2.146000] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 2.146011] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 2.146022] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.146056] pci_bus 0000:00: fixups for bus\r
+[ 2.146064] pci_bus 0000:00: bus scan returning with max=00\r
+[ 2.146076] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 2.146095] pci 0000:00:00.0: fixup irq: got 33\r
+[ 2.146103] pci 0000:00:00.0: assigning IRQ 33\r
+[ 2.146113] pci 0000:00:01.0: fixup irq: got 34\r
+[ 2.146121] pci 0000:00:01.0: assigning IRQ 34\r
+[ 2.146133] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 2.146145] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 2.146158] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 2.146170] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 2.146181] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 2.146192] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 2.146203] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 2.146214] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 2.146861] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 2.147132] ata_piix 0000:00:01.0: version 2.13\r
+[ 2.147142] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 2.147165] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 2.147427] scsi0 : ata_piix\r
+[ 2.147508] scsi1 : ata_piix\r
+[ 2.147536] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 2.147548] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 2.147650] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 2.147662] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 2.147676] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 2.147687] e1000 0000:00:00.0: enabling bus mastering\r
+[ 2.290931] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 2.290941] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 2.290968] ata1.00: configured for UDMA/33\r
+[ 2.291021] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 2.291157] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 2.291201] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 2.291210] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 2.291229] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 2.291303] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 2.291385] sda: sda1\r
+[ 2.291511] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 2.411191] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 2.411204] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 2.411225] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 2.411235] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 2.411255] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 2.411267] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 2.411336] usbcore: registered new interface driver usb-storage\r
+[ 2.411399] mousedev: PS/2 mouse device common for all mice\r
+[ 2.411553] usbcore: registered new interface driver usbhid\r
+[ 2.411563] usbhid: USB HID core driver\r
+[ 2.411592] TCP: cubic registered\r
+[ 2.411599] NET: Registered protocol family 17\r
+\0[ 2.411953] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 2.411989] devtmpfs: mounted\r
+[ 2.412026] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 2.449963] udevd[609]: starting version 182\r
+[ 2.450394] udevd[609]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 2.513292] random: dd urandom read with 17 bits of entropy available\r
+[ 2.513589] random: dd urandom read with 17 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 2.640887] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 2.641120] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/dist/m5/system/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/dist/m5/system/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/dist/m5/system/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM64
mem_mode=timing
mem_ranges=2147483648:2415919103
-memories=system.realview.vram system.physmem system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/z/stever/hg/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/dist/m5/system/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 29 2014 09:18:22
-gem5 started Oct 29 2014 10:29:11
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor
+gem5 compiled Mar 15 2015 20:30:55
+gem5 started Mar 15 2015 20:31:14
+gem5 executing on zizzer2
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
- 0: system.cpu.isa: ISA system set to: 0x5c61b00 0x5c61b00
+info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu.isa: ISA system set to: 0x404afc0 0x404afc0
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 51727209160500 because m5_exit instruction encountered
+Exiting @ tick 51609998980000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 51.690388 # Number of seconds simulated
-sim_ticks 51690388482000 # Number of ticks simulated
-final_tick 51690388482000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 51.609999 # Number of seconds simulated
+sim_ticks 51609998980000 # Number of ticks simulated
+final_tick 51609998980000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 185969 # Simulator instruction rate (inst/s)
-host_op_rate 218525 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 10104822635 # Simulator tick rate (ticks/s)
-host_mem_usage 719212 # Number of bytes of host memory used
-host_seconds 5115.42 # Real time elapsed on the host
-sim_insts 951311494 # Number of instructions simulated
-sim_ops 1117847862 # Number of ops (including micro ops) simulated
+host_inst_rate 125549 # Simulator instruction rate (inst/s)
+host_op_rate 147521 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6837484784 # Simulator tick rate (ticks/s)
+host_mem_usage 653616 # Number of bytes of host memory used
+host_seconds 7548.10 # Real time elapsed on the host
+sim_insts 947659008 # Number of instructions simulated
+sim_ops 1113505098 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 413184 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 346752 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 10436032 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 67415176 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 415104 # Number of bytes read from this memory
-system.physmem.bytes_read::total 79026248 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 10436032 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 10436032 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 95778368 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 398592 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 332160 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 10228032 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 65553800 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 419072 # Number of bytes read from this memory
+system.physmem.bytes_read::total 76931656 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 10228032 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 10228032 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 93992704 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 95798948 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 6456 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 5418 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 163063 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1053375 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6486 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1234798 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1496537 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 94013284 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 6228 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 5190 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 159813 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1024291 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6548 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1202070 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1468636 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1499110 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 7993 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 6708 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 201895 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1304211 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8031 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1528838 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 201895 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 201895 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1852924 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1853322 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1852924 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 7993 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 6708 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 201895 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1304609 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8031 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3382161 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1234798 # Number of read requests accepted
-system.physmem.writeReqs 2155868 # Number of write requests accepted
-system.physmem.readBursts 1234798 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 2155868 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 78985984 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 41088 # Total number of bytes read from write queue
-system.physmem.bytesWritten 134775168 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 79026248 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 137831460 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 642 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 49988 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 39660 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 74085 # Per bank write bursts
-system.physmem.perBankRdBursts::1 76722 # Per bank write bursts
-system.physmem.perBankRdBursts::2 75273 # Per bank write bursts
-system.physmem.perBankRdBursts::3 67779 # Per bank write bursts
-system.physmem.perBankRdBursts::4 73670 # Per bank write bursts
-system.physmem.perBankRdBursts::5 87218 # Per bank write bursts
-system.physmem.perBankRdBursts::6 75623 # Per bank write bursts
-system.physmem.perBankRdBursts::7 75034 # Per bank write bursts
-system.physmem.perBankRdBursts::8 70647 # Per bank write bursts
-system.physmem.perBankRdBursts::9 127770 # Per bank write bursts
-system.physmem.perBankRdBursts::10 77193 # Per bank write bursts
-system.physmem.perBankRdBursts::11 73706 # Per bank write bursts
-system.physmem.perBankRdBursts::12 69495 # Per bank write bursts
-system.physmem.perBankRdBursts::13 70758 # Per bank write bursts
-system.physmem.perBankRdBursts::14 68705 # Per bank write bursts
-system.physmem.perBankRdBursts::15 70478 # Per bank write bursts
-system.physmem.perBankWrBursts::0 131375 # Per bank write bursts
-system.physmem.perBankWrBursts::1 133100 # Per bank write bursts
-system.physmem.perBankWrBursts::2 134570 # Per bank write bursts
-system.physmem.perBankWrBursts::3 130352 # Per bank write bursts
-system.physmem.perBankWrBursts::4 132576 # Per bank write bursts
-system.physmem.perBankWrBursts::5 140660 # Per bank write bursts
-system.physmem.perBankWrBursts::6 130709 # Per bank write bursts
-system.physmem.perBankWrBursts::7 134220 # Per bank write bursts
-system.physmem.perBankWrBursts::8 130946 # Per bank write bursts
-system.physmem.perBankWrBursts::9 136651 # Per bank write bursts
-system.physmem.perBankWrBursts::10 131424 # Per bank write bursts
-system.physmem.perBankWrBursts::11 131217 # Per bank write bursts
-system.physmem.perBankWrBursts::12 125851 # Per bank write bursts
-system.physmem.perBankWrBursts::13 128099 # Per bank write bursts
-system.physmem.perBankWrBursts::14 126227 # Per bank write bursts
-system.physmem.perBankWrBursts::15 127885 # Per bank write bursts
+system.physmem.num_writes::total 1471209 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 7723 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 6436 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 198179 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1270176 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8120 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1490635 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 198179 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 198179 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1821211 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1821610 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1821211 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 7723 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 6436 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 198179 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1270575 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8120 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3312245 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1202070 # Number of read requests accepted
+system.physmem.writeReqs 2120779 # Number of write requests accepted
+system.physmem.readBursts 1202070 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 2120779 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 76896960 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 35520 # Total number of bytes read from write queue
+system.physmem.bytesWritten 132496640 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 76931656 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 135585764 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 50494 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 39336 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 72977 # Per bank write bursts
+system.physmem.perBankRdBursts::1 77412 # Per bank write bursts
+system.physmem.perBankRdBursts::2 73227 # Per bank write bursts
+system.physmem.perBankRdBursts::3 70716 # Per bank write bursts
+system.physmem.perBankRdBursts::4 69716 # Per bank write bursts
+system.physmem.perBankRdBursts::5 78531 # Per bank write bursts
+system.physmem.perBankRdBursts::6 70002 # Per bank write bursts
+system.physmem.perBankRdBursts::7 72888 # Per bank write bursts
+system.physmem.perBankRdBursts::8 66687 # Per bank write bursts
+system.physmem.perBankRdBursts::9 126636 # Per bank write bursts
+system.physmem.perBankRdBursts::10 72169 # Per bank write bursts
+system.physmem.perBankRdBursts::11 76842 # Per bank write bursts
+system.physmem.perBankRdBursts::12 69750 # Per bank write bursts
+system.physmem.perBankRdBursts::13 69617 # Per bank write bursts
+system.physmem.perBankRdBursts::14 66498 # Per bank write bursts
+system.physmem.perBankRdBursts::15 67847 # Per bank write bursts
+system.physmem.perBankWrBursts::0 128572 # Per bank write bursts
+system.physmem.perBankWrBursts::1 129591 # Per bank write bursts
+system.physmem.perBankWrBursts::2 133621 # Per bank write bursts
+system.physmem.perBankWrBursts::3 133794 # Per bank write bursts
+system.physmem.perBankWrBursts::4 127990 # Per bank write bursts
+system.physmem.perBankWrBursts::5 135547 # Per bank write bursts
+system.physmem.perBankWrBursts::6 129190 # Per bank write bursts
+system.physmem.perBankWrBursts::7 132517 # Per bank write bursts
+system.physmem.perBankWrBursts::8 125103 # Per bank write bursts
+system.physmem.perBankWrBursts::9 133352 # Per bank write bursts
+system.physmem.perBankWrBursts::10 128272 # Per bank write bursts
+system.physmem.perBankWrBursts::11 129497 # Per bank write bursts
+system.physmem.perBankWrBursts::12 125797 # Per bank write bursts
+system.physmem.perBankWrBursts::13 127747 # Per bank write bursts
+system.physmem.perBankWrBursts::14 124476 # Per bank write bursts
+system.physmem.perBankWrBursts::15 125194 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 155 # Number of times write queue was full causing retry
-system.physmem.totGap 51690386784000 # Total gap between requests
+system.physmem.numWrRetry 166 # Number of times write queue was full causing retry
+system.physmem.totGap 51609997338500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 2 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1234783 # Read request sizes (log2)
+system.physmem.readPktSize::6 1202055 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 2153295 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1198377 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 29223 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 559 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 277 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 484 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 543 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 471 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 778 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 497 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1896 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 2118206 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1132428 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 62352 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 724 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 310 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 460 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 547 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 490 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 762 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 454 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1875 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 234 # What read queue length does an incoming req see
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-system.physmem.bytesPerActivate::mean 289.702517 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1024-1151 84430 11.44% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 737863 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes
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-system.physmem.totQLat 16140892467 # Total ticks spent queuing
-system.physmem.totMemAccLat 39281317467 # Total ticks spent from burst creation until serviced by the DRAM
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-system.physmem.avgQLat 13078.49 # Average queueing delay per DRAM burst
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+system.physmem.wrPerTurnAround::total 99482 # Writes before turning the bus around for reads
+system.physmem.totQLat 16741886044 # Total ticks spent queuing
+system.physmem.totMemAccLat 39270292294 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 6007575000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 13933.98 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31828.49 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.53 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.61 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 32683.98 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.49 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.57 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.49 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing
-system.physmem.readRowHits 952465 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1649689 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 77.18 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 78.34 # Row buffer hit rate for writes
-system.physmem.avgGap 15244906.69 # Average gap between requests
-system.physmem.pageHitRate 77.91 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 2866207680 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1563903000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4722104400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 6917801760 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3376164558000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1320834277260 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 29855603520000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 34568672372100 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.764092 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 49666580122402 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1726055500000 # Time in different power states
+system.physmem.avgWrQLen 24.76 # Average write queue length when enqueuing
+system.physmem.readRowHits 927538 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1623609 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 77.20 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 78.42 # Row buffer hit rate for writes
+system.physmem.avgGap 15531851.53 # Average gap between requests
+system.physmem.pageHitRate 77.97 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 2802990960 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1529409750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 4566611400 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 6809326560 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3370914184560 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1308588544890 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 29818114243500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34513325311620 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.733317 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 49604286854347 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1723371260000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 297752382598 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 282340388153 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 2712036600 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1479781875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4904265600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 6728184000 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3376164558000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1311236111385 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29864022963750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34567247901210 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.736534 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 49680605946994 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1726055500000 # Time in different power states
+system.physmem_1.actEnergy 2644949160 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1443176625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 4805158800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 6605958240 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3370914184560 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1300507873200 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29825202552000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34512123852585 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.710038 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 49616091454429 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1723371260000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 283722031756 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 270535519321 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 261231631 # Number of BP lookups
-system.cpu.branchPred.condPredicted 183305796 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 12196019 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 193363774 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 136711559 # Number of BTB hits
+system.cpu.branchPred.lookups 260066829 # Number of BP lookups
+system.cpu.branchPred.condPredicted 182351604 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 12179122 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 192997810 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 135975989 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 70.701743 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 31664930 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 2143732 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 70.454680 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 31593975 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 2147293 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 585994 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 585994 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2 21793 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191747 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples 585994 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 585994 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 585994 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 213540 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 24710.005137 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 20824.581984 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 15872.776829 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767 123160 57.68% 57.68% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-65535 87731 41.08% 98.76% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-98303 1449 0.68% 99.44% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::98304-131071 786 0.37% 99.81% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-163839 33 0.02% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::163840-196607 127 0.06% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-229375 51 0.02% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::229376-262143 62 0.03% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-294911 77 0.04% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::294912-327679 22 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-360447 20 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::360448-393215 10 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-491519 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 213540 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks 583127 # Table walker walks requested
+system.cpu.dtb.walker.walksLong 583127 # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22581 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191165 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples 583127 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0 583127 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 583127 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 213746 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 24576.454072 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 20707.683114 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 15710.461946 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535 211230 98.82% 98.82% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071 2148 1.00% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607 131 0.06% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143 118 0.06% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679 73 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 213746 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples -15748296 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 -15748296 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total -15748296 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 191748 89.79% 89.79% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M 21793 10.21% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 213541 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 585994 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::4K 191166 89.44% 89.44% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M 22581 10.56% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 213747 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 583127 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 585994 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213541 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 583127 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213747 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213541 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 799535 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213747 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 796874 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 183604569 # DTB read hits
-system.cpu.dtb.read_misses 484391 # DTB read misses
-system.cpu.dtb.write_hits 162970808 # DTB write hits
-system.cpu.dtb.write_misses 101603 # DTB write misses
+system.cpu.dtb.read_hits 182952995 # DTB read hits
+system.cpu.dtb.read_misses 481784 # DTB read misses
+system.cpu.dtb.write_hits 162354187 # DTB write hits
+system.cpu.dtb.write_misses 101343 # DTB write misses
system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 47405 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 80226 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 794 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 14405 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid 47075 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 80213 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 854 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 14789 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 23565 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 184088960 # DTB read accesses
-system.cpu.dtb.write_accesses 163072411 # DTB write accesses
+system.cpu.dtb.perms_faults 23472 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 183434779 # DTB read accesses
+system.cpu.dtb.write_accesses 162455530 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 346575377 # DTB hits
-system.cpu.dtb.misses 585994 # DTB misses
-system.cpu.dtb.accesses 347161371 # DTB accesses
+system.cpu.dtb.hits 345307182 # DTB hits
+system.cpu.dtb.misses 583127 # DTB misses
+system.cpu.dtb.accesses 345890309 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 136676 # Table walker walks requested
-system.cpu.itb.walker.walksLong 136676 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2 1079 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3 118957 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples 136676 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 136676 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 136676 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 120036 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 27117.842072 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 23228.726671 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 17468.785563 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535 117053 97.51% 97.51% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071 2702 2.25% 99.77% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607 172 0.14% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143 64 0.05% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679 25 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215 17 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 120036 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks 136411 # Table walker walks requested
+system.cpu.itb.walker.walksLong 136411 # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2 1074 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3 118764 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples 136411 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0 136411 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 136411 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 119838 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 26864.678099 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 23079.638443 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 17315.603436 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535 117018 97.65% 97.65% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071 2553 2.13% 99.78% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607 159 0.13% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143 57 0.05% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679 28 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 119838 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples -16365796 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 -16365796 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total -16365796 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 118957 99.10% 99.10% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M 1079 0.90% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 120036 # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::4K 118764 99.10% 99.10% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M 1074 0.90% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 119838 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136676 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 136676 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136411 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 136411 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120036 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 120036 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 256712 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 454948976 # ITB inst hits
-system.cpu.itb.inst_misses 136676 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119838 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 119838 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 256249 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 452746266 # ITB inst hits
+system.cpu.itb.inst_misses 136411 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 47405 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 57709 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid 47075 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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-system.cpu.cpi 2.673409 # CPI: cycles per instruction
-system.cpu.ipc 0.374054 # IPC: instructions per cycle
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system.cpu.kern.inst.arm 0 # number of arm instructions executed
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system.cpu.dcache.tags.warmup_cycle 4320792250 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu.icache.ReadReq_avg_miss_latency::total 13331.208004 # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 13331.208004 # average overall miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13324.567403 # average overall miss latency
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3108920000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3108920000 # number of overall MSHR uncacheable cycles
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006626 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71119.001842 # average ReadReq mshr miss latency
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system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 33999690 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 33991608 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 8571803 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351764 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244986 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 49796 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 33827953 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 33819864 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 33705 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 33705 # Transaction distribution
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+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351233 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 49797 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::ReadExResp 2378926 # Transaction distribution
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-system.cpu.toL2Bus.snoops 562001 # Total snoops (count)
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-system.cpu.toL2Bus.snoop_fanout::mean 3.002499 # Request fanout histogram
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+system.cpu.toL2Bus.trans_dist::UpgradeResp 49296 # Transaction distribution
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+system.cpu.toL2Bus.trans_dist::ReadExResp 2357319 # Transaction distribution
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 46150346 99.75% 99.75% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 115640 0.25% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 45893822 99.75% 99.75% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 115645 0.25% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 46265986 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 32968786985 # Layer occupancy (ticks)
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+system.cpu.toL2Bus.reqLayer0.occupancy 32777837483 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 1168500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 1164000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 37104005805 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 36924053878 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 15790852218 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 15679140875 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 409077948 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 408249695 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 1301562725 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 1295905979 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40307 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40307 # Transaction distribution
+system.iobus.trans_dist::ReadReq 40311 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40311 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 29907 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230972 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230972 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353756 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353764 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334320 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334320 # Cumulative packet size per connected master and slave (bytes)
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-system.membus.snoops 3038 # Total snoops (count)
-system.membus.snoop_fanout::samples 3378648 # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13824 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198447468 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 198617866 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14069952 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14069952 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 212687818 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 2980 # Total snoops (count)
+system.membus.snoop_fanout::samples 3310460 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3378648 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3310460 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3378648 # Request fanout histogram
-system.membus.reqLayer0.occupancy 100002500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3310460 # Request fanout histogram
+system.membus.reqLayer0.occupancy 99903000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 5714500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 5637000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 12721299869 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 12263986868 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 7256295209 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 7071367467 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 151537359 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 151550030 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
[ 0.000026] Console: colour dummy device 80x25\r
[ 0.000029] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000030] pid_max: default: 32768 minimum: 301\r
-[ 0.000044] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000046] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000174] hw perfevents: no hardware support available\r
-[ 1.060092] CPU1: failed to come online\r
-[ 2.080180] CPU2: failed to come online\r
-[ 3.100268] CPU3: failed to come online\r
-[ 3.100271] Brought up 1 CPUs\r
-[ 3.100273] SMP: Total of 1 processors activated.\r
-[ 3.100341] devtmpfs: initialized\r
-[ 3.101042] atomic64_test: passed\r
-[ 3.101098] regulator-dummy: no parameters\r
-[ 3.101606] NET: Registered protocol family 16\r
-[ 3.101773] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.101783] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.102080] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.102082] Serial: AMBA PL011 UART driver\r
-[ 3.102304] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.102346] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.102874] console [ttyAMA0] enabled\r
-[ 3.102953] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.102989] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.103025] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.103058] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130671] 3V3: 3300 mV \r
-[ 3.130723] vgaarb: loaded\r
-[ 3.130779] SCSI subsystem initialized\r
-[ 3.130831] libata version 3.00 loaded.\r
-[ 3.130889] usbcore: registered new interface driver usbfs\r
-[ 3.130910] usbcore: registered new interface driver hub\r
-[ 3.130951] usbcore: registered new device driver usb\r
-[ 3.130982] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.130991] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.131010] PTP clock support registered\r
-[ 3.131159] Switched to clocksource arch_sys_counter\r
-[ 3.132645] NET: Registered protocol family 2\r
-[ 3.132738] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.132758] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.132782] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.132801] TCP: reno registered\r
-[ 3.132808] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.132822] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.132867] NET: Registered protocol family 1\r
-[ 3.132915] RPC: Registered named UNIX socket transport module.\r
-[ 3.132925] RPC: Registered udp transport module.\r
-[ 3.132933] RPC: Registered tcp transport module.\r
-[ 3.132941] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.132953] PCI: CLS 0 bytes, default 64\r
-[ 3.133150] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.133293] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.135708] fuse init (API version 7.23)\r
-[ 3.135822] msgmni has been set to 469\r
-[ 3.138911] io scheduler noop registered\r
-[ 3.138984] io scheduler cfq registered (default)\r
-[ 3.139445] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.139457] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.139469] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.139481] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.139491] pci_bus 0000:00: scanning bus\r
-[ 3.139501] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.139514] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.139528] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.139574] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.139586] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.139597] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.139607] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.139618] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.139629] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.139640] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.139683] pci_bus 0000:00: fixups for bus\r
-[ 3.139691] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.139703] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.139723] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.139731] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.139742] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.139750] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.139762] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.139775] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.139788] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.139801] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.139812] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.139823] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.139835] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.139846] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.140504] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.140842] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.140853] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.140875] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.141475] scsi0 : ata_piix\r
-[ 3.141603] scsi1 : ata_piix\r
-[ 3.141641] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.141654] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.141783] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.141795] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.141811] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.141823] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.301188] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.301198] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.301227] ata1.00: configured for UDMA/33\r
-[ 3.301281] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.301428] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.301457] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.301505] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.301514] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.301538] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.301694] sda: sda1\r
-[ 3.301852] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.421479] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.421492] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.421515] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.421525] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.421549] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.421561] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.421651] usbcore: registered new interface driver usb-storage\r
-[ 3.421719] mousedev: PS/2 mouse device common for all mice\r
-[ 3.421922] usbcore: registered new interface driver usbhid\r
-[ 3.421931] usbhid: USB HID core driver\r
-[ 3.421965] TCP: cubic registered\r
-[ 3.421972] NET: Registered protocol family 17\r
-\0[ 3.422387] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.422426] devtmpfs: mounted\r
+[ 0.000031] pid_max: default: 32768 minimum: 301\r
+[ 0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000047] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000180] hw perfevents: no hardware support available\r
+[ 1.060095] CPU1: failed to come online\r
+[ 2.080185] CPU2: failed to come online\r
+[ 3.100275] CPU3: failed to come online\r
+[ 3.100278] Brought up 1 CPUs\r
+[ 3.100280] SMP: Total of 1 processors activated.\r
+[ 3.100349] devtmpfs: initialized\r
+[ 3.100980] atomic64_test: passed\r
+[ 3.101035] regulator-dummy: no parameters\r
+[ 3.101538] NET: Registered protocol family 16\r
+[ 3.101703] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.101713] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.102141] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.102147] Serial: AMBA PL011 UART driver\r
+[ 3.102394] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.102440] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.102971] console [ttyAMA0] enabled\r
+[ 3.103068] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 3.103104] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 3.103141] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.103175] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 3.130690] 3V3: 3300 mV \r
+[ 3.130742] vgaarb: loaded\r
+[ 3.130800] SCSI subsystem initialized\r
+[ 3.130851] libata version 3.00 loaded.\r
+[ 3.130907] usbcore: registered new interface driver usbfs\r
+[ 3.130928] usbcore: registered new interface driver hub\r
+[ 3.130968] usbcore: registered new device driver usb\r
+[ 3.130999] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.131008] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.131027] PTP clock support registered\r
+[ 3.131174] Switched to clocksource arch_sys_counter\r
+[ 3.132602] NET: Registered protocol family 2\r
+[ 3.132697] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.132719] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.132744] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.132760] TCP: reno registered\r
+[ 3.132768] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.132782] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.132828] NET: Registered protocol family 1\r
+[ 3.132876] RPC: Registered named UNIX socket transport module.\r
+[ 3.132886] RPC: Registered udp transport module.\r
+[ 3.132894] RPC: Registered tcp transport module.\r
+[ 3.132902] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.132914] PCI: CLS 0 bytes, default 64\r
+[ 3.133108] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.133253] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.135428] fuse init (API version 7.23)\r
+[ 3.135535] msgmni has been set to 469\r
+[ 3.138600] io scheduler noop registered\r
+[ 3.138667] io scheduler cfq registered (default)\r
+[ 3.139158] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.139171] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.139182] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.139194] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.139204] pci_bus 0000:00: scanning bus\r
+[ 3.139215] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.139228] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.139243] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.139286] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.139299] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.139310] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.139320] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.139331] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.139342] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.139353] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.139394] pci_bus 0000:00: fixups for bus\r
+[ 3.139403] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.139414] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.139435] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.139444] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.139455] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.139463] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.139475] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.139488] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.139501] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.139514] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.139525] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.139537] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.139548] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.139559] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.140184] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.140520] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.140531] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.140555] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.140911] scsi0 : ata_piix\r
+[ 3.141038] scsi1 : ata_piix\r
+[ 3.141075] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.141087] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.141242] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.141254] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.141271] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.141283] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.301203] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.301213] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 3.301243] ata1.00: configured for UDMA/33\r
+[ 3.301299] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.301438] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.301467] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.301514] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.301523] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.301547] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.301695] sda: sda1\r
+[ 3.301842] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.421490] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.421503] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.421526] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.421536] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.421559] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.421571] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.421656] usbcore: registered new interface driver usb-storage\r
+[ 3.421723] mousedev: PS/2 mouse device common for all mice\r
+[ 3.421911] usbcore: registered new interface driver usbhid\r
+[ 3.421921] usbhid: USB HID core driver\r
+[ 3.421955] TCP: cubic registered\r
+[ 3.421963] NET: Registered protocol family 17\r
+\0[ 3.422382] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.422420] devtmpfs: mounted\r
[ 3.422455] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 3.464515] udevd[607]: starting version 182\r
+[ 3.464312] udevd[607]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 3.614679] random: dd urandom read with 21 bits of entropy available\r
+[ 3.594630] random: dd urandom read with 20 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.781391] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 3.751405] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
max_stack_size=67108864
output=cout
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 7 2014 10:57:46
-gem5 started May 7 2014 16:03:40
-gem5 executing on cz3211bhr8
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing
+gem5 compiled Mar 15 2015 20:30:55
+gem5 started Mar 15 2015 20:31:14
+gem5 executing on zizzer2
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x11aa5150
+ 0: system.cpu.isa: ISA system set to: 0 0x45a0240
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 61276704500 because target called exit()
+Exiting @ tick 61589191500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.061593 # Number of seconds simulated
-sim_ticks 61592600500 # Number of ticks simulated
-final_tick 61592600500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.061589 # Number of seconds simulated
+sim_ticks 61589191500 # Number of ticks simulated
+final_tick 61589191500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 271325 # Simulator instruction rate (inst/s)
-host_op_rate 272676 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 184448880 # Simulator tick rate (ticks/s)
-host_mem_usage 445184 # Number of bytes of host memory used
-host_seconds 333.93 # Real time elapsed on the host
+host_inst_rate 169101 # Simulator instruction rate (inst/s)
+host_op_rate 169943 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 114949938 # Simulator tick rate (ticks/s)
+host_mem_usage 374724 # Number of bytes of host memory used
+host_seconds 535.79 # Real time elapsed on the host
sim_insts 90602849 # Number of instructions simulated
sim_ops 91054080 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 805292 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 15378471 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 16183762 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 805292 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 805292 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 805292 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 15378471 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 16183762 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 805336 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 15379322 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 16184658 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 805336 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 805336 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 805336 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 15379322 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 16184658 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15575 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 61592506000 # Total gap between requests
+system.physmem.totGap 61589097000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 642.644287 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 437.986910 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 400.933627 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 248 16.01% 16.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 186 12.01% 28.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 90 5.81% 33.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 71 4.58% 38.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 77 4.97% 43.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 93 6.00% 49.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 43 2.78% 52.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 36 2.32% 54.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 705 45.51% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation
-system.physmem.totQLat 77242000 # Total ticks spent queuing
-system.physmem.totMemAccLat 369273250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 1548 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 642.728682 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 437.613794 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 401.141843 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 250 16.15% 16.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 184 11.89% 28.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 91 5.88% 33.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 69 4.46% 38.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 77 4.97% 43.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 93 6.01% 49.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 43 2.78% 52.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 36 2.33% 54.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 705 45.54% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1548 # Bytes accessed per row activation
+system.physmem.totQLat 76265750 # Total ticks spent queuing
+system.physmem.totMemAccLat 368297000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 4959.36 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 4896.68 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 23709.36 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 23646.68 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 14018 # Number of row buffer hits during reads
+system.physmem.readRowHits 14017 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.00 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 3954575.02 # Average gap between requests
+system.physmem.avgGap 3954356.15 # Average gap between requests
system.physmem.pageHitRate 90.00 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 6373080 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 3477375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 63718200 # Energy for read commands per rank (pJ)
+system.physmem_0.actEnergy 6365520 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 3473250 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 2539008855 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 34726497750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 41361784860 # Total energy per rank (pJ)
-system.physmem_0.averagePower 671.572046 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 57760380750 # Time in different power states
-system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states
+system.physmem_0.refreshEnergy 4022201040 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 2552305815 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 34710162000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 41358171225 # Total energy per rank (pJ)
+system.physmem_0.averagePower 671.598278 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 57736612750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 2056340000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 1772530500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 1792195250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 5329800 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2908125 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 57478200 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 5322240 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 2904000 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 2571546735 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 34697955750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 41357928210 # Total energy per rank (pJ)
-system.physmem_1.averagePower 671.509428 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 57713961000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states
+system.physmem_1.refreshEnergy 4022201040 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 2572075980 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 34692811500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 41352777360 # Total energy per rank (pJ)
+system.physmem_1.averagePower 671.510839 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 57709022500 # Time in different power states
+system.physmem_1.memoryStateTime::REF 2056340000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 1819631500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 1820633500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 20789446 # Number of BP lookups
-system.cpu.branchPred.condPredicted 17091418 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 8973614 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 8867024 # Number of BTB hits
+system.cpu.branchPred.lookups 20789992 # Number of BP lookups
+system.cpu.branchPred.condPredicted 17092121 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 765794 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 8976081 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 8866607 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.812184 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 62715 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 98.780381 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 62695 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 123185201 # number of cpu cycles simulated
+system.cpu.numCycles 123178383 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602849 # Number of instructions committed
system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 2068247 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 2068275 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.359617 # CPI: cycles per instruction
-system.cpu.ipc 0.735501 # IPC: instructions per cycle
-system.cpu.tickCycles 109827605 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 13357596 # Total number of cycles that the object has spent stopped
+system.cpu.cpi 1.359542 # CPI: cycles per instruction
+system.cpu.ipc 0.735542 # IPC: instructions per cycle
+system.cpu.tickCycles 109824698 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 13353685 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 946107 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3616.143974 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 26267423 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 3616.117477 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 26267654 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 27.644012 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 27.644255 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 20661192250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3616.143974 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.882848 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.882848 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 3616.117477 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.882841 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.882841 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 252 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 2243 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 1593 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 55463259 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 55463259 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 21598839 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 21598839 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4660810 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4660810 # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses 55463725 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 55463725 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 21598560 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 21598560 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 4660812 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 4660812 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 26259649 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 26259649 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 26259649 # number of overall hits
-system.cpu.dcache.overall_hits::total 26259649 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 26259372 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 26259372 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 26259880 # number of overall hits
+system.cpu.dcache.overall_hits::total 26259880 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 914934 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 914934 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 74171 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 74171 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 989105 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 989105 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 989105 # number of overall misses
-system.cpu.dcache.overall_misses::total 989105 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918412494 # number of ReadReq miss cycles
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+system.cpu.toL2Bus.snoop_fanout::samples 1894291 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 1894292 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 1894291 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 1894291 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 1890430500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1372497 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1372247 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1428682244 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1428681994 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
system.membus.trans_dist::ReadReq 1031 # Transaction distribution
system.membus.trans_dist::ReadResp 1031 # Transaction distribution
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 15575 # Request fanout histogram
-system.membus.reqLayer0.occupancy 21632500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 21630500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 82148250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
-Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 7 2014 10:57:46
-gem5 started May 7 2014 15:30:22
-gem5 executing on cz3211bhr8
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing
+gem5 compiled Mar 15 2015 20:30:55
+gem5 started Mar 15 2015 20:31:14
+gem5 executing on zizzer2
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x1e6be7a0
+ 0: system.cpu.isa: ISA system set to: 0 0x3275620
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 377875396500 because target called exit()
+Exiting @ tick 366358475500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.366359 # Number of seconds simulated
-sim_ticks 366358704500 # Number of ticks simulated
-final_tick 366358704500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.366358 # Number of seconds simulated
+sim_ticks 366358475500 # Number of ticks simulated
+final_tick 366358475500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 242855 # Simulator instruction rate (inst/s)
-host_op_rate 263044 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 175631724 # Simulator tick rate (ticks/s)
-host_mem_usage 316616 # Number of bytes of host memory used
-host_seconds 2085.95 # Real time elapsed on the host
+host_inst_rate 156500 # Simulator instruction rate (inst/s)
+host_op_rate 169511 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 113180486 # Simulator tick rate (ticks/s)
+host_mem_usage 245616 # Number of bytes of host memory used
+host_seconds 3236.94 # Real time elapsed on the host
sim_insts 506582155 # Number of instructions simulated
sim_ops 548695378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 221696 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9006016 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9227712 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9004224 # Number of bytes read from this memory
+system.physmem.bytes_read::total 9225920 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6179648 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6179648 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 6180352 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6180352 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3464 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 140719 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 144183 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 96557 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 96557 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.data 140691 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 144155 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 96568 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 96568 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 605134 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 24582509 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 25187642 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 24577633 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 25182767 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 605134 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 605134 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 16867753 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 16867753 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 16867753 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks 16869685 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 16869685 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 16869685 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 605134 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 24582509 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 42055395 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 144183 # Number of read requests accepted
-system.physmem.writeReqs 96557 # Number of write requests accepted
-system.physmem.readBursts 144183 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 96557 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 9220288 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6178496 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 9227712 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6179648 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu.data 24577633 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 42052451 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 144155 # Number of read requests accepted
+system.physmem.writeReqs 96568 # Number of write requests accepted
+system.physmem.readBursts 144155 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 96568 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 9218240 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6178944 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 9225920 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6180352 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 9347 # Per bank write bursts
-system.physmem.perBankRdBursts::1 9007 # Per bank write bursts
-system.physmem.perBankRdBursts::2 8992 # Per bank write bursts
-system.physmem.perBankRdBursts::3 8698 # Per bank write bursts
-system.physmem.perBankRdBursts::4 9455 # Per bank write bursts
+system.physmem.perBankRdBursts::0 9365 # Per bank write bursts
+system.physmem.perBankRdBursts::1 8967 # Per bank write bursts
+system.physmem.perBankRdBursts::2 8978 # Per bank write bursts
+system.physmem.perBankRdBursts::3 8700 # Per bank write bursts
+system.physmem.perBankRdBursts::4 9448 # Per bank write bursts
system.physmem.perBankRdBursts::5 9342 # Per bank write bursts
-system.physmem.perBankRdBursts::6 8946 # Per bank write bursts
-system.physmem.perBankRdBursts::7 8102 # Per bank write bursts
-system.physmem.perBankRdBursts::8 8570 # Per bank write bursts
+system.physmem.perBankRdBursts::6 8938 # Per bank write bursts
+system.physmem.perBankRdBursts::7 8105 # Per bank write bursts
+system.physmem.perBankRdBursts::8 8575 # Per bank write bursts
system.physmem.perBankRdBursts::9 8679 # Per bank write bursts
-system.physmem.perBankRdBursts::10 8773 # Per bank write bursts
-system.physmem.perBankRdBursts::11 9476 # Per bank write bursts
-system.physmem.perBankRdBursts::12 9374 # Per bank write bursts
-system.physmem.perBankRdBursts::13 9521 # Per bank write bursts
-system.physmem.perBankRdBursts::14 8712 # Per bank write bursts
-system.physmem.perBankRdBursts::15 9073 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6191 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6098 # Per bank write bursts
+system.physmem.perBankRdBursts::10 8775 # Per bank write bursts
+system.physmem.perBankRdBursts::11 9474 # Per bank write bursts
+system.physmem.perBankRdBursts::12 9378 # Per bank write bursts
+system.physmem.perBankRdBursts::13 9522 # Per bank write bursts
+system.physmem.perBankRdBursts::14 8708 # Per bank write bursts
+system.physmem.perBankRdBursts::15 9081 # Per bank write bursts
+system.physmem.perBankWrBursts::0 6205 # Per bank write bursts
+system.physmem.perBankWrBursts::1 6092 # Per bank write bursts
system.physmem.perBankWrBursts::2 6005 # Per bank write bursts
-system.physmem.perBankWrBursts::3 5815 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6163 # Per bank write bursts
+system.physmem.perBankWrBursts::3 5814 # Per bank write bursts
+system.physmem.perBankWrBursts::4 6161 # Per bank write bursts
system.physmem.perBankWrBursts::5 6174 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6014 # Per bank write bursts
-system.physmem.perBankWrBursts::7 5494 # Per bank write bursts
-system.physmem.perBankWrBursts::8 5727 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6015 # Per bank write bursts
+system.physmem.perBankWrBursts::7 5497 # Per bank write bursts
+system.physmem.perBankWrBursts::8 5724 # Per bank write bursts
system.physmem.perBankWrBursts::9 5822 # Per bank write bursts
system.physmem.perBankWrBursts::10 5961 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6445 # Per bank write bursts
-system.physmem.perBankWrBursts::12 6308 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6444 # Per bank write bursts
+system.physmem.perBankWrBursts::12 6310 # Per bank write bursts
system.physmem.perBankWrBursts::13 6277 # Per bank write bursts
-system.physmem.perBankWrBursts::14 5998 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6047 # Per bank write bursts
+system.physmem.perBankWrBursts::14 5996 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6049 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 366358675500 # Total gap between requests
+system.physmem.totGap 366358446500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 144183 # Read request sizes (log2)
+system.physmem.readPktSize::6 144155 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 96557 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 143693 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 352 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 96568 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 143662 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 351 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5533 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5679 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5680 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5677 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5673 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5679 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 5677 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 5676 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 5696 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 5690 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 5657 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 2912 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 3099 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 5531 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5665 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5684 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5679 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5677 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5677 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 5679 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 5680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 5705 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 5696 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 5660 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 5648 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 5587 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 5575 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 5653 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 5593 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 5579 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 65205 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 236.159558 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 156.546491 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 241.906067 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 24752 37.96% 37.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 18185 27.89% 65.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 7019 10.76% 76.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7903 12.12% 88.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2061 3.16% 91.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1167 1.79% 93.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 745 1.14% 94.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 604 0.93% 95.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 2769 4.25% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 65205 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 25.873563 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 382.195910 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 5565 99.95% 99.95% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 65262 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 235.919953 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 156.506308 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 241.385533 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 24794 37.99% 37.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 18171 27.84% 65.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 7030 10.77% 76.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7953 12.19% 88.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2052 3.14% 91.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1171 1.79% 93.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 739 1.13% 94.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 589 0.90% 95.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 2763 4.23% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 65262 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5572 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 25.848887 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 382.035418 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 5569 99.95% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.338182 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.234627 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.449204 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17 2631 47.25% 47.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19 2778 49.89% 97.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21 61 1.10% 98.24% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 5572 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5572 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.326992 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.223724 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.446858 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17 2657 47.68% 47.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19 2761 49.55% 97.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21 56 1.01% 98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23 29 0.52% 98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25 20 0.36% 99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-61 1 0.02% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads
-system.physmem.totQLat 1536843000 # Total ticks spent queuing
-system.physmem.totMemAccLat 4238099250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 720335000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10667.56 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 5572 # Writes before turning the bus around for reads
+system.physmem.totQLat 1537104750 # Total ticks spent queuing
+system.physmem.totMemAccLat 4237761000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 720175000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10671.74 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29417.56 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 16.86 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 25.19 # Average system read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29421.74 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 25.16 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 16.87 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 16.87 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.33 # Data bus utilization in percentage
system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 20.79 # Average write queue length when enqueuing
-system.physmem.readRowHits 110982 # Number of row buffer hits during reads
-system.physmem.writeRowHits 64419 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 77.03 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 66.72 # Row buffer hit rate for writes
-system.physmem.avgGap 1521802.26 # Average gap between requests
-system.physmem.pageHitRate 72.89 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 248111640 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 135378375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 560734200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 310741920 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 47516601060 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 178134108000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 250834440315 # Total energy per rank (pJ)
-system.physmem_0.averagePower 684.668623 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 296034178750 # Time in different power states
+system.physmem.avgWrQLen 20.57 # Average write queue length when enqueuing
+system.physmem.readRowHits 110916 # Number of row buffer hits during reads
+system.physmem.writeRowHits 64397 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 77.01 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 66.69 # Row buffer hit rate for writes
+system.physmem.avgGap 1521908.78 # Average gap between requests
+system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 248466960 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 135572250 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 560157000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 310566960 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 23928256560 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 47486087820 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 178156194000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 250825301550 # Total energy per rank (pJ)
+system.physmem_0.averagePower 684.658255 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 296072654000 # Time in different power states
system.physmem_0.memoryStateTime::REF 12233260000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 58091210000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 58046909500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 244838160 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 133592250 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 562988400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 314830800 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 46994125095 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 178592423250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 250771563075 # Total energy per rank (pJ)
-system.physmem_1.averagePower 684.496987 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 296797282750 # Time in different power states
+system.physmem_1.actEnergy 244634040 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 133480875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 562879200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 314740080 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 23928256560 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 47146698135 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 178453904250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 250784593140 # Total energy per rank (pJ)
+system.physmem_1.averagePower 684.547137 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 296568978750 # Time in different power states
system.physmem_1.memoryStateTime::REF 12233260000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 57328110000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 57550826250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 132587783 # Number of BP lookups
-system.cpu.branchPred.condPredicted 98513206 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 6558220 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 68845364 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 64852055 # Number of BTB hits
+system.cpu.branchPred.lookups 132589371 # Number of BP lookups
+system.cpu.branchPred.condPredicted 98514041 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 6557944 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 68842060 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 64854431 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 94.199596 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 10016928 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 17846 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 94.207569 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 10017867 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 17926 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 732717409 # number of cpu cycles simulated
+system.cpu.numCycles 732716951 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 506582155 # Number of instructions committed
system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 13466110 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 13466923 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.446394 # CPI: cycles per instruction
+system.cpu.cpi 1.446393 # CPI: cycles per instruction
system.cpu.ipc 0.691375 # IPC: instructions per cycle
-system.cpu.tickCycles 695820940 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 36896469 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 1139887 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4070.954708 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 171283476 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1143983 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 149.725543 # Average number of references to valid blocks.
+system.cpu.tickCycles 695825303 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 36891648 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements 1139854 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4070.954710 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 171283379 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1143950 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 149.729778 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4070.954708 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 4070.954710 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.993885 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993885 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 346821767 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 346821767 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 114767712 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 114767712 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 53538682 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 53538682 # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses 346821558 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 346821558 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 114764882 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 114764882 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 53538642 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 53538642 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 2773 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 2773 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 168306394 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 168306394 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 168306394 # number of overall hits
-system.cpu.dcache.overall_hits::total 168306394 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 854792 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 854792 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 700624 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 700624 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1555416 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1555416 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1555416 # number of overall misses
-system.cpu.dcache.overall_misses::total 1555416 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024046732 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 14024046732 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 22031424000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 22031424000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 36055470732 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 36055470732 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 36055470732 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 36055470732 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 115622504 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 115622504 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data 168303524 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 168303524 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 168306297 # number of overall hits
+system.cpu.dcache.overall_hits::total 168306297 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 854741 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 854741 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 700664 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 700664 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 20 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 20 # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data 1555405 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1555405 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1555425 # number of overall misses
+system.cpu.dcache.overall_misses::total 1555425 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 14025846982 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 14025846982 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 22027401500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 22027401500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 36053248482 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 36053248482 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 36053248482 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 36053248482 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 115619623 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 115619623 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 169861810 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 169861810 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 169861810 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 169861810 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 169858929 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 169858929 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 169861722 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 169861722 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007393 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012917 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007161 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.007161 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.385100 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.385100 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31445.431501 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31445.431501 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23180.596530 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23180.596530 # average overall miss latency
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+system.cpu.dcache.ReadReq_avg_miss_latency::total 16409.470216 # average ReadReq miss latency
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+system.cpu.l2cache.overall_mshr_miss_latency::total 9684156500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177160 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050550 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283042 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283042 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177160 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.123897 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177160 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.123897 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66535.363741 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70000.810098 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69723.407820 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66087.229012 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66087.229012 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66535.363741 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67194.617993 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67178.776317 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66535.363741 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.617993 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67178.776317 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 807125 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 807125 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1068568 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 356400 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 356400 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39084 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356534 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 3395618 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1250688 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141603264 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 142853952 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq 807086 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 807086 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1068578 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 356417 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 356417 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39106 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356478 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 3395584 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1251392 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141601792 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 142853184 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 2232093 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 2232081 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 2232093 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 2232081 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 2232093 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 2184614500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 2232081 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 2184618500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 30006497 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 30027495 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1744748235 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1744688735 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 43319 # Transaction distribution
-system.membus.trans_dist::ReadResp 43319 # Transaction distribution
-system.membus.trans_dist::Writeback 96557 # Transaction distribution
-system.membus.trans_dist::ReadExReq 100864 # Transaction distribution
-system.membus.trans_dist::ReadExResp 100864 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384923 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 384923 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15407360 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 15407360 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 43274 # Transaction distribution
+system.membus.trans_dist::ReadResp 43274 # Transaction distribution
+system.membus.trans_dist::Writeback 96568 # Transaction distribution
+system.membus.trans_dist::ReadExReq 100881 # Transaction distribution
+system.membus.trans_dist::ReadExResp 100881 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384878 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 384878 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15406272 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 15406272 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 240740 # Request fanout histogram
+system.membus.snoop_fanout::samples 240723 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 240740 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 240723 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 240740 # Request fanout histogram
-system.membus.reqLayer0.occupancy 679202000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 240723 # Request fanout histogram
+system.membus.reqLayer0.occupancy 679184500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 765364000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 765222500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing
+drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
-Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 7 2014 10:57:46
-gem5 started May 7 2014 12:10:42
-gem5 executing on cz3211bhr8
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing
+gem5 compiled Mar 15 2015 20:30:55
+gem5 started Mar 15 2015 20:31:14
+gem5 executing on zizzer2
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0xc928260
+ 0: system.cpu.isa: ISA system set to: 0 0x3ccd9b0
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
-OO-style eon Time= 0.220000
-Exiting @ tick 227450162000 because target called exit()
+OO-style eon Time= 0.210000
+Exiting @ tick 216864820000 because target called exit()
sim_ticks 216864820000 # Number of ticks simulated
final_tick 216864820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 175540 # Simulator instruction rate (inst/s)
-host_op_rate 210755 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 139425507 # Simulator tick rate (ticks/s)
-host_mem_usage 321524 # Number of bytes of host memory used
-host_seconds 1555.42 # Real time elapsed on the host
+host_inst_rate 114758 # Simulator instruction rate (inst/s)
+host_op_rate 137779 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 91148248 # Simulator tick rate (ticks/s)
+host_mem_usage 250616 # Number of bytes of host memory used
+host_seconds 2379.25 # Real time elapsed on the host
sim_insts 273037856 # Number of instructions simulated
sim_ops 327812213 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 6626 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 899 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 317.772817 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 188.476979 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 330.358112 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 549 36.05% 36.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 352 23.11% 59.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 179 11.75% 70.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 73 4.79% 75.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 70 4.60% 80.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 53 3.48% 83.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 37 2.43% 86.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 29 1.90% 88.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 181 11.88% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation
-system.physmem.totQLat 53728750 # Total ticks spent queuing
-system.physmem.totMemAccLat 195928750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 1521 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 318.190664 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 188.796192 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 330.520878 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 546 35.90% 35.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 355 23.34% 59.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 175 11.51% 70.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 75 4.93% 75.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 71 4.67% 80.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 52 3.42% 83.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 37 2.43% 86.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 29 1.91% 88.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 181 11.90% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1521 # Bytes accessed per row activation
+system.physmem.totQLat 53624000 # Total ticks spent queuing
+system.physmem.totMemAccLat 195824000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 37920000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7084.49 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 7070.68 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25834.49 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 25820.68 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 6056 # Number of row buffer hits during reads
+system.physmem.readRowHits 6058 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 79.85 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 28595013.65 # Average gap between requests
-system.physmem.pageHitRate 79.85 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ)
+system.physmem.pageHitRate 79.88 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 5668320825 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 125145525750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 145015982220 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.698913 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 208188918000 # Time in different power states
+system.physmem_0.actBackEnergy 5663385765 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 125149854750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 145015352790 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.696011 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 208196147750 # Time in different power states
system.physmem_0.memoryStateTime::REF 7241520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 1432738500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 1425508750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 29031600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 5831746380 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 125002170000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 145037386830 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.797614 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 207947266000 # Time in different power states
+system.physmem_1.actBackEnergy 5827279860 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 125006088000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 145036838310 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.795085 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 207953796500 # Time in different power states
system.physmem_1.memoryStateTime::REF 7241520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 1674122750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 1667592250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 33219592 # Number of BP lookups
+system.cpu.branchPred.lookups 33219593 # Number of BP lookups
system.cpu.branchPred.condPredicted 17177082 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1581285 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 17974979 # Number of BTB lookups
system.cpu.branchPred.BTBHits 15661112 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 87.127290 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 6612085 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.usedRAS 6612086 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 273037856 # Number of instructions committed
system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 4054235 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 4054236 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.588533 # CPI: cycles per instruction
system.cpu.ipc 0.629512 # IPC: instructions per cycle
-system.cpu.tickCycles 430193160 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 3536480 # Total number of cycles that the object has spent stopped
+system.cpu.tickCycles 430193126 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 3536514 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 1354 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3085.768991 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 168782225 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 3085.769078 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 168782221 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 37415.700510 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 37415.699623 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768991 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 3085.769078 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.753362 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.753362 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 337583521 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 337583521 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 86712977 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 86712977 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data 86649433 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 86649433 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82047458 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82047458 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 168760435 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 168760435 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 168760435 # number of overall hits
-system.cpu.dcache.overall_hits::total 168760435 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2061 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2061 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 168696891 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 168696891 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 168760431 # number of overall hits
+system.cpu.dcache.overall_hits::total 168760431 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5219 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5219 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 7280 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 7280 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 7280 # number of overall misses
-system.cpu.dcache.overall_misses::total 7280 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 137684956 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 137684956 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 400150250 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 400150250 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 537835206 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 537835206 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 537835206 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 537835206 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 86715038 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 86715038 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data 7278 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 7278 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 7284 # number of overall misses
+system.cpu.dcache.overall_misses::total 7284 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 136977706 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 136977706 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 400661500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 400661500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 537639206 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 537639206 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 537639206 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 537639206 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 86651492 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 86651492 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 63546 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 168767715 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 168767715 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 168704169 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 168704169 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168767715 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168767715 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000094 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.000094 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66804.927705 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66804.927705 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76671.824104 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76671.824104 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73878.462363 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73878.462363 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66526.326372 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 66526.326372 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76769.783483 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 76769.783483 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 73871.833746 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 73871.833746 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 73810.983800 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73810.983800 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks
system.cpu.dcache.writebacks::total 1010 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 420 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 420 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2349 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2349 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2769 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2769 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2769 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2769 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1641 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data 2771 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2771 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2771 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2771 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4511 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 4507 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109745542 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 109745542 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219964750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 219964750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329710292 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 329710292 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329710292 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 329710292 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109140792 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 109140792 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220213500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 220213500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 320750 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 320750 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329354292 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 329354292 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329675042 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 329675042 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000063 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000063 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66877.234613 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66877.234613 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76642.770035 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76642.770035 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66671.222969 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66671.222969 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.442509 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.442509 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73076.168627 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 73076.168627 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73082.474396 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 73082.474396 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 36897 # number of replacements
-system.cpu.icache.tags.tagsinuse 1924.852609 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 73252005 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 1924.852858 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 73252007 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 38834 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 1886.285343 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 1886.285394 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852609 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.939869 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.939869 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852858 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.939870 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.939870 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 146620514 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 146620514 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 73252005 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 73252005 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 73252005 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 73252005 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 73252005 # number of overall hits
-system.cpu.icache.overall_hits::total 73252005 # number of overall hits
+system.cpu.icache.tags.tag_accesses 146620518 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 146620518 # Number of data accesses
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 40476 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 40475 # Transaction distribution
system.cpu.toL2Bus.snoop_fanout::total 44356 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 23188000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 58975248 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 58975998 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 7577708 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 7577458 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadReq 4730 # Transaction distribution
system.membus.trans_dist::ReadResp 4730 # Transaction distribution
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 7584 # Request fanout histogram
-system.membus.reqLayer0.occupancy 8969500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 8969000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 40264250 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 40262750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=LiveProcess
cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing
+drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: fcntl64(3, 2) passed through to host
-Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 7 2014 10:57:46
-gem5 started May 7 2014 14:12:56
-gem5 executing on cz3211bhr8
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing
+gem5 compiled Mar 15 2015 20:30:55
+gem5 started Mar 15 2015 20:31:14
+gem5 executing on zizzer2
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x1273de40
+ 0: system.cpu.isa: ISA system set to: 0 0x2ccb000
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
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+Exiting @ tick 545056655500 because target called exit()
sim_ticks 545056655500 # Number of ticks simulated
final_tick 545056655500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 182072 # Simulator instruction rate (inst/s)
-host_op_rate 224154 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 154902851 # Simulator tick rate (ticks/s)
-host_mem_usage 321108 # Number of bytes of host memory used
-host_seconds 3518.70 # Real time elapsed on the host
+host_inst_rate 122221 # Simulator instruction rate (inst/s)
+host_op_rate 150470 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 103982941 # Simulator tick rate (ticks/s)
+host_mem_usage 247272 # Number of bytes of host memory used
+host_seconds 5241.79 # Real time elapsed on the host
sim_insts 640655084 # Number of instructions simulated
sim_ops 788730743 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 112305 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 203.035662 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 132.214062 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 254.437736 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 47268 42.09% 42.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 43750 38.96% 81.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8988 8.00% 89.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 1909 1.70% 90.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 489 0.44% 91.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples 112303 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 203.039278 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 132.213865 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 254.441282 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 47271 42.09% 42.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 43737 38.95% 81.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 8997 8.01% 89.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 1907 1.70% 90.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 490 0.44% 91.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 737 0.66% 91.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 726 0.65% 92.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 505 0.45% 92.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7933 7.06% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 112305 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 112303 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 48.526066 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 36.050433 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::16 3044 75.93% 75.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 965 24.07% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads
-system.physmem.totQLat 2737356250 # Total ticks spent queuing
-system.physmem.totMemAccLat 8179187500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 2738025750 # Total ticks spent queuing
+system.physmem.totMemAccLat 8179857000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9431.65 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 9433.95 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28181.65 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 28183.95 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 34.08 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 7.76 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 34.11 # Average system read bandwidth in MiByte/s
system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing
-system.physmem.readRowHits 193898 # Number of row buffer hits during reads
+system.physmem.readRowHits 193900 # Number of row buffer hits during reads
system.physmem.writeRowHits 50093 # Number of row buffer hits during writes
system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes
system.physmem.avgGap 1528348.80 # Average gap between requests
system.physmem.pageHitRate 68.47 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 424002600 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 231350625 # Energy for precharge commands per rank (pJ)
+system.physmem_0.actEnergy 424055520 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 231379500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1134369600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 215570160 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 106884947925 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 233273273250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 377763731280 # Total energy per rank (pJ)
-system.physmem_0.averagePower 693.076638 # Core power per rank (mW)
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-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19724.169362 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19724.169362 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19723.409934 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19723.409934 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19723.409934 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19723.409934 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19723.409934 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19723.409934 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 460840255 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 460840255 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 460840255 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 460840255 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 460840255 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 460840255 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 460820505 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 460820505 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 460820505 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 460820505 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 460820505 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 460820505 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18180.537123 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18180.537123 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18179.757969 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18179.757969 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18179.757969 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18179.757969 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18179.757969 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18179.757969 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 257753 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 32573.758002 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 32573.758043 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 538992 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 290497 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.855413 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 2882.231587 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.601373 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29601.925042 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 2882.231572 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.601388 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 29601.925083 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.087959 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002734 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.903379 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.inst 2582 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 287984 # number of overall misses
system.cpu.l2cache.overall_misses::total 290566 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 196449750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17674937000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 17871386750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 196430000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17675629250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 17872059250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4942281750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4942281750 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 196449750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 22617218750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 22813668500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 196449750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 22617218750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 22813668500 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 196430000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 22617911000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 22814341000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 196430000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 22617911000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 22814341000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 25348 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 712915 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 738263 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101862 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368154 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.359796 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76084.333850 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79655.225717 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 79614.151910 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76076.684741 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79658.345464 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 79617.147789 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74779.951128 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74779.951128 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78514.583606 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78514.583606 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76076.684741 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78538.776460 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 78516.898054 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76076.684741 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78538.776460 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 78516.898054 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2577 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 287957 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 290534 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163845000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14897681250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15061526250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163824250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14898374500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15062198750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4113937750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4113937750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163845000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19011619000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 19175464000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163845000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19011619000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 19175464000 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163824250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19012312250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 19176136500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163824250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19012312250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 19176136500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311210 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.304015 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.359757 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63579.743888 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67147.202591 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67106.241897 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63571.691890 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67150.327225 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67109.238203 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62246.565342 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62246.565342 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63571.691890 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66024.830964 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66003.071930 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63571.691890 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66024.830964 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66003.071930 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 738263 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 738262 # Transaction distribution
system.cpu.toL2Bus.snoop_fanout::total 899005 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 540922500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 38574245 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 38574495 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1224003723 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1224002973 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadReq 224442 # Transaction distribution
system.membus.trans_dist::ReadResp 224442 # Transaction distribution
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 356631 # Request fanout histogram
-system.membus.reqLayer0.occupancy 731515500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 731518000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1551221000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 1551221500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing
+drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 7 2014 10:57:46
-gem5 started May 7 2014 17:09:29
-gem5 executing on cz3211bhr8
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing
+gem5 compiled Mar 15 2015 20:30:55
+gem5 started Mar 15 2015 20:31:14
+gem5 executing on zizzer2
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0xcee8df0
+ 0: system.cpu.isa: ISA system set to: 0 0x3b079b0
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 64581408500 because target called exit()
+Exiting @ tick 57738195500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.058730 # Number of seconds simulated
-sim_ticks 58730125500 # Number of ticks simulated
-final_tick 58730125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.057738 # Number of seconds simulated
+sim_ticks 57738195500 # Number of ticks simulated
+final_tick 57738195500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 197162 # Simulator instruction rate (inst/s)
-host_op_rate 252141 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 163284235 # Simulator tick rate (ticks/s)
-host_mem_usage 321164 # Number of bytes of host memory used
-host_seconds 359.68 # Real time elapsed on the host
+host_inst_rate 113055 # Simulator instruction rate (inst/s)
+host_op_rate 144580 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 92047581 # Simulator tick rate (ticks/s)
+host_mem_usage 250264 # Number of bytes of host memory used
+host_seconds 627.26 # Real time elapsed on the host
sim_insts 70915127 # Number of instructions simulated
sim_ops 90690083 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 324352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 7923392 # Number of bytes read from this memory
-system.physmem.bytes_read::total 8247744 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 7922944 # Number of bytes read from this memory
+system.physmem.bytes_read::total 8247296 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory
-system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 5372992 # Number of bytes written to this memory
+system.physmem.bytes_written::total 5372992 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 5068 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 123803 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 128871 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 5522753 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 134911886 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 140434639 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 5522753 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 5522753 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 91483952 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 91483952 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 91483952 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 5522753 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 134911886 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 231918592 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 128871 # Number of read requests accepted
-system.physmem.writeReqs 83951 # Number of write requests accepted
-system.physmem.readBursts 128871 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
-system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 8247744 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::cpu.data 123796 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 128864 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 83953 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 83953 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 5617633 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 137221885 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 142839518 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 5617633 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 5617633 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 93057844 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 93057844 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 93057844 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 5617633 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 137221885 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 235897362 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 128864 # Number of read requests accepted
+system.physmem.writeReqs 83953 # Number of write requests accepted
+system.physmem.readBursts 128864 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 83953 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 8246976 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue
+system.physmem.bytesWritten 5371008 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 8247296 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 5372992 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 8159 # Per bank write bursts
-system.physmem.perBankRdBursts::1 8376 # Per bank write bursts
-system.physmem.perBankRdBursts::2 8228 # Per bank write bursts
-system.physmem.perBankRdBursts::3 8171 # Per bank write bursts
-system.physmem.perBankRdBursts::4 8319 # Per bank write bursts
-system.physmem.perBankRdBursts::5 8450 # Per bank write bursts
-system.physmem.perBankRdBursts::6 8088 # Per bank write bursts
-system.physmem.perBankRdBursts::7 7969 # Per bank write bursts
-system.physmem.perBankRdBursts::8 8071 # Per bank write bursts
-system.physmem.perBankRdBursts::9 7640 # Per bank write bursts
-system.physmem.perBankRdBursts::10 7818 # Per bank write bursts
-system.physmem.perBankRdBursts::11 7832 # Per bank write bursts
-system.physmem.perBankRdBursts::12 7881 # Per bank write bursts
-system.physmem.perBankRdBursts::13 7879 # Per bank write bursts
-system.physmem.perBankRdBursts::14 7977 # Per bank write bursts
-system.physmem.perBankRdBursts::15 8007 # Per bank write bursts
-system.physmem.perBankWrBursts::0 5180 # Per bank write bursts
+system.physmem.perBankRdBursts::0 8158 # Per bank write bursts
+system.physmem.perBankRdBursts::1 8374 # Per bank write bursts
+system.physmem.perBankRdBursts::2 8229 # Per bank write bursts
+system.physmem.perBankRdBursts::3 8170 # Per bank write bursts
+system.physmem.perBankRdBursts::4 8316 # Per bank write bursts
+system.physmem.perBankRdBursts::5 8449 # Per bank write bursts
+system.physmem.perBankRdBursts::6 8089 # Per bank write bursts
+system.physmem.perBankRdBursts::7 7971 # Per bank write bursts
+system.physmem.perBankRdBursts::8 8070 # Per bank write bursts
+system.physmem.perBankRdBursts::9 7642 # Per bank write bursts
+system.physmem.perBankRdBursts::10 7819 # Per bank write bursts
+system.physmem.perBankRdBursts::11 7829 # Per bank write bursts
+system.physmem.perBankRdBursts::12 7880 # Per bank write bursts
+system.physmem.perBankRdBursts::13 7877 # Per bank write bursts
+system.physmem.perBankRdBursts::14 7978 # Per bank write bursts
+system.physmem.perBankRdBursts::15 8008 # Per bank write bursts
+system.physmem.perBankWrBursts::0 5182 # Per bank write bursts
system.physmem.perBankWrBursts::1 5376 # Per bank write bursts
system.physmem.perBankWrBursts::2 5285 # Per bank write bursts
system.physmem.perBankWrBursts::3 5155 # Per bank write bursts
system.physmem.perBankWrBursts::4 5266 # Per bank write bursts
system.physmem.perBankWrBursts::5 5517 # Per bank write bursts
system.physmem.perBankWrBursts::6 5197 # Per bank write bursts
-system.physmem.perBankWrBursts::7 5050 # Per bank write bursts
+system.physmem.perBankWrBursts::7 5047 # Per bank write bursts
system.physmem.perBankWrBursts::8 5033 # Per bank write bursts
-system.physmem.perBankWrBursts::9 5087 # Per bank write bursts
+system.physmem.perBankWrBursts::9 5088 # Per bank write bursts
system.physmem.perBankWrBursts::10 5251 # Per bank write bursts
system.physmem.perBankWrBursts::11 5143 # Per bank write bursts
system.physmem.perBankWrBursts::12 5343 # Per bank write bursts
system.physmem.perBankWrBursts::13 5363 # Per bank write bursts
system.physmem.perBankWrBursts::14 5451 # Per bank write bursts
-system.physmem.perBankWrBursts::15 5227 # Per bank write bursts
+system.physmem.perBankWrBursts::15 5225 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 58730091000 # Total gap between requests
+system.physmem.totGap 57738161000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 128871 # Read request sizes (log2)
+system.physmem.readPktSize::6 128864 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 83951 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2284 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 83953 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 116707 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 12131 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 603 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 623 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5150 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5168 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5167 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5167 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5172 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 5174 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 5189 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 5334 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 5230 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 5694 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 5228 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 5161 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 615 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4052 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5049 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5142 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5173 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5172 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5174 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 5194 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 5187 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 5219 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 5363 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 5263 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 5291 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 5723 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 5319 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 5166 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 38559 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 353.122851 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 215.043714 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 334.345734 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 12150 31.51% 31.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 8188 21.23% 52.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 4125 10.70% 63.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2946 7.64% 71.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2498 6.48% 77.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1699 4.41% 81.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1309 3.39% 85.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1159 3.01% 88.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 4485 11.63% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 38559 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 24.968217 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 360.537784 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 5158 99.96% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 38462 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 353.991784 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 215.320111 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 335.607526 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 12100 31.46% 31.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 8198 21.31% 52.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 4148 10.78% 63.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2890 7.51% 71.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2484 6.46% 77.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1581 4.11% 81.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1319 3.43% 85.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1187 3.09% 88.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 4555 11.84% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 38462 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 24.974593 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 361.421207 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.264341 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.248462 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.748642 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 4548 88.14% 88.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 7 0.14% 88.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 485 9.40% 97.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 104 2.02% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 10 0.19% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 3 0.06% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 1 0.02% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads
-system.physmem.totQLat 1533027250 # Total ticks spent queuing
-system.physmem.totMemAccLat 3949246000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11896.38 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.276571 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.259351 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.782645 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 4530 87.86% 87.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 9 0.17% 88.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 479 9.29% 97.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 112 2.17% 99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 15 0.29% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 8 0.16% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 2 0.04% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads
+system.physmem.totQLat 1653247250 # Total ticks spent queuing
+system.physmem.totMemAccLat 4069353500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 644295000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12829.89 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30646.38 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 140.43 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 91.45 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 140.43 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 91.48 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 31579.89 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 142.83 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 93.02 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 142.84 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 93.06 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 1.81 # Data bus utilization in percentage
-system.physmem.busUtilRead 1.10 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.71 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing
-system.physmem.readRowHits 112070 # Number of row buffer hits during reads
-system.physmem.writeRowHits 62147 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.03 # Row buffer hit rate for writes
-system.physmem.avgGap 275958.74 # Average gap between requests
-system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 512499000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 272270160 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 12264762105 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 24475931250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 41596065810 # Total energy per rank (pJ)
-system.physmem_0.averagePower 708.329716 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 40585694500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1960920000 # Time in different power states
+system.physmem.busUtil 1.84 # Data bus utilization in percentage
+system.physmem.busUtilRead 1.12 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 23.36 # Average write queue length when enqueuing
+system.physmem.readRowHits 112168 # Number of row buffer hits during reads
+system.physmem.writeRowHits 62144 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 74.02 # Row buffer hit rate for writes
+system.physmem.avgGap 271304.27 # Average gap between requests
+system.physmem.pageHitRate 81.91 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 151283160 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 82545375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 512694000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 272322000 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3770972400 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 11678597190 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 24396798750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 40865212875 # Total energy per rank (pJ)
+system.physmem_0.averagePower 707.802856 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 40459125250 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1927900000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 16178034500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 15348292250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 139308120 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 76011375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 492024000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 271453680 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 11655970470 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 25009959000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 41480286165 # Total energy per rank (pJ)
-system.physmem_1.averagePower 706.358131 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 41477231750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1960920000 # Time in different power states
+system.physmem_1.actEnergy 139489560 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 76110375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 492070800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 271492560 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3770972400 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 11151778680 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 24858920250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 40760834625 # Total energy per rank (pJ)
+system.physmem_1.averagePower 705.994980 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 41228847750 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1927900000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 15286019500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 14578569750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 14827059 # Number of BP lookups
-system.cpu.branchPred.condPredicted 9919255 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 395881 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9555564 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6751205 # Number of BTB hits
+system.cpu.branchPred.lookups 14838314 # Number of BP lookups
+system.cpu.branchPred.condPredicted 9926302 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 397118 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9672403 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 6752101 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 70.652083 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1718768 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 69.807896 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1719649 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 117460251 # number of cpu cycles simulated
+system.cpu.numCycles 115476391 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70915127 # Number of instructions committed
system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 1148249 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 1150638 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.656350 # CPI: cycles per instruction
-system.cpu.ipc 0.603737 # IPC: instructions per cycle
-system.cpu.tickCycles 97003390 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 20456861 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 156434 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4067.721714 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 42666461 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 160530 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 265.784969 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 833735250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4067.721714 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.993096 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.993096 # Average percentage of cache occupancy
+system.cpu.cpi 1.628375 # CPI: cycles per instruction
+system.cpu.ipc 0.614109 # IPC: instructions per cycle
+system.cpu.tickCycles 96920862 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 18555529 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements 156418 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4067.282815 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 42627759 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 160514 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 265.570349 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 830513250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4067.282815 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.992989 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.992989 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 710 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 3342 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 1135 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 2916 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 86017904 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 86017904 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 22990876 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 22990876 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 19643747 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 19643747 # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses 86021754 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 86021754 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 22869180 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 22869180 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 19642188 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 19642188 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 84553 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 84553 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 42634623 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 42634623 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 42634623 # number of overall hits
-system.cpu.dcache.overall_hits::total 42634623 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 56072 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 56072 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 206154 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 206154 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 262226 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 262226 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 262226 # number of overall misses
-system.cpu.dcache.overall_misses::total 262226 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 2301185937 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 2301185937 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 16676998250 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 16676998250 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 18978184187 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 18978184187 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 18978184187 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 18978184187 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 23046948 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 23046948 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data 42511368 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 42511368 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 42595921 # number of overall hits
+system.cpu.dcache.overall_hits::total 42595921 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 51489 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 51489 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 207713 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 207713 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 43659 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 43659 # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data 259202 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 259202 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 302861 # number of overall misses
+system.cpu.dcache.overall_misses::total 302861 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 1477411436 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 1477411436 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 16920342250 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 16920342250 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 18397753686 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 18397753686 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 18397753686 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 18397753686 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 22920669 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 22920669 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 128212 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 128212 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 42896849 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 42896849 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 42896849 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 42896849 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002433 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010386 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.010386 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.006113 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.006113 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.006113 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.006113 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.840509 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.840509 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80895.826664 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 80895.826664 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72373.388554 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72373.388554 # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data 42770570 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 42770570 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 42898782 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 42898782 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002246 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002246 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.340522 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.340522 # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.006060 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.006060 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.007060 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.007060 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28693.729457 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28693.729457 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81460.198688 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 81460.198688 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 70978.440313 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 70978.440313 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60746.526248 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60746.526248 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 128445 # number of writebacks
-system.cpu.dcache.writebacks::total 128445 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2576 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 2576 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99120 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 99120 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 101696 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 101696 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 101696 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 101696 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53496 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 53496 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 160530 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 160530 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 160530 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 160530 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2163468813 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2163468813 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402400750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402400750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10565869563 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10565869563 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10565869563 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10565869563 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002321 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks 128435 # number of writebacks
+system.cpu.dcache.writebacks::total 128435 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21989 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 21989 # number of ReadReq MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total 122672 # number of overall MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::total 29500 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107030 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 107030 # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23984 # number of SoftPFReq MSHR misses
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-system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89633 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449505 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 539138 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2868224 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18494400 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 21362624 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq 98283 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 98282 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 128435 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 107030 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 107030 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89597 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449463 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 539060 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2867072 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492736 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 21359808 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 333792 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 333748 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 333792 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 333748 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 333792 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 295341000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 333748 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 295309000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 68175990 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 68157239 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 268644937 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 268247686 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 26591 # Transaction distribution
-system.membus.trans_dist::ReadResp 26591 # Transaction distribution
-system.membus.trans_dist::Writeback 83951 # Transaction distribution
-system.membus.trans_dist::ReadExReq 102280 # Transaction distribution
-system.membus.trans_dist::ReadExResp 102280 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341693 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 341693 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620608 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 13620608 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 26582 # Transaction distribution
+system.membus.trans_dist::ReadResp 26582 # Transaction distribution
+system.membus.trans_dist::Writeback 83953 # Transaction distribution
+system.membus.trans_dist::ReadExReq 102282 # Transaction distribution
+system.membus.trans_dist::ReadExResp 102282 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341681 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 341681 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620288 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 13620288 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 212822 # Request fanout histogram
+system.membus.snoop_fanout::samples 212817 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 212822 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 212817 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 212822 # Request fanout histogram
-system.membus.reqLayer0.occupancy 579596500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 212817 # Request fanout histogram
+system.membus.reqLayer0.occupancy 578407500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 680391500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 680129500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing
+drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
-Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 7 2014 10:57:46
-gem5 started May 7 2014 11:11:49
-gem5 executing on cz3211bhr8
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing
+gem5 compiled Mar 15 2015 20:30:55
+gem5 started Mar 15 2015 20:31:14
+gem5 executing on zizzer2
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x1f2b7940
+ 0: system.cpu.isa: ISA system set to: 0 0x2c50960
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 1135900642500 because target called exit()
+Exiting @ tick 1121241432500 because target called exit()
sim_ticks 1121241432500 # Number of ticks simulated
final_tick 1121241432500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 243175 # Simulator instruction rate (inst/s)
-host_op_rate 261985 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 176527853 # Simulator tick rate (ticks/s)
-host_mem_usage 312356 # Number of bytes of host memory used
-host_seconds 6351.64 # Real time elapsed on the host
+host_inst_rate 170583 # Simulator instruction rate (inst/s)
+host_op_rate 183778 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 123831111 # Simulator tick rate (ticks/s)
+host_mem_usage 241824 # Number of bytes of host memory used
+host_seconds 9054.60 # Real time elapsed on the host
sim_insts 1544563087 # Number of instructions simulated
sim_ops 1664032480 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 60985 # Writes before turning the bus around for reads
-system.physmem.totQLat 38434565750 # Total ticks spent queuing
-system.physmem.totMemAccLat 76957228250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 38434561000 # Total ticks spent queuing
+system.physmem.totMemAccLat 76957223500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 10272710000 # Total ticks spent in databus transfers
system.physmem.avgQLat 18707.12 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 596864300250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 240141363 # Number of BP lookups
-system.cpu.branchPred.condPredicted 186745178 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 240141357 # Number of BP lookups
+system.cpu.branchPred.condPredicted 186745174 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 14595264 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 132286201 # Number of BTB lookups
+system.cpu.branchPred.BTBLookups 132286195 # Number of BTB lookups
system.cpu.branchPred.BTBHits 122283419 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 92.438530 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 92.438534 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 15659523 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1544563087 # Number of instructions committed
system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 40063389 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 40063388 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.451856 # CPI: cycles per instruction
system.cpu.ipc 0.688774 # IPC: instructions per cycle
-system.cpu.tickCycles 1838984641 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 403498224 # Total number of cycles that the object has spent stopped
+system.cpu.tickCycles 1838984644 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 403498221 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 9223361 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4085.642530 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 624067003 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 4085.642531 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 624067002 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9227457 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 67.631527 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 67.631526 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 9813070000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4085.642530 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 4085.642531 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997471 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997471 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1276544027 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1276544027 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 453735354 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 453735354 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data 453735352 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 453735352 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 170331527 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 170331527 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 624066881 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 624066881 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 624066881 # number of overall hits
-system.cpu.dcache.overall_hits::total 624066881 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 7336762 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 7336762 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 624066879 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 624066879 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 624066880 # number of overall hits
+system.cpu.dcache.overall_hits::total 624066880 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 7336761 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 7336761 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2254520 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2254520 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 9591282 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9591282 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9591282 # number of overall misses
-system.cpu.dcache.overall_misses::total 9591282 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 192442349996 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 192442349996 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 109711138250 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 109711138250 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 302153488246 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 302153488246 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 302153488246 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 302153488246 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 461072116 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 461072116 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data 9591281 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 9591281 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 9591283 # number of overall misses
+system.cpu.dcache.overall_misses::total 9591283 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 192442274246 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 192442274246 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 109711140250 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 109711140250 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 302153414496 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 302153414496 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 302153414496 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 302153414496 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 461072113 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 461072113 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 633658163 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 633658163 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 633658160 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 633658160 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 633658163 # number of overall (read+write) accesses
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88193.858129 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88193.858129 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 87772.574673 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 87772.574673 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 87504.132819 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88193.859378 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88193.859378 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77096.396966 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87776.682074 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 87772.572849 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77096.396966 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87776.682074 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 87772.572849 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 790 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2055093 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2055883 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51087500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51082250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93955002000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94006089500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60459125500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60459125500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51087500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154414127500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 154465215000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51087500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154414127500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 154465215000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94006084250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60459126500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60459126500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51082250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154414128500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 154465210750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51082250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154414128500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 154465210750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171054 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171142 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.222781 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64667.721519 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64661.075949 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74867.764828 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74861.347847 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75560.022721 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75560.022721 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74861.343666 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75560.023971 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75560.023971 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64661.075949 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75137.294760 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75133.269135 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64661.075949 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75137.294760 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75133.269135 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 7337377 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7337377 # Transaction distribution
system.cpu.toL2Bus.snoop_fanout::total 12929320 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10165700000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1400999 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1401249 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 14190167496 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
system.membus.snoop_fanout::total 3102414 # Request fanout histogram
system.membus.reqLayer0.occupancy 7944829000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 11243795500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 11243795750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=LiveProcess
cmd=twolf smred
cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
+drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 7 2014 10:57:46
-gem5 started May 7 2014 13:16:45
-gem5 executing on cz3211bhr8
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
+gem5 compiled Mar 15 2015 20:30:55
+gem5 started Mar 15 2015 20:31:14
+gem5 executing on zizzer2
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x1c024750
+ 0: system.cpu.isa: ISA system set to: 0 0x3623b60
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 133578736500 because target called exit()
+122 123 124 Exiting @ tick 131756455500 because target called exit()
sim_ticks 131756455500 # Number of ticks simulated
final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 249754 # Simulator instruction rate (inst/s)
-host_op_rate 263281 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 190965456 # Simulator tick rate (ticks/s)
-host_mem_usage 316672 # Number of bytes of host memory used
-host_seconds 689.95 # Real time elapsed on the host
+host_inst_rate 150043 # Simulator instruction rate (inst/s)
+host_op_rate 158169 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 114724713 # Simulator tick rate (ticks/s)
+host_mem_usage 245376 # Number of bytes of host memory used
+host_seconds 1148.46 # Real time elapsed on the host
sim_insts 172317809 # Number of instructions simulated
sim_ops 181650742 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation
-system.physmem.totQLat 26801000 # Total ticks spent queuing
-system.physmem.totMemAccLat 99344750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 26795500 # Total ticks spent queuing
+system.physmem.totMemAccLat 99339250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6927.11 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 6925.69 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25677.11 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 25675.69 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s
system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 3539588850 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 75945927000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 88111773120 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.773044 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 126343733250 # Time in different power states
+system.physmem_0.actBackEnergy 3539591415 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 75945924750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 88111773435 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.773046 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 126343729250 # Time in different power states
system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 1010942750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 1010946750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ)
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 49934480 # Number of BP lookups
-system.cpu.branchPred.condPredicted 39666708 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 49934475 # Number of BP lookups
+system.cpu.branchPred.condPredicted 39666705 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 24374232 # Number of BTB lookups
+system.cpu.branchPred.BTBLookups 24374227 # Number of BTB lookups
system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 95.592518 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 95.592537 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.529226 # CPI: cycles per instruction
system.cpu.ipc 0.653925 # IPC: instructions per cycle
-system.cpu.tickCycles 257129924 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 6382987 # Total number of cycles that the object has spent stopped
+system.cpu.tickCycles 257129929 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 6382982 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 42 # number of replacements
-system.cpu.dcache.tags.tagsinuse 1377.698544 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 40765677 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 1377.698550 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 40765676 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 22522.473481 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 22522.472928 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698544 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698550 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 81538036 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 81538036 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 28358222 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 28358222 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 81538034 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 81538034 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 28357756 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 28357756 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 465 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 465 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 40720863 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 40720863 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 40720863 # number of overall hits
-system.cpu.dcache.overall_hits::total 40720863 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 790 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 790 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 40720397 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 40720397 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 40720862 # number of overall hits
+system.cpu.dcache.overall_hits::total 40720862 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 789 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 789 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2436 # number of demand (read+write) misses
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution
system.membus.snoop_fanout::total 3869 # Request fanout histogram
system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff