Updated verific build/test instructions

diff --git a/frontends/verific/build_amd64.txt b/frontends/verific/build_amd64.txt
index 49debe0f080b3223f57b4014b400f5ed4fcbb5d9..2f325e515d3a6fab23432c21a9975771c833f24c 100644 (file)
--- a/frontends/verific/build_amd64.txt
+++ b/frontends/verific/build_amd64.txt
@@ -1,6 +1,6 @@
 
-Notes on buildin yosys with verific support on amd64 when you only have the
-i386 eval version of Verific:
+Notes on building yosys with verific support on amd64 when you
+only have the i386 eval version of Verific:
 
 
 1.) Use a Makefile.conf like the following one:
@@ -13,21 +13,19 @@ ENABLE_ABC := 0
 ENABLE_VERIFIC := 1
 CXXFLAGS += -m32
 LDFLAGS += -m32
+VERIFIC_DIR = /usr/local/src/verific_lib_eval
 --snap--
 
 
-2.) Install the neccessary multilib packages.
+2.) Install the neccessary multilib packages
 
 Hint: On debian/ubuntu the multilib packages have names such as
-libreadline-dev:amd64 or lib32readline6-dev, depending on the version
-of the system you are working with.
+libreadline-dev:amd64 or lib32readline6-dev, depending on the
+exact version of debian/ubuntu you are working with.
 
-Hint: On Ubuntu 14.04 there is a problem with the 32bit libz
-package. A workaround is running the following command in the
-yosys source directory:
 
-    ln -s /usr/include/x86_64-linux-gnu/zconf.h .
+3.) Build and test
 
-
-3.) Run 'make' and 'make install' as usual.
+make -j8
+./yosys frontends/verific/test_navre.ys
 

diff --git a/frontends/verific/test_navre.ys b/frontends/verific/test_navre.ys
index 6f63761ab80c07e2e1112014b981787e6fe2b099..a56b725ac4e73f0c0876c57bdc9b25dd8bbdc894 100644 (file)
--- a/frontends/verific/test_navre.ys
+++ b/frontends/verific/test_navre.ys
@@ -1,11 +1,11 @@
-verific -vlog2k ../../../yosys-bigsim/softusb_navre/rtl/softusb_navre.v
+verific -vlog2k ../yosys-bigsim/softusb_navre/rtl/softusb_navre.v
 verific -import softusb_navre
 
 memory softusb_navre
 flatten softusb_navre
 rename softusb_navre gate
 
-read_verilog ../../../yosys-bigsim/softusb_navre/rtl/softusb_navre.v
+read_verilog ../yosys-bigsim/softusb_navre/rtl/softusb_navre.v
 cd softusb_navre; proc; opt; memory; opt; cd ..
 rename softusb_navre gold