soc/cores/clock: add Max10PLL.

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 4b6addab20621e59a8506b76cf118f3b27e61690..2ff7668c930e3cac85a32d344c23733a190471ed 100644 (file)
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -884,3 +884,23 @@ class Cyclone10LPPLL(IntelClocking):
             "-A7" : (0e6, 450e6),
             "-I8" : (0e6, 362e6),
         }[speedgrade]
+
+# Intel / Max10 ------------------------------------------------------------------------------------
+
+class Max10PLL(IntelClocking):
+    nclkouts_max   = 5
+    n_div_range    = (1, 512+1)
+    m_div_range    = (1, 512+1)
+    c_div_range    = (1, 512+1)
+    clkin_freq_range     = (5e6, 472.5e6)
+    clkin_pfd_freq_range = (5e6, 325e6)  # FIXME: use
+    vco_freq_range       = (600e6, 1300e6)
+    def __init__(self, speedgrade="-6"):
+        self.logger = logging.getLogger("Max10PLL")
+        self.logger.info("Creating Max10PLL, {}.".format(colorer("speedgrade {}".format(speedgrade))))
+        IntelClocking.__init__(self)
+        self.clko_freq_range = {
+            "-6" : (0e6, 472.5e6),
+            "-7" : (0e6, 450e6),
+            "-8" : (0e6, 402.5e6),
+        }[speedgrade]