std::string expr_d = stringf("(|%s#%d#%d| state)", get_id(module), arrayid, wr_ports);
std::string expr_q = stringf("(|%s#%d#0| next_state)", get_id(module), arrayid);
trans.push_back(stringf(" (= %s %s) ; %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell)));
+
+ Const init_data = cell->getParam("\\INIT");
+ int memsize = cell->getParam("\\SIZE").as_int();
+
+ for (int i = 0; i < memsize; i++)
+ {
+ if (GetSize(init_data) < i*width)
+ break;
+
+ Const initword = init_data.extract(i*width, width, State::Sx);
+ bool gen_init_constr = false;
+
+ for (auto bit : initword.bits)
+ if (bit == State::S0 || bit == State::S1)
+ gen_init_constr = true;
+
+ init_list.push_back(stringf("(= (select (|%s#%d#0| state) #b%s) #b%s) ; %s[%d]",
+ get_id(module), arrayid, Const(i, abits).as_string().c_str(),
+ initword.as_string().c_str(), get_id(cell), i));
+ }
}
}
}
log(" this will print the recursive walk used to export the modules.\n");
log("\n");
log(" -nobv\n");
- log(" disable support for BitVec (FixedSizeBitVectors theory). with this\n");
- log(" option set multi-bit wires are represented using the BitVec sort and\n");
+ log(" disable support for BitVec (FixedSizeBitVectors theory). without this\n");
+ log(" option multi-bit wires are represented using the BitVec sort and\n");
log(" support for coarse grain cells (incl. arithmetic) is enabled.\n");
log("\n");
log(" -nomem\n");
log("\n");
log(" -wires\n");
log(" create '<mod>_n' functions for all public wires. by default only ports,\n");
- log(" registers, and wires with the 'keep' attribute set are exported.\n");
+ log(" registers, and wires with the 'keep' attribute are exported.\n");
log("\n");
log(" -tpl <template_file>\n");
log(" use the given template file. the line containing only the token '%%%%'\n");
-all: demo1 demo2 demo3 demo4 demo5 demo6
+all: demo1 demo2 demo3 demo4 demo5 demo6 demo7
demo1: demo1.smt2
yosys-smtbmc --dump-vcd demo1.vcd demo1.smt2
demo6: demo6.smt2
yosys-smtbmc -t 1 demo6.smt2
+demo7: demo7.smt2
+ yosys-smtbmc -t 10 demo7.smt2
+
demo1.smt2: demo1.v
yosys -ql demo1.yslog -p 'read_verilog -formal demo1.v; prep -top demo1 -nordff; write_smt2 -wires demo1.smt2'
demo6.smt2: demo6.v
yosys -ql demo6.yslog -p 'read_verilog demo6.v; prep -top demo6 -nordff; assertpmux; opt -keepdc -fast; write_smt2 -wires demo6.smt2'
+demo7.smt2: demo7.v
+ yosys -ql demo7.yslog -p 'read_verilog -formal demo7.v; prep -top demo7 -nordff; write_smt2 -wires demo7.smt2'
+
clean:
rm -f demo1.yslog demo1.smt2 demo1.vcd
rm -f demo2.yslog demo2.smt2 demo2.vcd demo2.smtc demo2_tb.v demo2_tb demo2_tb.vcd
rm -f demo4.yslog demo4.smt2 demo4.vcd
rm -f demo5.yslog demo5.smt2 demo5.vcd
rm -f demo6.yslog demo6.smt2
+ rm -f demo7.yslog demo7.smt2
-.PHONY: demo1 demo2 demo3 demo4 demo5 demo6 clean
+.PHONY: demo1 demo2 demo3 demo4 demo5 demo6 demo7 clean