info->has_gpu_reset_status_query = true;
info->has_gpu_reset_counter_query = false;
info->has_eqaa_surface_allocator = true;
+ info->has_format_bc1_through_bc7 = true;
info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */
printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
printf(" has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
+ printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);
bool has_gpu_reset_status_query;
bool has_gpu_reset_counter_query;
bool has_eqaa_surface_allocator;
+ bool has_format_bc1_through_bc7;
/* Shader cores. */
uint32_t r600_max_quad_pipes; /* wave size / 16 */
int first_non_void)
{
struct si_screen *sscreen = (struct si_screen*)screen;
- bool enable_compressed_formats = (sscreen->info.drm_major == 2 &&
- sscreen->info.drm_minor >= 31) ||
- sscreen->info.drm_major == 3;
bool uniform = true;
int i;
}
if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
- if (!enable_compressed_formats)
+ if (!sscreen->info.has_format_bc1_through_bc7)
goto out_unknown;
switch (format) {
}
if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
- if (!enable_compressed_formats)
+ if (!sscreen->info.has_format_bc1_through_bc7)
goto out_unknown;
switch (format) {
}
if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
- if (!enable_compressed_formats)
+ if (!sscreen->info.has_format_bc1_through_bc7)
goto out_unknown;
switch (format) {
ws->info.has_gpu_reset_status_query = false;
ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
ws->info.has_eqaa_surface_allocator = false;
+ ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;