ac/gpu_info: add has_format_bc1_through_bc7
authorMarek Olšák <marek.olsak@amd.com>
Wed, 2 May 2018 23:04:10 +0000 (19:04 -0400)
committerMarek Olšák <marek.olsak@amd.com>
Thu, 10 May 2018 22:40:00 +0000 (18:40 -0400)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
src/amd/common/ac_gpu_info.c
src/amd/common/ac_gpu_info.h
src/gallium/drivers/radeonsi/si_state.c
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

index f05dd77a21ef1f2097911cc9ed8440bcbef7ba34..1c7abdb87cb64d05dc55513640f7c4b1762ebedc 100644 (file)
@@ -323,6 +323,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
        info->has_gpu_reset_status_query = true;
        info->has_gpu_reset_counter_query = false;
        info->has_eqaa_surface_allocator = true;
+       info->has_format_bc1_through_bc7 = true;
 
        info->num_render_backends = amdinfo->rb_pipes;
        /* The value returned by the kernel driver was wrong. */
@@ -477,6 +478,7 @@ void ac_print_gpu_info(struct radeon_info *info)
        printf("    has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
        printf("    has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
        printf("    has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
+       printf("    has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
 
        printf("Shader core info:\n");
        printf("    max_shader_clock = %i\n", info->max_shader_clock);
index f8e4adf0d41f61b5eb7d50d5048bafdb45f1702c..9c4c6cb11f0f1ea5c672c1d408c77856be9f0974 100644 (file)
@@ -103,6 +103,7 @@ struct radeon_info {
        bool                        has_gpu_reset_status_query;
        bool                        has_gpu_reset_counter_query;
        bool                        has_eqaa_surface_allocator;
+       bool                        has_format_bc1_through_bc7;
 
        /* Shader cores. */
        uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
index c7585b285e92b77d8f4a7c86ce892e798a479f11..675b1adbe6544a8e89bd86af08eb83ee91bdf42c 100644 (file)
@@ -1573,9 +1573,6 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen,
                                       int first_non_void)
 {
        struct si_screen *sscreen = (struct si_screen*)screen;
-       bool enable_compressed_formats = (sscreen->info.drm_major == 2 &&
-                                         sscreen->info.drm_minor >= 31) ||
-                                        sscreen->info.drm_major == 3;
        bool uniform = true;
        int i;
 
@@ -1630,7 +1627,7 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen,
        }
 
        if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
-               if (!enable_compressed_formats)
+               if (!sscreen->info.has_format_bc1_through_bc7)
                        goto out_unknown;
 
                switch (format) {
@@ -1676,7 +1673,7 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen,
        }
 
        if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
-               if (!enable_compressed_formats)
+               if (!sscreen->info.has_format_bc1_through_bc7)
                        goto out_unknown;
 
                switch (format) {
@@ -1705,7 +1702,7 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen,
        }
 
        if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
-               if (!enable_compressed_formats)
+               if (!sscreen->info.has_format_bc1_through_bc7)
                        goto out_unknown;
 
                switch (format) {
index 1eecb23d9dd0229fe36617e254805b60b3727ab2..108c1af99851504f40ccf0bedcb29712737d7008 100644 (file)
@@ -537,6 +537,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     ws->info.has_gpu_reset_status_query = false;
     ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
     ws->info.has_eqaa_surface_allocator = false;
+    ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
 
     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;