Revert "Make one check $shift(x)? only; change testcase to be 8b"

This reverts commit e2c2d784c8217e4bcf29fb6b156b6a8285036b80.

diff --git a/passes/pmgen/peepopt_shiftmul.pmg b/passes/pmgen/peepopt_shiftmul.pmg
index e1da5218291d7d9666fc5fe6dc2dc6c8f95106c6..d4748ae19e4fd9e9980cd3d777b64a094fd7bb65 100644 (file)
--- a/passes/pmgen/peepopt_shiftmul.pmg
+++ b/passes/pmgen/peepopt_shiftmul.pmg
@@ -50,9 +50,8 @@ code
        if (GetSize(const_factor_cnst) > 20)
                reject;
 
-       if (shift->type.in($shift, $shiftx))
-               if (GetSize(port(shift, \Y)) > const_factor)
-                       reject;
+       if (GetSize(port(shift, \Y)) > const_factor)
+               reject;
 
        int factor_bits = ceil_log2(const_factor);
        SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A);

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index 886c8cd9dc347c7c18f6024b77fbd6e304af2285..abee9cc0a5325e904c276ff65f419bad3a51098b 100644 (file)
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -16,7 +16,7 @@ select -assert-count 0 t:$shiftx t:* %D
 design -reset
 read_verilog <<EOT
 module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
-assign y = 1'b1 >> (w * (8'b110));
+assign y = 1'b1 >> (w * (3'b110));
 endmodule
 EOT
 
@@ -25,7 +25,7 @@ equiv_opt -assert peepopt
 design -load postopt
 clean
 select -assert-count 1 t:$shr
-select -assert-count 0 t:$mul
+select -assert-count 1 t:$mul
 select -assert-count 0 t:$shr t:$mul %% t:* %D
 
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