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Fix comment
author
Eddie Hung
<eddie@fpgeh.com>
Sat, 5 Oct 2019 04:45:31 +0000
(21:45 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Sat, 5 Oct 2019 05:31:04 +0000
(22:31 -0700)
passes/pmgen/xilinx_dsp.cc
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diff --git
a/passes/pmgen/xilinx_dsp.cc
b/passes/pmgen/xilinx_dsp.cc
index 489887207b8c7ffccc2fe0e5c2c4e3247a3cb4c3..886e01c0f32b1a32d437c5c093fd1e5b8fc04ab8 100644
(file)
--- a/
passes/pmgen/xilinx_dsp.cc
+++ b/
passes/pmgen/xilinx_dsp.cc
@@
-614,7
+614,7
@@
struct XilinxDspPass : public Pass {
xilinx_simd_pack(module, module->selected_cells());
// Match for all features ([ABDMP][12]?REG, pre-adder,
- //
(
post-adder, pattern detector, etc.) except for CREG
+ // post-adder, pattern detector, etc.) except for CREG
{
xilinx_dsp_pm pm(module, module->selected_cells());
pm.run_xilinx_dsp_pack(xilinx_dsp_pack);