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diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 3d454b63fe409bf5e3cfcc2a150410076a09d908..7f0d9d7a48151f23c985e5f49986bca56b2da4ff 100644 (file)
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -221,26 +221,13 @@ change all [GPR to FPR conversion instructions](#GPR-to-FPR-conversions)
 to instead write `+0.0` if `RA` is register `0`, at least
 allowing clearing FPRs.
 
-|  0-5   | 6-10 | 11-25 | 26-30 | 31  |
-|--------|------|-------|-------|-----|
-|  Major | FRT  | FI    | XO    | FI0 |
+`fmvis` fits well with DX-Form:
 
-The above fits reasonably well with Minor 19 and follows the
-pattern shown by `addpcis`, which uses an entire column of Minor 19
-XO. 15 bits of FI fit into bits 11 to 25,
-the top bit FI0 (MSB0 numbered 0) makes 16.
+|  0-5   | 6-10 | 11-15 | 16-25 | 26-30 | 31  | Form
+|--------|------|-------|-------|-------|-----|-----|
+|  Major | FRT  | d1    | d0    | XO    | d2  | DX-Form |
 
-    bf16 = FI0 || FI
-    fp32 = bf16 || [0]*16
-    FRT = Single_to_Double(fp32)
-
-Also worth noting, `fmvis` fits well with DX-Form:
-
-|  0-5   | 6-10 | 11-15 | 16-25 | 26-30 | 31  |
-|--------|------|-------|-------|-------|-----|
-|  Major | FRT  | d0    | d1    | XO    | d2  |
-
-    bf16 = d2 || d1 || d0
+    bf16 = d0 || d1 || d2
     fp32 = bf16 || [0]*16
     FRT = Single_to_Double(fp32)